JP2002359819A - Circuit and method for converting sequential scanning, settop box and television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sequential scanning conversion circuit which is ultimately advantageous in the cost by reducing the number of double speed conversion memories and reducing a circuit scale, and to provide a settop box, a television receiver and a sequential scanning conversion method. SOLUTION: In sequential conversion control, signals of a direct system and an interpolation system are switched alternately and read from a first memory, being a mass image memory storing a plurality of image signals of the direct and interpolation systems to be held in a second memory 3 being a buffer memory (memory for double-speed conversion) for reading. In double speed system separation processing, a signal read from the second memory 3 is separated between a luminance signal and a color signal to obtain double speed luminance signal and color signal, with respect to a standard television signal. The number of memories for double speed conversion can be reduced and the circuit scale can be reduced, without needing as many as four systems of memories for double-speed conversion by using the mass image memory 1 and a video processing circuit system, using a buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to NTSC, PAL
The present invention relates to a progressive scan conversion circuit, a set-top box, a television receiver, and a progressive scan conversion method for doubling the number of scanning lines in one field period by receiving an interlace signal such as an input signal.

[0002]

2. Description of the Related Art In recent years, demands for improving the image quality of television receivers have been increasing in the market.

[0003] The progressive scan conversion means that an interlace signal which is a standard television signal such as NTSC or PAL is input and the number of scan lines in one field period is doubled (for example, NTSC or NTSC).
In this case, the function is to scan the image sequentially from the top of the screen and display an image. In doubling the scanning line,
An image signal scanned by an original interlace signal is called a direct system signal, and an image signal displayed between scanning lines of the interlace signal is called an interpolation system signal.

A line memory or a field memory or the like is used for a progressive scan conversion circuit for converting an interlaced television signal to a non-interlaced television signal by doubling the number of scanning lines by line interpolation. As the line interpolation method, the repetitive interpolation for scanning the direct system signal again, the average interpolation for scanning the average of the upper and lower lines of the direct system signal, and the scanning line information of the field immediately preceding the field to be interpolated are performed. There are three methods of vector interpolation that also use.

[0005] As a known example of such a progressive scan conversion circuit, Japanese Patent Publication No. 7-40733 and Japanese Patent Laid-Open No. 10-126 are disclosed.
No. 749, for example. Japanese Patent Publication No. 7-40733 describes means for preventing the occurrence of line flicker and the reduction in vertical resolution that occur when performing line interpolation. Further, Japanese Patent Application Laid-Open No.
Japanese Patent Application Laid-Open Publication No. H10-157,197 discloses a progressive scan conversion device suitable for an MPEG decoder or the like, by adaptively switching an interpolation method in progressive scan conversion using information such as an image structure and a motion vector included in an MPEG2 signal. It describes that a circuit such as a motion vector detection circuit is omitted to reduce the circuit scale.

FIG. 7 shows an example of a conventional progressive scan conversion circuit. In this conventional circuit, a description will be given assuming that signals of a direct system and an interpolation system required for progressive scan conversion have already been generated in a preceding circuit.

A system luminance signal is directly input from an input terminal 11,
The interpolation system signal is supplied to the first double speed conversion memory 7, and the interpolation system luminance signal is input from the input terminal 12, and is supplied to the second double speed conversion memory 8.

On the other hand, a color signal is input directly from an input terminal 13 to a third double-speed conversion memory 9, and an interpolation color signal is input from an input terminal 14 to a fourth double-speed conversion memory.
Has given to 10.

The internal progressive scan conversion control is performed using a control signal generation circuit 22. A horizontal synchronizing signal (hereinafter, referred to as HD) is inputted from an input terminal 15, a vertical synchronizing signal (hereinafter, referred to as VD) is inputted from an input terminal 16, control data from a microcomputer 27 is inputted from an input terminal 17, and H
It is provided to the control signal generation circuit 22 together with D and VD.

The control signal generating circuit 22 generates various control signals necessary for write control and read control of the first to fourth double-speed conversion memories 7 to 10.

Basically, irrespective of the direct system signal and the interpolation system signal, for each of the double-speed conversion memories, a portion corresponding to the valid period of the input video signal is converted at a clock rate (n) locked to HD. At the time of writing and reading, reading is performed at twice the clock rate (2n) in order to perform double speed conversion.

Originally, a sequential scanning signal (called a non-interlaced signal) may be obtained by alternately reading a double-speed signal of a direct system and an interpolating signal. The same video signal is output twice for each of the double-speed lines of the system and the interpolation system, and finally the selectors 27 and 28 alternately select the direct system and the interpolation system in units of the double-speed line to obtain the sequential scan conversion signal. .

FIG. 8 is a timing chart of the double speed conversion memory control in the above conventional example. The horizontal axis indicates the passage of time, and the vertical axis indicates the increase of the memory address. Fig. 8 (a)
7 shows the state of the memory address when the direct system signal in the double speed conversion memory 7 and the double speed conversion memory 9 is written in the effective pixel period (direct system W). A1, A2, A3... Indicate the writing status of the direct system signal. FIG. 8B shows a case where the direct system signal written in FIG. 8A is read at double speed (direct system R).
This is the situation of the memory address. A1 ', A2', A3 '
.. Indicate the reading status of the direct system signal. here,
The reason why the double speed output is read twice is that the control signal generation circuit
This is for facilitating the read control and the configuration thereof.

The same applies to the double speed conversion memory control of the interpolation system signal. FIG. 8C shows a case where the interpolation system signal in the second double speed conversion memory 8 and the fourth double speed conversion memory 10 is written in the effective pixel period. This is the situation of the memory address of (interpolation system W). B
1, B2, B3,... Indicate the writing status of the interpolation system signal. FIG. 8D shows the state of the memory address when the interpolation system signal written in FIG. 8C is read at double speed (interpolation system R). .. B1 ', B2', B3 ',... 8 (b) and 8 (d), the selector 27 and the selector 28 are switched by the direct selection signal shown in FIG. 8 (e) from the control signal generating circuit 22. Thus, the progressive scan conversion signal shown in FIG.
The direct complement selection signal (e) is a selection signal for switching between the direct system and the indirect system. As for the progressive scan conversion output, each double speed output of the direct system and the interpolation system is alternately selected and A1 ', B1',
2 ′, B2 ′, A3,...

In the conventional method, as described above, the capacity of the double speed conversion memory needs at least the number of effective pixels of one line. For example, if the sampling frequency is 910fH
At (fH: horizontal scanning frequency), the capacity of the double-speed conversion memory requires 768 samples of words, and the number of double-speed conversion memories also requires four as described above.

2PRAM having two independent ports for writing and reading only for double speed conversion in one system
The use of four line memories configured as described above has a problem that the circuit scale increases and the cost increases.

[0017]

As described above, in the conventional progressive scan conversion circuit, the number of double speed conversion memories is large,
There is a problem that the circuit scale and cost increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to reduce the number of double-speed conversion memories, reduce the circuit scale, and be advantageous in cost, such as a progressive scan conversion circuit, a set-top box, and a television. It is an object of the present invention to provide a John receiver and a progressive scan conversion method.

[0019]

SUMMARY OF THE INVENTION A progressive scanning conversion circuit according to the present invention comprises a plurality of direct systems,
A first memory that stores an image signal of an interpolation system, a second memory that holds a signal read from the first memory, and a first memory that stores a horizontal and vertical synchronization signal of an image. A control signal generating circuit for generating various write and read control signals for the second memory; and a sequential conversion control circuit for generating a control signal for alternately switching and reading the direct system and interpolation system signals from the first memory. And a double-speed separation processing circuit that separates a signal read from the second memory into a luminance signal and a color signal to obtain a double-speed signal.

In the present invention, the direct-system and interpolation-system signals are alternately switched and read out from the first memory storing a plurality of direct-system and interpolation-system image signals, and stored in the second memory. Then, the signal read from the second memory is separated into a luminance signal and a chrominance signal to obtain a luminance signal and a chrominance signal which are twice as fast as the standard television signal. This makes it possible to reduce the capacity and the number of double-speed conversion memories used when performing the sequential scan conversion.

Further, the progressive scan conversion circuit according to the present invention comprises a first memory capable of storing a plurality of image signals, a second memory holding a signal read from the first memory, and an input direct system. A multiplex processing circuit for time-divisionally multiplexing a plurality of signals including a luminance signal, a direct color signal, and an internally generated interpolation signal; and holding the time-division multiplexed signal until writing to the first memory. A third memory for storing, a fourth memory for holding a signal read from the first memory, a separation processing circuit for separating a signal read from the fourth memory into various types of signals, A first interpolation line generation circuit that receives a luminance signal from the processing circuit and generates a luminance interpolation signal using a first line memory; and receives a color signal from the separation processing circuit.
A second interpolation line generation circuit that generates a color interpolation signal using a second line memory; a control signal generation circuit that generates various control signals based on horizontal and vertical synchronization signals of an image; A sequential conversion control circuit for generating a control signal for alternately switching and reading out the image signals of the direct system and the interpolation system from the first memory, and separating the signal read from the second memory into a luminance signal and a chrominance signal, A double speed system separation processing circuit for obtaining a signal.

In the present invention, an interpolation signal is generated internally, and the signal output from the first memory is converted into a necessary signal by using a fourth memory (RBUFF) and a separation processing circuit. After separation into various signals, the first and second interpolation line generation circuits obtain the field delay and the frame delay of the luminance and color signals, and use the line memory to determine the luminance,
Each color interpolation signal can be generated.

The signals of the direct system and the interpolation system are alternately switched and read out from the first memory storing a plurality of image signals of the direct system and the interpolation system, and are stored in the second memory.
The signal read from the memory is separated into a luminance signal and a chrominance signal, and a luminance signal and a chrominance signal which are twice as fast as the standard signal are obtained. This makes it possible to reduce the capacity and the number of double-speed conversion memories used when performing the sequential scan conversion.

[0024]

Embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing a progressive scan conversion circuit according to a first embodiment of the present invention. In the configuration of the present embodiment, an example will be described in which a direct system signal (brightness, color) and an interpolation system signal (brightness, color) required for the progressive scan conversion are input from the outside to realize. The direct system signal (brightness, color) is obtained, for example, by receiving a television broadcast signal at a receiving unit (not shown) and demodulating an interlaced image signal. From an interlaced direct system signal (luminance, color) demodulated by a receiving unit, an interpolation system signal required for sequential scan conversion can be generated by a well-known interpolation system signal generation unit.

In FIG. 1, a progressive scan conversion circuit has an input terminal 11 for inputting a direct system luminance signal, an input terminal 12 for inputting a direct system color signal, and an input terminal 11 for inputting an interpolation system luminance signal. An input terminal 13, an input terminal 14 for inputting an interpolation color signal, and a first memory which is a large-capacity image memory for storing a plurality of image signals (read from a third memory described later) in field units. 1, a multiplex processing circuit 21 for time-division multiplexing the four system image signals of the direct system luminance signal, the direct system color signal, the interpolation system luminance signal, and the interpolation system color signal, and a time-division multiplexed image signal. , A third memory which is temporarily stored until the data is written to the first memory.
(Write system buffer memory WBUFF) 2 and a second memory (double speed conversion read system buffer memory RBU) for temporarily holding the image signal read from first memory 1.
FF) 3, a horizontal synchronizing signal (HD), and a vertical synchronizing signal (V
D) for inputting control signals from the microcomputer 27, a terminal 17 for inputting a control signal from the microcomputer 27, and receiving signals from the terminals 15 to 17 for each circuit (including various memories). A control signal generating circuit 22 for generating a control signal; a control (alternate complement selection control) for alternately switching and reading image signals of a direct system and an interpolation system from the first memory 1; A sequential conversion control circuit 30 for controlling the separation processing circuit 23; and a double-speed separation processing circuit for separating a signal read from the second memory 3 into a luminance signal and a chrominance signal to obtain a double-speed luminance signal and a chrominance signal. 23, an output terminal 19 as an output means for finally outputting a double-speed luminance signal, and an output terminal 20 as an output means for outputting a double-speed color signal.

In the above configuration, after the sequential scan conversion,
In order to alternately output a direct signal, which is an original interlace signal, and an interpolation signal for interpolating between lines of the direct signal, the first memory 1 stores a direct signal and an interpolation signal in advance in the first memory 1. Must be stored. First memory
1 is conventionally required as a pre-stage circuit for storing a plurality of field images in advance for performing the sequential scan conversion process. In the present embodiment, an attempt is made to realize a sequential scan conversion process with a small number of memories and a small capacity by using a large-capacity image memory for video processing which is necessary even in a conventional circuit.

By the way, the direct system luminance signal input from the input terminal 11 and the direct system color signal input from the input terminal 12
Interpolated luminance signal input from input terminal 13 and input terminal 14
Since the interpolated color signals input from the multiplex processing circuit 21 may be input at the same time, each of the input signals from the input terminals 11, 12, 13, and Must be converted to an integer multiple to generate a time-division multiplexed signal. In the multiplex processing circuit 21, for example,
Four input signals each having a bit width are serially arranged for each predetermined number of clocks (for example, four clocks), input and stored in a buffer, and then, for each clock, the input signals for each of the four clocks are input for each input signal. The input 8 bits width is converted to the output of 32 bits width (so-called serial / parallel conversion) by sequentially outputting the signals in parallel to each other, and the input signals of four clocks are time-division multiplexed and output every clock.

In the third memory 2, the memory address of the time-division multiplexed image signal from the multiplex processing circuit 21 is switched according to the write enable signal from the control signal generation circuit 22 based on the HD and VD. While separating and storing each input signal.

Next, means for reading and writing image signals between another buffer memory including the third memory 2 and the first memory 1 which is a large-capacity image memory will be described.
To read and write multiple image signals at any given period,
The operation clock of the large-capacity first memory 1 is multiplied by an integer multiple of the write clock to the third memory 2 (in the present embodiment, the clock of the first memory 1 is 54 MHz,
Clock is 13.5MHz and 4 times). This allows
The number of events for accessing the large-capacity image memory 1 is secured during any given period, and the writing and reading operations are performed according to each event. It should be noted that a unit in which events of various image signals make one cycle is an event block.

Writing and reading of an image to and from a first memory 1 which is a large-capacity memory storing an image, and a third and a second memory 2 and 3 which are a plurality of front and rear write and read buffer memories. Is the event block as described above (Fig. 2
See)).

FIG. 2 shows the structure in the event block. FIG. 2A shows an operation clock of the first memory 1, and FIG. 2B shows input / output signals for reading from and writing to the first memory 1. The number of event clocks of the first write signal is determined by the conversion ratio of the bit width, the capacity of another buffer memory including the third memory 2, and the operation clock of the large-capacity image memory 1. In the present embodiment, 1
The number of clocks of the event is k, and one block, which is one cycle of a memory event, is composed of an event of various writing systems, an event of reading an image signal having the same frequency as an input signal, and an event of a double speed signal output system. are doing.

In FIG. 2, the number of clocks of the double-speed read system event is twice as many as the number of write event clocks of the direct system signal and the interpolation system signal. This is because the write signal rate of the direct system and the interpolation system is 13.5 MHz as an example.
On the other hand, the signal rate read from the second memory 3 is 27 MHz, which is twice as high, so that the write / read relationship can be maintained.

The sequential conversion read operation of the second memory 3 will be described below. In the control signal generation circuit 22, a double speed read enable signal for outputting a double speed conversion signal is generated based on the given HD, VD, and the set value from the microcomputer 27. The double speed read enable signal is supplied to the second memory inside the control signal generation circuit 22.
It is used as a signal to generate a double speed read address of 3.

FIG. 3 shows a timing chart of the first embodiment. FIG. 3A shows an input video signal, and FIGS.
The effective image period of the line period (1H) is shown. FIG.
(b) is a write enable signal from the control signal generation circuit 22 to the third memory 2. FIG. 3C shows an occurrence state of an event block serving as a source of a control signal for reading and writing the image signal from and to the first memory 1. This event block is generated based on the input horizontal synchronizing signal HD. In FIG. 3, the effective pixel period is described as 8 blocks (1BL, 2BL..., 8BL) as an example (FIG. 3).
(c)).

Next, transfer control of image signals between the large-capacity first memory 1 and the third memory 2 which is a write buffer memory will be described. In the control signal generating circuit 22, the addresses of various signals written to the third memory 2 by the write enable signal shown in FIG.
At the start point of the corresponding signal period in the event block of (c), a difference from the address read from the third memory 2 is obtained. If the difference value does not reach the predetermined value set by the microcomputer 27, the difference is calculated. As NG, control is performed to stop writing to the first memory 1 without supplying a write valid event block to the first memory 1. Thereafter, writing to the second memory 3 is performed by the address control signal generation circuit 22 in accordance with the write enable, and as a result, the address difference value exceeds a predetermined value (difference OK),
A write enable event block for the first memory 1 is generated, and writing to the first memory 1 is performed. FIG. 3D shows an address difference value in an arbitrary image signal in the third memory 2. FIG. 3E shows a write valid event block gated by the address difference control, during which the first memory 1
The writing of the image signal is performed.

On the other hand, transfer control of image signals between the first memory 1 and the second memory 3 which is a buffer memory for reading will be described. An image signal is written to the second memory 3 which is a double speed read buffer memory by the event block of FIG. 3C output from the control signal generation circuit 22. When this write operation is continued in accordance with the event block of FIG.
If the double-speed read enable of (f) is not input, the second memory 3 becomes full of the image signal to be written, and the capacity is exceeded. Therefore, control to stop the writing is required.

The write / read control to / from the second memory 2 will be described. FIG. 3G shows the difference between the write address and the read address in the second memory 3. When the address difference value exceeds a predetermined value set by the microcomputer 27 (difference NG), control to stop writing from the first memory 1 to the second memory 3 is performed, and FIG. ), The generation of the read valid event block is stopped. Thereafter, in the state where the double speed read enable is issued from the control signal generation circuit 22, reading is performed from the second memory 3, and as a result, the address difference value falls below a predetermined value (difference OK), and the first memory 3 A read valid event block to 1 is generated, and writing to the second memory 3 is performed.

By the operation shown in FIGS. 3A to 3H, a sequential scanning signal in which a luminance signal and a chrominance signal are time-division multiplexed is output from the second memory 3 which is a reading buffer memory. The direct complementation selection signal, which is a control signal for switching the area (direct system, interpolation system) of the memory 1, is obtained by counting the number of read valid event blocks in FIG. That is, it is generated by switching between low level (direct system) / high level (indirect system) with four out of eight effective blocks. FIG. 3 (i)
Shows a direct selection signal. Then, as shown in FIG. 3 (f), in synchronization with the double speed read enable output every half of the horizontal period, a double speed output of 31 kHz is alternately output from the second memory 3 to the direct system and the interpolation system. You. FIG. 3 (k) shows terminals 19 and 20.
2 shows a horizontal synchronizing signal for double-speed scanning used for a display means (display) not shown connected to.

As described above, the first memory 1, which is a large-capacity memory for storing images, and the third and second memories 2, 3, which are a plurality of preceding and succeeding write / read buffer memories.
The image writing and reading are performed on the basis of the event block (see FIG. 2) as described above. And
The control signal generating circuit 22 compares the value of the read address of the second memory 3, which is a double-speed buffer memory, with the value of the write address of the second memory 3 controlled by an event block. The various signal event enables in the event block are individually gated to generate an effective event enable so that the capacity of each signal area of the memory 3 does not exceed the capacity of each of the signal areas. It controls writing and reading to and from the memory 3.

For the above reasons, the second and third memories
The capacity of 3 and 2 can be composed of several blocks.

Next, a direct complement selection signal for switching the area (direct system, interpolation system) of the first memory 1 will be described.

In order to perform the sequential scan conversion, the first memory 1 storing the direct system signal and the interpolation system signal in a time division multiplex manner is stored.
Therefore, a control signal for alternately switching to and outputting a direct system signal and an interpolation system signal is required. The control signal generation circuit
A valid event enable (see FIG. 3 (h)) for reading a luminance signal and a chrominance signal from 22 is given to the sequential conversion control circuit 30. In the sequential conversion control circuit 30, a one-line period designated by the microcomputer 27 is provided. Number of event blocks (8 in the figure)
Of the read valid event enable (1BL to 4BL in FIG. 3 (h)), and the count values match (both are 4). (I), a direct complement selection signal as shown in FIG. 3 (i) is generated independently for the luminance signal and the chrominance signal. The details in the block will be described later with reference to FIG.

The direct complement selection signals for luminance and color output from the sequential conversion control circuit 30 are supplied to the control signal generation circuit 22 to read out the image signal from the first memory 1 and to read out the second When writing to the double speed buffer memory as the memory 3, the read address is switched based on the direct complement selection signal, and the direct signal and the interpolation signal are alternately output.

In the double-speed buffer memory, which is the second memory 3, the control signal from the control signal generating circuit 22 is used to write and read the image signal from the first memory 1 and to switch the clock when reading the image signal. It is output to the double speed system separation processing circuit 23 in the subsequent stage.

The double speed system separation processing circuit 23 takes in the image signal by the control signal from the control signal generation circuit 22 and expands the time axis independently for the luminance signal and the chrominance signal.
The double-speed luminance signal that is sequentially scanned and converted from
, And outputs a double-speed color signal that is sequentially scanned and converted.

FIG. 4 is a block diagram of the sequential conversion control circuit 30. The sequential conversion control circuit 30 includes a luminance signal type sequential conversion control circuit 100 and a color signal type sequential conversion control circuit 101. Since both of the sequential conversion control circuits have the same circuit configuration, only the luminance signal system sequential conversion control circuit will be described, and the description of the color signal will be omitted.

With the read valid event block shown in FIG. 3 (h) from the control signal generating circuit 22 as an input, the differentiating circuit 300 generates an enable signal (ENB) for the counter 302 at the next stage.

On the other hand, a field reset signal is input from the control signal generating circuit 22 as a reference of the system, and is differentiated by a differentiating circuit 301 to generate a field reset signal (VRST). 304 has been reset.

The comparison circuit 303 compares the value of the counter 302 with the value of the event block set by the microcomputer 27.
4 and the counter 302 is also cleared (CLR), whereby the output of the toggle circuit 304 is inverted at two levels (low level / high level) for each enable to generate a direct complement selection signal. Generate and control the sequential scan conversion.

As described above, even if the state of the valid event block shown in FIG. 3 (h) for controlling the first memory 1 changes, the direct complement selection signal shown in FIG. 3 (i) can be generated stably. Finally, a good progressive scan conversion signal as shown in FIG. 3 (j) can be output.

According to the first embodiment of the present invention, when performing the sequential scan conversion, the double speed conversion memory to be used is substantially only the second memory 3, and the capacity and the number are greatly reduced. can do.

The first memory 1 which is a large-capacity image memory and the second memory 3 which is a double-speed conversion buffer memory
In the control of writing to the memory, the phase of the double-speed read enable signal ensures stable direct selection even if writing to the double-speed conversion buffer memory 3 is intermittent in order to avoid area overflow of the double-speed conversion buffer memory 3. A signal can be generated.

[Second Embodiment] FIG. 5 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a progressive scan conversion circuit according to the embodiment.

In the first embodiment, a direct system signal (brightness, color) and an interpolation system signal (brightness, color) required for progressive scan conversion are used.
In the configuration of the second embodiment, the direct system signal (luminance, luminance,
An example is shown in which only color (color) is input from the outside, and based on this, an interpolation system signal (luminance, color) is internally generated to realize progressive scan conversion.

In FIG. 5, in order to internally generate interpolation signals (luminance and color), a fourth memory (read buffer memory) 4 and first and second memories 4 , Line memories 5 and 6, a separation processing circuit 24, and first and second interpolation line generation circuits 25 and 26.

As a feature, the first memory is read by a valid event block read from the control signal generation circuit 22.
The signal output from 1 is written into the fourth memory 4 using the control signal output from the control signal generation circuit 22. Then, the read address to the fourth memory 4 is switched to output an image signal from the fourth memory 4, separated into various signals by a separation processing circuit 24, and a field delay required for generating an interpolation system. Various signals such as signals (including motion detection signals) are obtained.

The first interpolation line generation circuit 25 receives the field delay signal and the frame delay signal of the luminance signal from the separation processing circuit 24, and uses the first line memory 5 for the field delay signal. And one line (1
H) Obtain a delayed signal, and finally generate an interpolation signal of a luminance signal in the first interpolation line generation circuit 25 according to the motion detection signal from the control signal generation circuit 22.

Similarly, in the second interpolation line generation circuit 26, the field delay and the frame delay of the color signal from the separation processing circuit 24 are input, and the field delay signal is converted by using the second line memory 6. , A signal delayed by one line (1H), and finally a second interpolation line generation circuit 26
Within, a color signal interpolation signal is generated according to the motion detection signal from the control signal generation circuit 22.

The first and second interpolation line generation circuits 25 and 26
Each interpolation signal generated in is given to the multiplex processing circuit 21,
It is time-division multiplexed with the direct luminance and color signals and stored in the large-capacity first memory 1 via the third memory (write buffer memory) 2.

In the subsequent processing, as in the first embodiment, a direct signal and an interpolation signal are sequentially switched from the first memory 1 by the direct complement selection signal, and the signal is switched via the double speed system separation processing circuit 23. Then, a double-speed luminance signal sequentially scanned and converted from the terminal 19 and a double-speed color signal sequentially scanned and converted from the terminal 20 are output.

In the second embodiment of the present invention, as in the first embodiment, when performing the sequential scan conversion, the double speed conversion memory used is substantially only the second memory 3. The capacity and the number can be reduced well.

The first memory 1 which is a large-capacity image memory and the second memory 3 which is a double-speed conversion buffer memory
In the control of writing to the memory, the phase of the double-speed read enable signal ensures stable direct selection even if writing to the double-speed conversion buffer memory 3 is intermittent in order to avoid area overflow of the double-speed conversion buffer memory 3. A signal can be generated.

Further, after the signal output from the first memory 1 is separated into various necessary signals by using the read buffer memory 4 and the separation processing circuit 24, the first and second signals are separated.
The interpolation line generation circuits 25 and 26 obtain the field delay signal and the frame delay signal of the luminance and chrominance signals, and can generate the luminance and color interpolation signals.

FIG. 6 is a block diagram showing a progressive scan conversion television receiver according to the present invention.

In FIG. 6, reference numeral 41 denotes an antenna, and reference numeral 42 denotes a receiving circuit for receiving a television broadcast wave, extracting a baseband composite video signal, and outputting it as a direct system luminance signal and a direct system color signal. The composite video signal is an interlaced video signal. The composite video signal from the receiving circuit 42 is supplied to a sync separation circuit 45,
Are supplied to the sequential scan conversion circuit 50.

The progressive scan conversion circuit 50 receives the interlaced luminance signal and the color signal from the reception circuit 42 and generates a known interpolation system signal signal for generating an interpolation system luminance signal and an interpolation system color signal. The interlaced luminance signal and the interpolated luminance signal and the interpolated luminance signal and the interpolated luminance signal generated by the interpolated signal generation means are inputted from the circuit 42, and the non-interlaced signal is inputted by performing the sequential scan conversion processing. And a conversion circuit for outputting a double-speed luminance signal and a double-speed color signal as shown in FIG. Alternatively, the progressive scan conversion circuit 50
Is composed of a conversion circuit as shown in FIG. 5 which receives an interlaced luminance signal and a color signal from the receiving circuit 42, performs a sequential scan conversion process, and outputs a non-interlaced double-speed luminance signal and a double-speed color signal. Have been.

The non-interlaced double-speed luminance signal and double-speed chrominance signal output from the progressive scan conversion circuit 50 are converted into non-interlaced RGB signals via a picture tube driving circuit 43 to form a picture tube 44 as a display means. One field supplied to the axial cathode is displayed as a non-interlaced image composed of, for example, 525 scanning lines.

The synchronization separation circuit 45 converts the interlaced composite video signal from the reception circuit 42 into a horizontal synchronization signal (15.75 kHz).
And the vertical synchronizing signal (60 Hz). Horizontal deflection circuit 46
Inputs a horizontal synchronizing signal of, for example, 15.75 kHz from the synchronizing separation circuit 45, and outputs a horizontal synchronizing signal for progressive scanning (non-interlace).
A horizontal synchronizing signal having a double frequency (31.5 kHz) is generated, and a horizontal deflection scanning signal based on the horizontal synchronizing signal having the double frequency is generated and supplied to the horizontal deflection coil of the deflection yoke. In addition, the vertical deflection circuit 47 receives 60
A vertical synchronization signal of Hz is input, a vertical deflection scanning signal is generated, and supplied to the vertical deflection coil of the deflection yoke. As a result, the non-interlaced signal from the progressive scan conversion circuit 50 is sequentially scanned for each field with twice the number of scanning lines as interlaced.

Incidentally, the progressive scan conversion circuit according to the present invention is shown in FIG.
FIG. 1 including a receiving unit for receiving and demodulating a television signal and an interpolation signal generating means in addition to a progressive scan conversion television receiver as described above (provided that it has an interpolation signal generating means). Alternatively, the present invention can be applied to a set-top box including a progressive scan conversion circuit as shown in FIG. 5 and an output terminal as output means for outputting a non-interlaced double-speed signal (luminance, color).

[0070]

As described above, according to the present invention, it is possible to reduce the capacity and the number of double-speed conversion memories to be used in performing the sequential scan conversion, to reduce the circuit scale, and to be advantageous in terms of cost. It is possible to realize a progressive scan conversion circuit, a set-top box, a television receiver, and a progressive scan conversion method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a progressive scan conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a memory event of a first memory in the embodiment of FIG. 1;

FIG. 3 is a timing chart showing the operation of the embodiment of FIG. 1;

FIG. 4 is a block diagram of a sequential conversion control circuit according to the embodiment of FIG. 1;

FIG. 5 is a block diagram showing a progressive scan conversion circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a progressive scan conversion television receiver according to the present invention.

FIG. 7 is a block diagram showing a conventional progressive scan conversion circuit.

FIG. 8 is a timing chart showing the operation of the conventional example of FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st memory (large capacity image memory) 2 ... 3rd memory (write system buffer memory) 3 ... 2nd memory (double speed conversion read system buffer memory) 4 ... 4th memory (read system buffer memory) ) 5, 6 ... line memories 11 to 17 ... input terminals 19, 20 ... output terminals 21 ... multiplex processing circuit 22 ... control signal generation circuit 23 ... double speed system separation processing circuit 24 ... separation processing circuit 25 ... first interpolation line generation Circuit 26: second interpolation line generation circuit 27: microcomputer 30: sequential conversion control circuit

Continued on the front page F-term (reference) 5C057 AA06 AA11 BA02 BA11 BB03 DA10 EC01 ED03 EH03 EH10 EL01 GG01 GJ09 5C063 AA01 AA06 BA03 BA04 BA08 BA09 CA01 CA03 CA16

Claims (11)

[Claims] 1. A first memory for storing a plurality of direct-system and interpolation-system image signals, a second memory for storing signals read from the first memory, and horizontal and vertical synchronization of images. A control signal generating circuit for generating various control signals for writing and reading of the first and second memories based on a signal; and for alternately switching and reading signals of a direct system and an interpolation system from the first memory. A sequential conversion control circuit that generates the control signal of the above, and a double speed system separation processing circuit that separates a signal read from the second memory into a luminance signal and a color signal to obtain a double speed signal. Scan conversion circuit. 2. A receiving section for receiving a television broadcast signal and reproducing an interlaced image signal, and an interpolating signal required for sequential scan conversion from the interlaced direct image signal reproduced by the receiving section. , A first memory capable of storing a plurality of image signals, a second memory holding a signal read from the first memory, the reception unit and the interpolation A multiplex processing circuit for time-division multiplexing a plurality of direct signals and interpolation signals respectively input from the system signal generating means; and a third circuit for holding the time-division multiplexed signals until the signals are written to the first memory. A control signal generating circuit for generating various control signals based on the horizontal and vertical synchronizing signals of the image; and directly and interpolatively reading the signals from the first memory. Conversion control circuit for generating a control signal for the same, a double-speed separation processing circuit for separating a signal read from the second memory into a luminance signal and a chrominance signal to obtain a double-speed signal, Output means for extracting a double-speed luminance signal and a double-speed color signal as outputs. 3. A receiving unit for receiving a television broadcast signal and reproducing an interlaced image signal, and an interpolating signal required for sequential scan conversion from the interlaced direct image signal reproduced by the receiving unit. , A first memory capable of storing a plurality of image signals, a second memory holding a signal read from the first memory, the reception unit and the interpolation A multiplex processing circuit for time-division multiplexing a plurality of direct signals and interpolation signals respectively input from the system signal generating means; and a third circuit for holding the time-division multiplexed signals until the signals are written to the first memory. A control signal generating circuit for generating various control signals based on the horizontal and vertical synchronizing signals of the image; and directly and interpolatively reading the signals from the first memory. Conversion control circuit for generating a control signal for the same, a double-speed separation processing circuit for separating a signal read from the second memory into a luminance signal and a chrominance signal to obtain a double-speed signal, And a display means for inputting a double-speed luminance signal and a double-speed color signal and displaying the signals as progressively scanned video signals. 4. A first memory capable of storing a plurality of image signals, a second memory holding a signal read from the first memory, an input direct luminance signal, a direct color signal, A multiplex processing circuit for time-division multiplexing a plurality of signals including an internally generated interpolation signal; a third memory for holding the time-division multiplexed signal until writing to the first memory; A fourth memory for holding a signal read from the first memory, a separation processing circuit for separating the signal read from the fourth memory into various types of signals, and receiving a luminance signal from the separation processing circuit A first interpolation line generation circuit for generating a luminance interpolation signal using a first line memory, and a color interpolation system signal for receiving a color signal from the separation processing circuit and using a second line memory The first to generate An interpolating line generating circuit, a control signal generating circuit for generating various control signals based on horizontal and vertical synchronizing signals of an image, and an image signal of a direct system and an interpolating system are alternately read from the first memory. Conversion control circuit for generating a control signal for generating a double-speed signal for separating the signal read from the second memory into a luminance signal and a chrominance signal to obtain a double-speed signal. Scanning conversion circuit. 5. A receiving section for receiving a television broadcast signal and reproducing an interlaced image signal, a first memory capable of storing a plurality of image signals, and holding a signal read from the first memory. A second memory that performs time division multiplexing of a plurality of signals including a direct system luminance signal, a direct system color signal, and an internally generated interpolation system signal input from the receiving unit; and the time division multiplexing. A third memory for holding the read signal until it is written to the first memory, a fourth memory for holding a signal read from the first memory, and a signal read from the fourth memory A first interpolation line generation circuit that receives a luminance signal from the separation processing circuit and generates a luminance interpolation signal using a first line memory; A second interpolation line generation circuit that receives a color signal from the separation processing circuit and generates a color interpolation system signal using a second line memory; and various control signals based on the horizontal and vertical synchronization signals of the image. A control signal generating circuit for generating a control signal for generating a control signal for alternately switching and reading the direct-system and interpolating-system image signals from the first memory; A double-speed system separation processing circuit for separating a signal into a luminance signal and a color signal to obtain a double-speed signal; and output means for extracting a double-speed luminance signal and a double-speed color signal from the double-speed system separation processing circuit as outputs. A set-top box characterized by: 6. A receiving section for receiving a television broadcast signal and reproducing an interlaced image signal, a first memory capable of storing a plurality of image signals, and holding a signal read from the first memory. A second memory that performs time division multiplexing of a plurality of signals including a direct system luminance signal, a direct system color signal, and an internally generated interpolation system signal input from the receiving unit; and the time division multiplexing. A third memory for holding the read signal until it is written to the first memory, a fourth memory for holding a signal read from the first memory, and a signal read from the fourth memory A first interpolation line generation circuit that receives a luminance signal from the separation processing circuit and generates a luminance interpolation signal using a first line memory; A second interpolation line generation circuit that receives a color signal from the separation processing circuit and generates a color interpolation system signal using a second line memory; and various control signals based on the horizontal and vertical synchronization signals of the image. A control signal generating circuit for generating a control signal for generating a control signal for alternately switching and reading the direct-system and interpolating-system image signals from the first memory; A double-speed system separation processing circuit for separating a signal into a luminance signal and a color signal to obtain a double-speed signal, and a double-speed luminance signal and a double-speed color signal from the double-speed system separation processing circuit are input and displayed as a progressively scanned video signal. A television receiver, comprising: display means. 7. The second memory capacity is a pixel number significantly smaller than an effective horizontal pixel number for one block of an event which is a minimum unit for reading and writing various image signals with the first memory. 5. The progressive scan conversion circuit according to claim 1, wherein the progressive scan conversion circuit comprises a capacity of a plurality of blocks. 8. The method according to claim 1, wherein a direct complement selection signal output from the sequential conversion control circuit is generated based on the number of times of control of writing an image signal from the first memory to the second memory. 5. The progressive scan conversion circuit according to 1 or 4. 9. The progressive scan conversion circuit according to claim 1, wherein a plurality of image signals are time-division multiplexed and processed when writing or reading to or from said first memory. 10. A sequential conversion step of alternately switching and reading direct system and interpolation system signals from a first memory storing a plurality of direct system and interpolation system image signals, and storing the signals in a second memory. Separating the signal read from the second memory into a luminance signal and a chrominance signal to obtain a luminance signal and a chrominance signal twice as fast as the standard television signal. Scanning conversion method. 11. A multiplex processing step of time-division multiplexing a plurality of signals including an input direct-system luminance signal, a direct-system chrominance signal, and an internally generated interpolation-system signal; A step of holding the image signal in a memory until the image signal is written in a first memory capable of storing the signal; a step of writing the time-division multiplexed signal in the first memory; A second holding step of holding a signal read from the first memory storing an image signal, a separation processing step of separating the signal read from the second holding step into various types of signals, Receiving a luminance signal from the processing step and generating a luminance interpolation system signal using a first line memory;
An interpolation line generation step of receiving a color signal from the separation processing step and generating a color interpolation system signal using a second line memory; A sequential conversion step of alternately switching and reading direct system and interpolation system signals from the first memory storing system image signals, and storing the signals in the second memory; and a signal read from the second memory. A double speed system separation processing step of obtaining a double speed signal by separating into a luminance signal and a color signal.