JP2951669B2 - Video signal processing device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a scanning line number conversion device for converting an interlaced television signal into a non-interlaced signal,
Also, the present invention relates to a down-converter device to which the same is applied and a two-screen television receiver incorporating the down-converter device.

2. Description of the Related Art A scanning line number conversion device for appropriately processing an interlaced input television signal to obtain an output television signal having a different number of scanning lines from an input signal is generally included in various devices embodying the purpose. It is handled in form. Examples of the device embodying such a purpose include a two-screen television receiver (for example, see Nikkei Electronics, April 14, 1980, JP-B-59-37913, JP-A-62-269482, and the like). ), A high-definition / NTSC down-converter device (see, for example, Japanese Patent Application No. 1-120128).

These devices all include a scanning line number conversion device. Such a scanning line number conversion device is configured according to the intended use of the included device, but is generally configured so that the number of scanning lines of the output signal is smaller than the number of scanning lines of the input signal. It is.

First, a related art of such a scanning line number conversion device will be described.

A scan line can generally be interpreted as a vertical sample of a two-dimensional sample of a television screen. Therefore, the operation of reducing the number of scanning lines is equivalent to the operation of reducing the vertical sampling frequency of the television screen. Such an operation can be realized by the operation of the following two components.

That is, a band-limiting filter that limits the vertical spatial frequency component of the television screen to half or less of the reduced vertical sampling frequency, and a scan that reduces the vertical sampling frequency of the television screen by thinning out the scanning lines. This is a line thinning circuit. This operation completely obeys the sampling theorem, and the principle of operation is self-evident.

FIG. 2A shows the scanning line position for each field f1, f2,... Of the interlace signal. In the figure, a mark “○” represents a scanning line, and the position is shifted by one line in the vertical direction for each field. FIG. 2B shows the scanning line position for each field of the non-interlace signal. In the figure, "○"
Marks, “X” marks indicate scanning lines, “O” marks are scanning lines corresponding to interlaced signals, and “X” marks are scanning lines appropriately created by interpolating from interlaced signals. Scan lines are present at the same position in the field.

In FIG. 2, the horizontal axis indicates the time direction in units of the field period, and the vertical axis indicates the vertical direction in units of the scanning line interval.

FIG. 3A shows a basic configuration of an apparatus for inputting such interlaced signals and converting the number of scanning lines.

The signal applied to the input terminal 500 is band-limited by the vertical spatial frequency limiting low-pass filter 501, and then guided to the thinning circuit 502. In the thinning circuit 502, the scanning lines are thinned as shown in FIG. B, and a scanning line signal corresponding to the mark “x” is output from the output terminal 503.

In FIG. 3B, “○” indicates a scanning line corresponding to an input signal, and “×” indicates a scanning line corresponding to an output signal. Also, Represents the tap range of the vertical spatial frequency limiting low-pass filter.

The television signal input to such a scanning line number conversion device is an interlaced signal. Therefore, the output signal with the reduced number of scanning lines shown in FIG. 3B is also interlaced.

By the way, in a device including such a scanning line number conversion device that outputs such a signal, the signal is further processed according to the purpose of use.

In this case, since the signals to be handled are interlaced, it is often necessary to determine the interlace rank using a field determination unit. That is, in the prior art,
Field determination is performed on the interlaced signal in this manner, and subsequent signal processing is performed based on the result of the field determination.

In the following, the reason why field determination is necessary for signal processing will be described with reference to the above two examples.

 First, a two-screen TV will be described as an example.

The basic structure of a two-screen TV is Nikkei Electronics
It is described in the April 14, 1980 issue. That is, an image memory is provided for absorbing the time difference between the video signal for the main screen and the video signal for the sub-screen, the video signal for the sub-screen is written into the image memory in synchronization with the synchronization, and the video signal for the main screen is By reading out according to the synchronization, the child screen is displayed at a predetermined position on the main screen.

The two-screen television having such a configuration has two technical problems. In the related art, a field determination unit is used to solve these problems.

All of these problems occur because the signal phases of the video signal for the main screen and the video signal for the sub-screen generally do not match.

First, when the interlace relationship between the video signal for the main screen and the video signal for the sub-screen does not match, the above-described image memory is generally controlled on a field-by-field basis. The problem that the interlacing relation of the screen is reversed (the problem of inadequate interlacing)
There is.

When the interlace relationship is reversed in this way, severe line flicker, double image disturbance, and the like occur on the child screen.

Second, when the vertical synchronization phase of the video signal for the parent screen and the video signal for the child screen does not satisfy a certain relationship, the content of the video signal for the child screen is read during the reading of the video signal for the child screen from the image memory described above. There is a problem (border problem) that the next field information is rewritten and images of different fields are displayed above and below the child screen.

When images of different fields are displayed on the upper and lower sides of the sub-screen in this way, especially in the case of a moving image, a scanning line on a boundary line is clearly observed, which causes unsightly disturbance. Further, since the interlace relationship is inverted above and below the boundary line, not only the scanning line on the boundary line is observed, but also the first problem described above occurs at the same time. That is, a normal image can be obtained only on one of the upper and lower sides of the boundary line, and on the other hand, line flicker, double image disturbance, and the like occur.

These two problems are basic problems that need to be solved in order to improve the image quality of a two-screen television, and a solution using a field determination unit has been conventionally proposed.

First, regarding the first problem, the fields of both the video signal for the main screen and the video signal for the child screen are determined,
Based on the field determination result of the video signal for the child screen, the video signal for the child screen is written to a predetermined area of the image memory, while an appropriate start is performed based on the field determination result of the video signal for the parent screen. It has been proposed that a video signal for a small screen is read out from the phase, thereby making the interlace relationship between the video signal for the main screen and the video signal for the small screen coincide (see Japanese Patent Publication No. 59-37913).

Next, with respect to the second problem, an overtaking prevention circuit is provided which divides the image memory into four areas, allocates two areas each for the first and second fields, and controls so that reading and writing are not performed simultaneously in the same area. Thus, it has been proposed to prevent so-called overtaking in which the contents are rewritten to the next field information while the video signal for the small screen is being read out from the image memory (Japanese Patent Application Laid-Open No. Sho 62-62). 269482).

That is, based on the field determination result of the video signal for the child screen, the video signal for the child screen is written to a predetermined area of the image memory. On the other hand, the overtaking prevention circuit determines the field of the video signal for the main screen, and determines the video signal for the child screen from the first of the two areas in which the field information that matches the determination result is written. Is read. As a result, reading and writing are performed in each area of the image memory on a first-in first-out basis, and reading and writing of field information always precedes reading, so that overtaking can be prevented as described above.

As described above, the first and second problems have been individually solved by using the field determination means. Also, the second
If the control function for matching the interlace relationship between the video signal for the main screen and the video signal for the child screen shown in the first means for solving the problem is added to the overtaking prevention circuit in the method for solving the problem of Can be solved at the same time.

As described above, the field determination means is indispensable for the two-screen television technology.

Next, a high definition / NTSC down converter device will be described as an example.

This device uses an interlaced HDTV signal of 1125 scanning lines per frame at a field rate of 60.00 Hz and converts it to a field rate of 59.94 Hz and one scanning line.
This is a device for converting into 525 interlaced television signals per frame.

Therefore, the device has two points. Frame rate conversion and scanning line number conversion.

Among them, the problem associated with the frame rate conversion is considered to be the same as the problem associated with the phase adjustment between the parent and the child described in the section of the two-screen television. That is, the occurrence of a boundary problem due to overtaking is expected.

However, this problem can be solved by using a method described in Japanese Patent Application Laid-Open No. Sho 62-269482 and applying a field determination means.

However, most of the currently provided down converters do not perform frame rate conversion. Therefore, although it is pointed out that a boundary problem will occur when frame rate conversion is performed in the future, the current situation is that no problem to be solved has occurred.

On the other hand, the conversion of the number of scanning lines is described in Japanese Patent Application No.
It is embodied in No. 28 etc.

The device will be described. The apparatus includes a field determination unit that determines whether a current field is an even field or an odd field with respect to an input signal, and the number of scanning lines of the odd field and the even field of the interlaced video signal is 525. Scanning line number conversion means, and position adjustment means for adjusting one position of the odd field and even field scanning line signals output from the conversion means to the other position.
It acts to convert to 525 non-interlaced television signals per frame.

Since the signal output from the scanning line number conversion means is an interlaced signal, the scanning line position differs for each field. For this reason, the apparatus is configured to prevent the occurrence of line flicker by acting to match the scanning line position of one field to the other based on the result of field determination.

Here, the field determination means is one of the indispensable elements for preventing line flicker from occurring in the apparatus.

As described above with respect to the two examples, in an apparatus including a scanning line number conversion apparatus, in the related art, the field determination unit is used as an essential unit for achieving the purpose.

[Problems to be Solved by the Invention] By the way, if the field determination unit is configured as described above and operates properly, the scanning line number conversion device and the device including them can be operated without any problem. Problems can be prevented beforehand.

However, the device may not operate well, for example, when a reproduced video signal from a home VTR is used.

The reason for this is that the field determination means used for solving the problem may malfunction with respect to the reproduced video signal of the home VTR.

The reason why the field determination unit malfunctions with respect to the reproduced video signal of the home VTR is that noise due to head switching is mixed in the vicinity of the vertical synchronization signal. The field determination means generally determines the field order by comparing the phases of the horizontal synchronization signal and the vertical synchronization signal. Therefore, if noise is mixed near the vertical synchronization signal as described above, the field determination operation may be erroneously performed. is there. Such malfunctions occur with high probability during special playback such as picture search or slow playback.

Such malfunctions occur not only with respect to a reproduced video signal of a home VTR, but also with respect to a video signal from a still image photo player or a video game machine. The reason why a malfunction occurs with respect to the video signal from these is that the output video signal itself is not originally interlaced, not the noise as described above.

Generally, the operation of the field determination means for a non-interlaced video signal cannot be defined at all. For example, it is completely indeterminate whether to continuously output the judgment output of one of the first and second fields, or to output the judgment output of the first and second fields irregularly. When the above-described first and second problem solving methods are used for such an output, there is an equal probability that the problem is solved effectively and that the problem is not solved. That is, the problem may not be effectively solved.

Considering the malfunction of the field determination means, there is a limit to signal processing relying on the field determination means as described above.

The above is summarized as follows. That is, the field determination means is used as an indispensable means for achieving the purpose of use in the conventional scanning line number conversion apparatus and the apparatus including the same. However, the field determination unit may malfunction, and the erroneous determination hinders the entire use purpose of the device including the scanning line number conversion device.
They appear, for example, in the form of line flicker.

Such a problem can be avoided if the output signal of the scanning line number conversion device can be a non-interlace signal. This is because a non-interlaced signal originally has no concept of a field, and therefore it is not necessary to introduce a field determination unit even in a device including a scanning line number conversion device.

Therefore, in the present invention, first, a scanning line number conversion device capable of obtaining a non-interlaced output signal without using a field determination unit is configured.

Secondly, as a device including the scanning line number conversion device, a down converter device that does not need to use a field determination unit is configured.

[Means for Solving the Problems] To solve the above problems, a video signal processing apparatus according to the invention according to claim 1, wherein a number of lines for counting the number of scanning lines of one frame of an interlaced input video signal is provided. Counting means, each having a plurality of weighted averaging means for weighted averaging over one or more scanning lines of the input video signal,
This is a video signal processing device that reduces the number of scanning lines in one frame of an input video signal and outputs it as a non-interlaced signal. The weighted averaging means configures each of the fields of the input video signal in order to compensate for a difference in position between the scanning line that forms each of the fields of the input video signal and each of the scanning lines of the non-interlaced signal. As many as the number required to generate the video signal of each scanning line of the non-interlace signal from the scanning lines are provided. The video signal processing apparatus includes a thinning circuit for selectively selecting and outputting one of a plurality of weighted averaging means for each scanning line of an input video signal in accordance with the number of scanning lines counted by the line number counting means. Has,
The thinning-out circuit determines an input video signal in the frame based on the order of selecting outputs of the plurality of weighted averaging means, which is determined for the frame according to the number of scanning lines of one frame counted by the line number counting means. And selecting and outputting the outputs of a plurality of weighted averaging means alternatively for each scanning line.

According to a second aspect of the present invention, there is provided a video signal processing apparatus, comprising: a line number counting means for counting the number of scanning lines in one frame of an interlaced input video signal;
A plurality of weighted averaging means for performing weighted averaging over more than one scanning line, wherein the number of scanning lines in one frame of the input video signal is reduced and output as a non-interlaced signal; A thinning circuit for selectively selecting and outputting one of a plurality of weighted averaging means for each scanning line of the input video signal in accordance with the number of scanning lines counted by the means. The weighted averaging means includes first weighted averaging means for weighing the input video signal over two scanning lines, and second weighted averaging means for weighing the input video signal over three scanning lines. When the number of lines in one frame of the input video signal counted by the line number counting means is an even number, the thinning circuit performs 3n, 3n + 1, 3n + 2nd (n is a positive integer) for each field of the input video signal. Forming two scanning line signals from the scanning line signals,
These signals are assigned to the scanning line signals of each field of the non-interlaced signal. In the 3nth line, the current scanning line signal and the previous scanning line signal are respectively
The scanning line signal of the non-interlaced signal added at a ratio of 1/2 is used. In the 3n + 1st line, the scanning line signal of the interlaced signal is not formed. In the 3n + 2nd line, the current scanning line signal, The one-line preceding scanning line signal and the two-line preceding scanning line signal are added at a ratio of 1/4, 1/2, and 1/4, respectively, to obtain a scanning line signal of a non-interlaced signal. If the number of lines in the frame is 6k + 3 (k is a positive integer), control is repeated every three lines in each frame period with reference to a frame pulse obtained by dividing the vertical synchronization signal by 1/2. The scanning line signal of the non-interlaced signal is formed, and in the 3nth line from the frame pulse, the current scanning line signal and the previous scanning line signal are added at a rate of 1/2, respectively, and the non-interlaced signal is added. No scanning line signal of the non-interlace signal is formed on the (3n + 1) th line, and the current scanning line signal, the previous scanning line signal, and the two lines on the (3n + 2) th line. The previous scan line signals are 1/4, 1/2 and 1 /
The signal is added at a ratio of 4 to be a scanning line signal of a non-interlaced signal, and the number of lines of one frame of the input video signal is 6k.
If +1 (k is a positive integer), the vertical synchronization signal is
The control is made different between the field where the frame pulse obtained by dividing by 1/2 exists and the field where the frame pulse does not exist, and the control is repeated every three lines to form the scanning line signal of the non-interlace signal, In the field where the frame pulse exists, the current scan line signal, the scan line signal one line before and the scan line two lines before in the 3nth line from the frame pulse are 1/4 and 1 respectively.
Are added at a ratio of / 2 and 1/4 to form a scanning line signal of a non-interlaced signal.
No scanning line signal of non-interlace signal is formed and 3n
In the + 2nd line, the scanning line signal of the preceding line and the scanning line signal of the preceding line are added at a ratio of 1/2, respectively, to form a scanning line signal of a non-interlace signal, and a field in which no frame pulse exists is provided. In the 3n-th line from the frame pulse, the current scanning line signal and the previous scanning line signal are each added at a rate of 1/2 to form a scanning line signal of a non-interlaced signal, and the 3n + 1th scanning line signal is formed. In the line, the scanning line signal of the non-interlace signal is not formed, and in the 3n + 2nd line, the current scanning line signal, the previous scanning line signal, and the previous scanning line signal are 1/4, 1 respectively. / 2 and 1 /
4 to form a scanning line signal of a non-interlaced signal. In the 3n + 1-th line of the field where the frame pulse exists, the current scanning line signal and 1
The scanning line signal of the non-interlace signal is formed from the scanning line signal before the line, the scanning line signal of the non-interlace signal is not formed in the 3n + 2nd line, and the number of lines of one frame of the input video signal is 6k + 5. In some cases, the control is made different between the field where the frame pulse obtained by dividing the vertical synchronization signal by 1/2 and the field where the frame pulse does not exist, and the control is repeated every three lines, and the non-interlaced In the field where the scanning line signal of the signal is formed and the frame pulse is present, in the 3nth line from the frame pulse, the current scanning line signal and the previous scanning line signal are added at a rate of 1/2 each. A scanning line signal of a non-interlaced signal is formed, and a scanning line signal of a non-interlaced signal is formed on the (3n + 1) th line. On the 3n + 2th line, the current scanning line signal, the previous scanning line signal and the previous scanning line signal are added at the ratios of 1/4, 1/2 and 1/4, respectively. In a field in which a scanning line signal of a non-interlace signal is formed and a frame pulse does not exist, the current scanning line signal, the previous scanning line signal, and the scanning line signal two lines before in the 3nth line from the frame pulse. But 1/4, 1/2 and 1 /
The scanning line signal of the non-interlaced signal is formed by adding at a ratio of 4. The scanning line signal of the non-interlaced signal is not formed in the (3n + 1) th line, and the scanning line signal of the preceding line is formed in the (3n + 2) th line. The signal and the scanning line signal two lines before are added at a ratio of 1/2, respectively, to form a scanning line signal of a non-interlaced signal. In the 3n + 1st line of the field where no frame pulse exists, the current scanning line is A scanning line signal of a non-interlace signal is formed from a signal and a scanning line signal of one line before, and a scanning line signal of a non-interlace signal is not formed in the (3n + 2) th line.

According to a third aspect of the present invention, there is provided a video signal processing apparatus, comprising: a line number counting means for counting the number of scanning lines in one frame of an interlaced input video signal;
A plurality of weighted averaging means for performing weighted averaging over more than one scanning line, wherein the number of scanning lines in one frame of the input video signal is reduced and output as a non-interlaced signal; A thinning circuit for selectively selecting and outputting one of a plurality of weighted averaging means for each scanning line of the input video signal in accordance with the number of scanning lines counted by the means. When the number of scanning lines of one frame counted by the line number counting means is an even number, the thinning circuit assigns the scanning line signals of any field of the video signal to the scanning line signals of each field of the non-interlace signal as they are. When the number of lines in one frame of the input video signal is 2n + 1, the vertical synchronizing signal is
(A) In each frame period, the first n scanning line signals of the input video signal are directly assigned to the scanning line signals of one field of the non-interlace signal with reference to the frame pulse obtained by frequency division. Next, an interpolated scanning line signal is formed by using the remaining (n + 1) scanning line signals of the input video signal so that the scanning lines exist at the same positions as the n scanning lines. A process, which is assigned to the scanning line signal of the other field of the non-interlace signal, is performed in each frame period.

According to a fourth aspect of the present invention, there is provided a video signal processing apparatus, comprising: a line number counting means for counting the number of scanning lines in one frame of an interlaced input video signal;
A plurality of weighted averaging means for performing weighted averaging over more than one scanning line, wherein the number of scanning lines of one frame of the input video signal is reduced and output as a non-interlaced signal; And a thinning circuit for selecting and outputting one of a plurality of weighted averaging means for each scanning line of the input video signal in accordance with the number of scanning lines counted by (1). When the number of scanning lines of one frame counted by the line number counting means is an even number, the thinning circuit converts the scanning line signal of any field of the input video signal into the scanning line signal of each field of the non-interlace signal as it is. When the number of lines in one frame of the input video signal is 2n + 1 (n is a positive integer), (a) the input video signal is determined based on the frame pulse obtained by dividing the vertical synchronization signal by 1/2. The first n scanning line signals of the signal are directly assigned to the scanning line signals of one field of the non-interlace signal, and (b) subsequently, the remaining n + 1 scanning line signals of the input video signal are used, n
The interpolated scanning line signal is formed so that the scanning line is present at the same position as the main scanning line, and the interpolated scanning line signal is assigned to the scanning line signal of the other field of the non-interlaced signal. The video signal is arithmetically averaged every two lines to reduce the number of scanning lines to half, and the processing is performed in each frame period.

A video signal processing apparatus according to a fifth aspect of the present invention, in addition to the configuration of the first aspect, further includes a frame memory capable of performing writing and reading of signals and controlling writing and reading asynchronously, Write control means for starting writing to the field portion after reading of the signal for one field from the frame memory is completed, and writing the video signal output from the thinning circuit to the frame memory. It is characterized by

According to a sixth aspect of the present invention, in addition to the configuration of the fifth aspect, the video signal processing apparatus reads a signal from the frame memory in synchronization with a second video signal different from the input video signal. It is characterized by putting out.

According to a seventh aspect of the present invention, in addition to the structure of the sixth aspect, a function for storing and switching a plurality of sets of a clock frequency, a write range, and a read range of the frame memory. Switching means is further provided, and the clock frequency, the writing range, and the reading range can be changed by selecting one set from a plurality of sets of the clock frequency, the writing range, and the reading range.

[Operation] According to the invention described in claim 1, the output of the plurality of weighted averaging means determined in the frame according to the counted number of scanning lines in one frame is selected in the frame. The outputs of a plurality of weighted averaging means can be alternatively selected for each scanning line of the input video signal and output as a non-interlaced signal. That is,
A non-interlaced signal is generated by thinning out a video signal without performing field determination on an input interlaced video signal, thereby eliminating the need for a field determination circuit and its malfunction prevention circuit. Play.

According to the second aspect of the present invention, the order of the counted number of scanning lines in one frame is 3n, 6n + 1, 6n + 3, or 6n + 5 according to the counted number of scanning lines in one frame. Can easily determine whether to select the outputs of a plurality of weighted averaging means, and thereby output a non-interlaced signal. In other words, a non-interlaced signal is generated while thinning out the video signal without performing field determination on the input interlaced video signal. Therefore, erroneous field determination is performed for input video signals of any number of scanning lines. There is no risk of determination, and the number of scanning lines can be reduced. Further, there is an effect that the circuit configuration is further simplified.

According to the third aspect of the present invention, what kind of processing is performed on a frame in accordance with whether the counted number of scanning lines in one frame is an even number or an odd number to form a non-interlace signal Can be easily determined. That is, a non-interlaced signal is generated while thinning out the video signal without performing field determination on the input interlaced video signal. Therefore, the field determination is incorrect for input video signals of any number of scanning lines. The number of scanning lines can be reduced without fear. Further, the circuit configuration for that purpose can be simplified.

According to the fourth aspect of the present invention, what kind of processing is performed on a frame in accordance with whether the counted number of scanning lines in one frame is an even number or an odd number to form a non-interlace signal Can be easily determined. In other words, a non-interlaced signal is generated while thinning out the video signal without performing field determination on the input interlaced video signal. Therefore, erroneous field determination is performed for input video signals of any number of scanning lines. There is no determination, and the number of scanning lines can be reduced. Also, there is an effect that the circuit configuration is simplified. Furthermore, no matter what the video signal is, if the required number of scanning lines is 1/2, 1/3, 1/4, it is possible to reduce the number of scanning lines by forming a non-interlaced signal with a thinning circuit. it can. In addition, with the same configuration as this configuration, the number of scanning lines is reduced.
In other cases that satisfy the relationship of 1 / 2n, 1 / 3n (n is a natural number), a complete non-interlace signal can be formed.
There is an effect that the number of scanning lines can be reduced.

According to the fifth aspect of the present invention, the writing to the field portion is started after the reading of one field is completed. Therefore, the problem caused by the unstable operation of the field determination circuit and its malfunction prevention circuit. , The latest non-interlaced signal can be stably written on the memory at all times without overtaking. In addition, a non-interlaced signal can be favorably formed regardless of the phase of the frame pulse. As a result, there is an effect that the control may start from any of the odd and even fields. As a result, it is possible to convert an interlaced signal into an interlaced signal without performing the field determination of the video signal on the writing side.

According to the invention of claim 6, the signal is read from the frame memory in synchronization with the second video signal.
In addition to the effect of the invention described in claim 5, there is an effect that stable two-screen processing can be realized.

According to the seventh aspect of the present invention, since the function switching means is provided, one circuit can be switched and used for a plurality of purposes. In particular, one memory can be shared for many functions. Therefore, in addition to the effect of the invention described in claim 6, there is an effect that the cost of the apparatus can be further reduced.

[Embodiment] Hereinafter, an embodiment of a scanning line number conversion device and a down converter device will be described with reference to FIG.

A two-screen television receiver with a built-in downconverter will be described last.

In FIG. 1, an input terminal 1 has a reference video signal.
An SVm, for example, an NTSC signal is supplied. This video signal SVm is connected to the fixed terminal m of the changeover switch 2.

As described later, the video signal SVm is separated from synchronization and used as a timing reference for output of a signal from the down-converter device, so that it may be a signal representing any video.

The input terminal 3 is supplied with a video signal SVs, for example, a high definition signal. This video signal SVs is output to the A / D converter 4
After being converted into a digital signal, the signal is supplied to the thinning circuit 5. The operation of the thinning circuit 5 is controlled by a thinning control circuit 6.

The output signal of the thinning circuit 5 is supplied as a write signal to a frame memory 7 composed of, for example, a RAM. The write operation in the frame memory 7 is as follows.
It is controlled by the write control circuit 8.

The video signal SVs supplied to the input terminal 3 is supplied to a synchronization separation circuit 9, and the vertical synchronization signal WVD and the horizontal synchronization signal WHD separated by the separation circuit 9 are supplied to a thinning control circuit 6 and a write control circuit 8. Is done.

Reference numeral 10 denotes a write clock generation circuit including, for example, a PLL circuit. The clock WCK output from the generation circuit 10 is supplied to the A / D converter 4, the thinning circuit 5, and the thinning control circuit 6.

In the thinning circuit 5 described above, the sampling frequency in the vertical direction is reduced. In this case, the scanning lines are thinned in the vertical direction. When the sampling frequency is reduced, a low-pass filter corresponding to the reduced frequency is inserted in advance so that no signal component having a frequency higher than the Nyquist frequency is present.

The thinning circuit 5 performs a process of forming a non-interlace signal by interpolating a scanning line signal, in addition to the above-described process of reducing the sampling frequency.

Here, the sampling frequency reduction process and the non-interlace signal forming process will be described in detail.

Here, an example will be described in which the number of scanning lines in one field of the output signal is set to 、, 3, and 1 of the number of scanning lines in one frame of the input signal. If these are used in combination, almost any number of scanning lines can be realized.

Here, the point lies in the process of reducing the sampling frequency in the vertical direction and the process of forming a non-interlaced signal without using the field determination means. Therefore,
The description will focus on these two points.

First, a case where the number of scanning lines in one field of the output signal is reduced to half the number of scanning lines in one frame of the input video signal will be described.

The number of lines in one field of the video signal SVs is represented by ln for convenience.
If the number of lines is one, the number of lines of one field of the non-interlace signal to be output is ln ÷ 2 × 2 = ln [lines]. Here, "$ 2" indicates that the number of scanning lines is halved, and "x2" indicates that the number of lines is doubled due to non-interlacing.

As described above, the number of lines in one field to be output is equal to the number of lines in one field of the video signal SVs, so that non-interlacing is performed as follows.

When the number of lines in one frame of the video signal SVs is an even number, the video signal SVs itself is considered to be a non-interlaced signal. Therefore, the scanning line signal of any field of the video signal SVs is directly used for each of the non-interlaced signals. Assigned to field scan line signals.

When the number of one frame line of the video signal SVs is 2n + 1 (n is a positive integer) and an odd number, a frame pulse obtained by dividing the vertical synchronizing signal WVD by 1/2 is used as a reference.
The following processing is performed in each frame period.

That is, the first n scanning line signals of the video signal SVs are directly assigned to the scanning line signals of one field of the non-interlace signal. Subsequently, by using the remaining (n + 1) scanning line signals of the video signal SVs, an interpolation scanning line signal is formed such that the scanning lines exist at the same positions as the above-mentioned n scanning lines. Is assigned to the scanning line signal of the other field of the non-interlace signal.

FIG. 4A shows the video signal SVs, and “○” indicates a scanning line. FIG. 6B shows a non-interlace signal written in the frame memory 7, and the “x” mark indicates a scanning line based on an interpolation scanning line signal.

The interpolation scanning line signal is formed by, for example, arithmetic averaging of the upper and lower lines. In other words, as for the remaining n + 1 lines based on the frame pulse, two scanning lines are combined as shown by the solid line in FIG.
They are added at a rate of two, thereby forming an interpolated scan line signal.

FIG. 5B shows a non-interlaced signal formed as described above. In this case, by writing the vertical position of each scanning line in the same manner as in FIG. 7A, it is easy to understand which position of each scanning line corresponds to the video signal SVs.

That is, one scanning line of the non-interlace signal is placed at the position of one of the video signals SVs,
The scanning line 2 is subjected to arithmetic processing at the position 13 of the video signal SVs so as to correspond to the same position, and a non-interlace signal is formed.

By the way, although the frame pulse is referred to as described above, when the phase of the frame pulse is inverted,
As shown in FIG. 6A, a process of forming an interpolation scanning line signal is performed, and as shown in FIG. 6B, a non-interlace signal is formed. In this case, one scan line of the non-interlace signal is located at the position of l2 of the video signal SVs, the scan line of l2 of the non-interlace signal is located at the position of l4 of the video signal SVs,
Hereinafter, the positions correspond to the same positions, and are shifted by one line as compared with the case of the example in FIG. 5, but the scanning line position for each field is constant, and a non-interlace signal is formed similarly.

4 to 6, the description has been made assuming that the number of lines in one frame of the video signal SVs is eleven. However, in the case of an odd number, non-interlaced signals are generally formed in the same manner.

FIG. 7 shows a specific configuration example of the thinning circuit 5 and the thinning control circuit 6 for performing the above-described processing.

In the figure, the video signal SVs from the A / D converter 4 is supplied to the fixed terminal on the a side of the changeover switch 51v. The video signal SVs is directly supplied to the adder 52v and
The signal is supplied to an adder 52v via a line memory 53v constituting a delay element having a delay time of a horizontal period. Adder 52v
In this example, the two signals are added at a ratio of 1/2, and the output signal is used as an interpolated scanning line signal.
Supplied to the fixed terminal on the side.

The vertical synchronizing signal WVD from the synchronizing separation circuit 9 is supplied to a frame order circuit 61 composed of, for example, a T flip-flop, a gate circuit, and the like. This frame order circuit
At 61, the vertical synchronizing signal WVD is frequency-divided by 1/2 to form a frame pulse WFP, and a signal SFP indicating whether or not the field is where the frame pulse WFP exists is formed.

The frame pulse WFP from the frame order circuit 61 is supplied to a line number counting circuit 62 constituted by using, for example, a counter.
Is supplied, and the number of lines in one frame is counted. The 1 from the counting circuit 62
The line number data of the frame is supplied to the status determination circuit 63, and it is determined whether the number of lines in one frame is even or odd.

Also, the frame pulse WFP from the frame order circuit 61
Is supplied to a line timing display circuit 64 composed of, for example, a counter, and the timing display circuit 64
Is supplied with a horizontal synchronization signal WHD from the synchronization separation circuit 9. The timing display circuit 64 counts the number of the current line from the frame pulse WFP.

The signal SFP from the frame order circuit 61, the determination signal from the status determination circuit 63, and the count data from the timing display circuit 64 are provided by the changeover switch of the thinning circuit 5.
It is supplied as a switching control signal to 51v.

That is, when the number of lines in one frame is an even number, the changeover switch 51v remains connected to the a side. On the other hand, when the number of lines in one frame is an odd number, the period from the frame pulse to the n-th line is connected to the a-side, and the remaining n + 1-line period is connected to the b-side.

As a result, the number of scanning lines is reduced by half from the changeover switch 51v.
The non-interlaced signal is output.

In the thinning control circuit 6, a frame order circuit
The signal SFP from 61, the determination signal from the status determination circuit 63, and the count data from the timing display circuit 64 are supplied to the line address control circuit 65. The line address control circuit 65 supplies the write control circuit 8 with:
A line address increment signal INC is supplied. The increment signal INC is also supplied as an output enable signal WE as described later.

 Next, a case where the number of scanning lines is 1/3 will be described.

The number of lines in one field of the video signal SVs is represented by ln for convenience.
If the number of lines is one, the number of lines of one field of the non-interlace signal to be output is ln 3 × 2 = 2ln / 3 [lines]. Here, “$ 3” indicates that the number of scanning lines is 3, and “× 2” indicates that the number of scanning lines is doubled due to non-interlacing.

As described above, the number of lines of one field to be output is 2/3 of the number of lines of one field of the video signal SVs. Therefore, according to the number of lines of one frame of the video signal SVs,
Non-interlaced as follows.

When the number of lines in one frame of the video signal SVs is an even number (for example, 526, 626, 1050, 1250, etc.), the video signal SVs itself is considered to be a non-interlace signal. In this case, for each field of the video signal SVs, two scanning line signals are formed from the 3n + 0, 3n + 1, and 3n + 2nd scanning line signals, and are assigned to the scanning line signals of each field of the non-interlace signal. For example, the following control is repeated every three lines.

In the 3n + 0th line, the current scanning line signal and the previous scanning line signal are added at a ratio of 1/2, respectively, to form a non-interlaced scanning line signal.

On the (3n + 1) th line, a scanning line signal of a non-interlace signal is not formed.

In the (3n + 2) th line, the current scanning line signal, the scanning line signal one line before and the scanning line signal two lines before are
A scanning line signal of a non-interlace signal is formed by adding at a ratio of 1/4, 1/2, and 1/4, respectively.

Also, the number of lines in one frame of the video signal SVs is 6k + 3.
In the case where k is a positive integer (for example, 525 lines, 627 lines, 1125 lines, etc.), each frame is determined based on a frame pulse obtained by dividing the vertical synchronization signal WVD by 1/2. The control is repeated every three lines during the period to form a scanning line signal of a non-interlace signal.

FIG. 8A shows the video signal SVs, and the “○” marks are scanning lines. FIG. 6B shows a non-interlaced signal to be output, and “x” indicates a scanning line. In this case, each scanning line signal of the non-interlaced signal is formed by calculating from a plurality of scanning line signals of the video signal SVs.

For example, the following control is repeated every three lines in each frame period.

That is, 3n + 0 (0, 3, 6, ...) from the frame pulse
In the third line, the current scanning line signal and the previous scanning line signal surrounded by a broken line in FIG. 9A are added at a rate of 1/2 each to form a scanning line signal of a non-interlace signal. Is done.

Further, in the 3n + 1 (1, 4, 7,...) -Th line, a scanning line signal of a non-interlace signal is not formed.

In the 3n + 2 (2,5,8, ...) line, the ninth line
The current scanning line signal surrounded by a solid line in FIG. A, the scanning line signal one line before and the scanning line signal two lines before are added at a ratio of 1/4, 1/2 and 1/4, respectively. A scanning line signal of a non-interlace signal is formed.

In FIG. 9A, “(x = 0 to 14)” is a scanning line.

FIG. 9B shows a non-interlaced signal formed by repeating the above control, and “x” indicates a scanning line. In this case, the vertical position of each scanning line is written in the same manner as in FIG.
In s, it is easy to understand which position corresponds.

That is, one scanning line of the non-interlace signal is placed at the position of l2 of the video signal SVs,
Are processed at the position of l3 'of the video signal SVs so as to correspond to the following similar positions to form a non-interlaced signal.

By the way, although the frame pulse is referred to as described above, when the phase of the frame pulse is inverted,
The processing is performed as shown in FIG. 10A, and a non-interlace signal is formed as shown in FIG. 10B. In this case, one scan line of the non-interlace signal corresponds to the position of 1 of the video signal SVs, the scan line of l2 of the non-interlace signal corresponds to the position of l2 'of the video signal SV, and so on. The scanning line position for each field is constant, but a non-interlaced signal is formed in the same manner.

8 to 10, the number of scanning lines of the video signal SVs is one.
Although the description has been made with reference to five lines, for example, when the number of scanning lines is 6k + 3, such as 525 lines, 627 lines, and 1125 lines, a non-interlace signal is formed in the same manner.

Also, the number of lines in one frame of the video signal SVs is 6k + 1.
When the number is k (k is a positive integer, for example, 523 lines, 625 lines, etc.), the control is repeated every three lines to form a scanning line signal of a non-interlace signal. In this case, the control is different between a field where a frame pulse obtained by dividing the vertical synchronization signal WVD by 1/2 and a field where the frame pulse does not exist.

FIG. 11A shows a video signal SVs, and “○” indicates a scanning line. FIG. 6B shows a non-interlaced signal to be output, and “x” indicates a scanning line. In this case, each scanning line signal of the non-interlaced signal is formed by calculating from a plurality of scanning line signals of the video signal SVs.

For example, in a field where a frame pulse exists and a field where no frame pulse exists, the following control is repeated for every three lines.

That is, in FIG. 12A, assuming that a frame pulse exists in the field f1, in this field f1,
In the 3n + 0 (0, 3, 6,...) Line from the frame pulse, the current scanning line signal surrounded by a solid line in FIG. 12A, the scanning line signal one line before, and the scanning line two lines before The signals are added at a rate of 1/4, 1/2 and 1/4, respectively, to form a scanning line signal of a non-interlaced signal.

Further, in the 3n + 1 (1, 4, 7,...) -Th line, a scanning line signal of a non-interlace signal is not formed.

In the 3n + 2 (2,5,8, ...) line, the twelfth
The one-line preceding scanning line signal and the two-line preceding scanning line signal surrounded by a broken line in FIG. A are added at a rate of 1/2, respectively, to form a non-interlaced scanning line signal.

In the field f2 where no frame pulse is present, the current scanning line signal enclosed by a broken line in FIG. 12A and one line before the 3n + 0 (12, 15, 18,...) Line from the frame pulse Scan line signals are 1 /
The scanning line signal of the non-interlace signal is formed by adding at the ratio of 2.

In the 3n + 1 (13,16,19, ...) line,
No scanning line signal of the non-interlace signal is formed.

In the 3n + 2 (11,14,17, ...) line,
The current scanning line signal surrounded by a solid line in FIG. 12A, the scanning line signal one line before and the scanning line signal two lines before are
A scanning line signal of a non-interlace signal is formed by adding at a ratio of 1/4, 1/2, and 1/4, respectively.

In FIG. 12A, “(x = 0 to 18)” is a scanning line.

FIG. 12B shows a non-interlaced signal formed by repeating the above control, and “x” indicates a scanning line. In this case, the vertical position of each scanning line is written in the same manner as in FIG.
In s, it is easy to understand which position corresponds.

That is, one scan line of the non-interlace signal is calculated at the position 1 'of the SVs of the video signal, the scan line 12 of the non-interlace signal is calculated at the position 13 of the video signal SVs, and so on. The processing is performed to form a non-interlaced signal.

In the above description, the scanning line signal of the non-interlace signal is not formed in the 3n + 1th line of the field where the frame pulse exists, and the scanning line signal of the previous line and the scanning line signal of the previous line are not formed in the 3n + 2nd line. Although the scanning line signal of the non-interlace signal is formed from the scanning line signal, this may be performed as follows. That is, in the (3n + 1) th line, a scanning line signal of a non-interlace signal is formed from the current scanning line signal and the scanning line signal one line before, and in the (3n + 2) th line, a scanning line signal of a non-interlace signal is not formed. It may be.

By the way, when the phase of the frame pulse is inverted, the processing shown in FIG. 13A is performed, and a non-interlaced signal is formed as shown in FIG. 13B. in this case,
One scanning line of the non-interlace signal is a video signal SV
The scanning line of l2 of the non-interlace signal at the position of l2 of the s corresponds to the position of the l3 'of the video signal SVs, and the same as the following position. However, the scanning line position for each field is constant, and a non-interlace signal is similarly formed.

Note that in FIGS. 11 to 13, the number of scanning lines of the video signal SVs is one.
Although the description has been made on the assumption that the number of scanning lines is nine, for example, when the number of scanning lines is 6k + 1, such as 523 lines or 625 lines, a non-interlace signal is formed in the same manner.

Also, the number of lines in one frame of the video signal SVS is 6k + 5
When the number is k (k is a positive integer, for example, 527 or 623), the control is repeated every three lines to form a scanning line signal of a non-interlace signal. As in the case where the number of lines in one frame is 6k + 1, the control is different between a field in which a frame pulse obtained by dividing the vertical synchronizing signal WVD by 1/2 and a field in which a frame pulse does not exist.

FIG. 14A shows a video signal SVS, and “○” indicates a scanning line. FIG. 6B shows a non-interlaced signal to be output, and “x” indicates a scanning line. In this case, each scanning line signal of the non-interlace signal is formed by calculating from a plurality of scanning line signals of the video signal SVS.

For example, in a field where a frame pulse exists and a field where no frame pulse exists, the following control is repeated for every three lines.

That is, assuming that a frame pulse exists in the field f1 in FIG. 15A,
In the 3n + 0 (0, 3, 6,...) -Th line from the frame pulse, the current scanning line signal and the previous scanning line signal enclosed by a solid line in FIG. The non-interlaced scanning line signals are formed by adding at the ratio.

Further, in the 3n + 1 (1, 4, 7,...) -Th line, a scanning line signal of a non-interlace signal is not formed.

In the 3n + 2 (2,5,8, ...) line, the 15th line
The current scanning line signal surrounded by a broken line in FIG. A, the scanning line signal one line before and the scanning line signal two lines before are added at the ratios of 1/4, 1/2 and 1/4, respectively. A scanning line signal of a non-interlace signal is formed.

In the field f2 in which no frame pulse exists, the current scanning line signal surrounded by a broken line in FIG. 15A and the line before the 3n + 0 (9, 12, 15,...) Line from the frame pulse And the scanning line signal two lines before are added at a rate of 1/4, 1/2 and 1/4, respectively, to form a scanning line signal of a non-interlace signal.

In the 3n + 1 (10,13,16, ...) line,
No scanning line signal of the non-interlace signal is formed.

In the 3n + 2 (11, 14, ...) line, the 15th line
The one-line preceding scanning line signal and the two-line preceding scanning line signal surrounded by a solid line in FIG. A are added at a rate of 1/2, respectively, to form a non-interlaced scanning line signal.

In FIG. 15A, “(x = 0 to 16)” is a scanning line.

FIG. 15B shows a non-interlaced signal formed by repeating the above control, and “x” indicates a scanning line. In this case, the vertical position of each scanning line is written in the same manner as in FIG.
In S, it is easy to understand which position corresponds.

That is, one scanning line of the non-interlace signal is located at the position of l2 of the SVS of the video signal,
The scanning line 2 is subjected to arithmetic processing at the position of l3 'of the video signal SVS so as to correspond to the same position, and a non-interlace signal is formed.

In the above description, the scanning line signal of the non-interlaced signal is not formed in the 3n + 1-th line of the field where no frame pulse exists, and the scanning line signal of the previous line and the scanning line signal of the previous line are not formed in the 3n + 2nd line. Although the scanning line signal of the non-interlace signal is formed from the scanning line signal, this may be performed as follows.
That is, in the (3n + 1) th line, a scanning line signal of a non-interlace signal is formed from the current scanning line signal and the scanning line signal of the previous line, and in the (3n + 2) th line,
The scanning line signal of the non-interlace signal may not be formed.

By the way, when the phase of the frame pulse is inverted, the processing shown in FIG. 16A is performed, and a non-interlaced signal is formed as shown in FIG. 16B. in this case,
One scanning line of the non-interlace signal is a video signal SVS
The scan line of l2 of the non-interlace signal corresponds to the position of l4 of the video signal SVS, and thereafter, the position of l2 'of the non-interlace signal is shifted by one line compared to the case of FIG. However, the scanning line position for each field is constant, and a non-interlaced signal is similarly formed.

14 to 16, the number of scanning lines of the video signal SVS is 1
Although the number of scanning lines has been described as seven, for example, when the number of scanning lines is 6k + 5, such as 527 lines or 623 lines, a non-interlace signal is formed in the same manner.

FIG. 17 shows a specific configuration example of the thinning circuit 5 and the thinning control circuit 6 for performing the processing when the number of scanning lines is reduced to 1/3 as described above.

In the figure, a video signal SVs from an A / D converter 4 is supplied to a series circuit of line memories 54v and 55v which constitute a delay element having a delay time of one horizontal period. Then, the output signals of the line memories 54v and 55v are supplied to an adder 56v and added at a ratio of 1/2, respectively, and then supplied to a fixed terminal on the c side of a changeover switch 57v. The video signal SVs from the A / D converter 4, the output signal of the line memory 54v, and the output signal of the line memory 55v are supplied to the adder 58v, and the ratio is 1/4, 1/2, and 1/4, respectively. Is supplied to the fixed terminal on the b side of the changeover switch 57v. Further, the video SVs from the A / D converter 4 and the line memory 54
The output signal of v is supplied to the adder 59v, added at a ratio of 1/2, and then supplied to the fixed terminal on the a side of the changeover switch 57v.

In the status determination circuit 63 of the thinning control circuit 6, the number of scanning lines is even, 6k + 1, 6k + 3, and 6k +
It is determined which of the five lines corresponds. That is, it is determined from the line number data of one frame from the line number counting circuit 62 whether the number of lines is an even number, and in the case of an odd number, the remainder divided by 6 is obtained. The status determination circuit 63 can be configured by hardware, but can be easily configured by using a ROM.

The capacity of the ROM used here is 2K bits as follows when the normal number of scanning lines is about 525. That is,
Supplying the line number data to the ROM address requires 10 bits. Also, since there are four types of status in total, it can be represented by two bits. Therefore, 2 ¹⁰ × 2 = 2K bits.

A line timing display circuit of the thinning control circuit 6
At 64, the number of the current line from the frame pulse WFP or the vertical synchronization signal WVD is counted, and the remainder obtained by dividing the value by 3 is output. Other configurations are the same as in the example of FIG.

The signal SFP from the frame ordering circuit 61, the determination signal from the status determination circuit 63, and the output signal from the timing display circuit 64 are supplied to the changeover switch 57 of the thinning circuit 5.
The signal is also supplied to the line address control circuit 65, and the switching control of the changeover switch 57v and the availability of signal output are controlled.

That is, when the number of scanning lines in one frame is an even number, control is performed as follows. In the 3n + 0th line of each field, the changeover switch 57v is connected to the a side, the increment signal INC is output from the line address control circuit 65 and the signal from the changeover switch 57v is output, and in the 3n + 1th line, the changeover switch 57v is changed. 57v is undefined, the increment signal INC is not output from the line address control circuit 65, and the output of the signal is also prohibited.
In the + 2nd line, the changeover switch 57v is connected to the b side, and the line address control circuit 65 outputs the increment signal INC and outputs the signal from the changeover switch 57v.

When the number of scanning lines in one frame is 6k + 1, control is performed as follows. In the field where the frame pulse exists, in the 3n + 0th line from the frame pulse, the switch 57v is connected to the b side, and the line address control circuit 65 outputs an increment signal to output the signal from the switch 57v. And
In the (3n + 1) th line from the frame pulse, the changeover switch 57v is undefined and the line address control circuit 6
The increment signal INC is not output from 5 and the output of the signal is also prohibited. In the 3n + 2nd line, the changeover switch 57v
Is connected to the c side, and the line address control circuit 65
The increment signal INC is output from the switch 5
The signal from 7v is output. On the other hand, in a field where no frame pulse exists, 3n +
In the 0th line, the changeover switch 57v is connected to the a side, the increment signal INC is output from the line address control circuit 65, the signal from the changeover switch 57v is output, and in the 3n + 1th line from the frame pulse, the changeover switch 57v is changed. 57v is undefined, the increment signal INC is not output from the line address control circuit 65, and the output of the signal is also inhibited. In the 3n + 2nd line, the changeover switch 57v is connected to the b side and the line address control circuit 65 The increment signal INC is output, and the signal from the changeover switch 57v is output.

In a field where a frame pulse exists, the following control may be performed. That is, in the 3n + 0th line from the frame pulse, the changeover switch
57v is connected to the b side, and an increment signal is output from the line address control circuit 65 to switch
The signal from 57v is output and 3n + 1 from the frame pulse
In the second line, the changeover switch 57v is connected to the a side, the increment signal INC is output from the line address control circuit 65, the signal from the changeover switch 57v is output, and in the 3n + 2nd line from the frame pulse, the changeover switch 57v is Is undefined, and the increment signal INC is not output from the line address control circuit 65, and the output of the signal is also inhibited.

When the number of scanning lines in one frame is 6k + 3, control is performed as follows. 3n + from frame pulse
In the 0th line, the changeover switch 57v is connected to the a side, the increment signal INC is output from the line address control circuit 65, the signal from the changeover switch 57v is output, and in the 3n + 1th line from the frame pulse, the changeover switch 57v is changed. 57v is undefined, the increment signal INC is not output from the line address control circuit 65, and the output of the signal is also inhibited. In the 3n + 2nd line, the changeover switch 57v is connected to the b side and the line address control circuit 65 The increment signal INC is output, and the signal from the changeover switch 57v is output.

When the number of scanning lines in one frame is 6k + 5, the control is performed as follows. In the field in which the frame pulse exists, in the 3n + 0th line from the frame pulse, the changeover switch 57v is connected to the a side, and the line address control circuit 65 outputs an increment signal to output the signal from the changeover switch 57v. And
In the (3n + 1) th line from the frame pulse, the changeover switch 57v is undefined and the line address control circuit 6
5, the increment signal INC is not output and the output of the signal is also inhibited. In the 3n + 2nd line, the changeover switch 57v is connected to the b side, and the line address control circuit 65 outputs the increment signal INC to change the changeover switch 57v.
Is output. On the other hand, in a field where no frame pulse exists, 3n + 0
In the second line, the changeover switch 57v is connected to the b side, the increment signal INC is output from the line address control circuit 65, the signal from the changeover switch 57v is output, and in the 3n + 1th line from the frame pulse, the changeover switch 57v is Is undefined, the increment signal INC is not output from the line address control circuit 65, and the output of the signal is also inhibited. In the 3n + 2nd line, the changeover switch 57v is connected to the c side, and the line address control circuit 65 The increment signal INC is output, and the signal from the changeover switch 57v is output.

In the field where no frame pulse exists,
The control may be performed as follows. That is, in the 3n + 0th line from the frame pulse, the changeover switch
57v is connected to the b side, an increment signal INC is output from the line address control circuit 65, a signal from the changeover switch 57v is output, and 3n is output from the frame pulse.
In the + 1st line, the changeover switch 57v is connected to the a side, the increment signal INC is output from the line address control circuit 65, the signal from the changeover switch 57v is output, and in the 3n + 2nd line from the frame pulse, the changeover switch 57v is changed. 57v is undefined, and the line address control circuit 65 does not output the increment signal INC and prohibits the output of the signal.

 Next, a case where the number of scanning lines is 1/4 will be described.

In this case, the concept of the case where the number of scanning lines is 1/2 can be applied. In other words, since the number of scanning lines may be further reduced to 1/2 of that in the case of に よ っ て, a non-interlaced signal is formed once by the same control as in the case of ち, and then the arithmetic average is calculated every two lines. This is processed to reduce the number of scanning lines to half.

As described above, the thinning circuit 5 and the thinning control circuit 6 for performing the processing when the number of scanning lines is 1/2 perform, for example, the arithmetic averaging processing for every two lines after the changeover switch 51v in the example of FIG. And a circuit for performing the operation. Thus, a good non-interlace signal is formed even when the number of scanning lines is 1/4.

As described above, the circuit shown in FIG. 7 can be commonly used when the number of scanning lines is 1/2 and 1.

When the number of scanning lines is 1/4, as in the case of 1/2, the number of lines may be directly reduced to 1/2 to obtain a non-interlace signal.

As described above, no matter what the video signal SVs is, if the number of scanning lines is 1/2, 1/3, and 1/4, the thinning circuit 5 forms a non-interlace signal.

With the same configuration as described above, a complete non-interlaced signal can be formed in other cases where the number of scanning lines satisfies the relationship of 1 / 2n and 1 / 3n (n is a natural number).

By the way, in the above control, a non-interlaced signal is favorably formed regardless of the phase of the frame pulse.
This means that control may start from any field, even or odd. As a result, it is possible to convert an interlaced signal into a non-interlaced signal without performing the field determination of the video signal SVs on the writing side.

When the reference video signal SVm is an NTSC signal and the video signal SVs is a Hi-Vision signal as in this example, it is desirable to reduce the number of scanning lines to 1/3. It is NTS
It depends on the aspect ratio of C and HD.

When a high-definition image with an aspect ratio of about 5: 3 is projected on an NTSC monik with an aspect ratio of 4: 3 with the same width, the number of effective scanning lines on the screen is about 380. On the other hand, if the number of scanning lines is 1
With the function of the scanning line number conversion device of / 3, the number of scanning lines per field, 375 non-interlaced, high definition signals can be generated.

 Therefore, it is desirable to reduce the number of scanning lines to 1/3.

Returning to FIG. 1, each scanning line signal of the non-interlace signal output from the thinning circuit 5 is written to the frame memory 7.

As described above, on the writing side, the field determination of the video signal SVs is not performed, and when the video signal SVs is an interlace signal, which field is written to which field portion of the frame memory 7 is determined. Cannot be defined. However, since the output signal itself of the thinning circuit 5 is non-interlaced, it is not necessary to bring another concept of an even / odd field into the frame memory 7 and there is no problem.

Reference numeral 11 denotes an overtaking judgment circuit. In this overtaking determination circuit 11, writing and reading of the frame memory 7 are performed for either field portion based on the MSB data of the line address from the writing control circuit 8 and the reading control circuit 12 as described later. Signal IN for inverting the write field
V is output. Then, the inverted signal INV is supplied to the write control circuit 8, and the write field is inverted in the same field portion of the frame memory 7 so that writing and reading do not occur simultaneously.

The write control circuit 8 has the synchronization signal WH as described above.
In addition to D and WVD, the write clock WC from the thinning circuit 5
K ', an increment signal INC of the line address from the thinning control circuit 6, and an inverted signal I from the overtaking judgment circuit 11.
The NV is supplied, and a write address of the frame memory 7 is formed based on the NV.

FIG. 18 is a diagram showing a specific configuration example of the write control circuit 8.

In the figure, a write clock WCK from a write clock generating circuit 10 is supplied to a counter 81, to which a horizontal synchronizing signal WHD from a synchronizing separation circuit 9 is supplied as a reset signal. And this counter 81
Is supplied to the frame memory 7 as a horizontal address.

The horizontal synchronizing signal WHD from the synchronization separating circuit 9 is supplied to the counter 82 as a clock, and the vertical synchronizing signal WVD from the synchronization separating circuit 9 is supplied to the counter 82 as a reset signal. The counter 82 is supplied with an increment signal INC from the thinning control circuit 6 as a counter enable signal. The MSB-1 to LSB of the count output of the counter 82 are supplied to the frame memory 7 as the MSB-1 to LSB of the line address (vertical address).

The MSB of the count output of the counter 82 is supplied to one input terminal of the exclusive OR circuit 83, and the other input terminal of the exclusive OR circuit 83 is supplied with the inverted signal INV from the overtaking determination circuit 11. The output signal of the exclusive OR circuit 83 is supplied to the frame memory 7 as the MSB of the line address.

In this case, when the inversion signal INV is supplied from the overtaking control circuit 11, the output signal of the exclusive OR circuit 83,
Therefore, the state of the MSB of the line address is inverted, whereby the field on the writing side is inverted. Further, when the increment signal INC is supplied from the thinning control circuit 6, the counter 82 becomes a countable state, and the line address is incremented. At this time, since the write enable signal WE is supplied to the frame memory 7, the frame memory 7 is in a writable state.

The MSB of the count output of the counter 82 is supplied to the overtaking determination circuit 11, which generates an inverted signal INV based on a comparison with the MSB of the read line address, as described later.

Note that the write control circuit 8 in FIG. 18 is an example in which the frame memory 7 is configured using a normal RAM, but the frame memory 7 may be configured using an IC dedicated to a field memory or the like. In that case, the configuration can be simplified.

As shown in FIG. 19, a non-interlace signal is written in each field portion of the frame memory 7 by the write address formed by the write control circuit 8 in this manner. FIG. 19 shows a case where the number of lines in one field is nine for simplicity.

Next, how to read the non-interlace signal written in the frame memory 7 in this manner will be described.

In FIG. 1, reference numeral 13 denotes a read clock generation circuit configured using a PLL circuit or the like. The frequency of the read clock RCK generated by the clock generation circuit 13 affects the horizontal length of the screen to be displayed.

This frequency is determined in consideration of the aspect ratio of the high-definition image and the NTSC television monitor, and the like. For example, the frequency may be the same as the write clock WCK of the frame memory 7, or may be an appropriate constant multiple. Here, the frame memory 7 operates as a time axis changing unit, and the writing and the reading operate asynchronously.

For reading from the frame memory 7, the reference video signal SVm is used. SVm is input terminal 1
Is supplied to the synchronization separation circuit 14 to separate the vertical synchronization signal RVD and the horizontal synchronization signal RHD.

The video signal SVm is supplied to the monitor receiver 18 during a period in which the down-converted Hi-Vision signal is not applied to the monitor receiver 18 through the s-side fixed terminal of the changeover switch 2.
And has a function of masking the screen.

That is, as described above, since there are only about 375 scanning lines of the down-converted HDTV signal, the NTSC
There is no Hi-Vision signal during a period corresponding to a scanning line having a difference from the number of scanning lines of the monitor of 525. Therefore, only during this period, the image is displayed on the screen of the image monitor receiver 18 by the video signal SVm, and unnecessary portions on the screen are masked.

When a signal for masking is separately generated, the input terminal 1 and the synchronization separation circuit 14 shown in FIG.
VD may be generated directly.

The reading of the signal from the frame memory 7 may be performed interlaced or non-interlaced. Since signals are written in the frame memory in a non-interlaced manner, when reading out a signal in a non-interlaced manner, it is only necessary to read out the signal in order using RHD and RVD, and no complicated control is required.

Hereinafter, a configuration for reading an interlaced signal will be described.

When reading the interlaced signal, the synchronization signals RVD and RHD are supplied to the field determination circuit 15. In the field determination circuit 15, an even / odd field of the reference signal SVm is determined based on the phases of the synchronization signals RVD and RHD. For example, the horizontal synchronization signal RHD and the vertical synchronization signal RVD
Are coincident with each other as shown in FIGS. 20A and 20B, while the phases of the horizontal synchronizing signal RHD and the vertical synchronizing signal RVD are determined as odd fields.
Fields shifted by a 1/2 horizontal period (H / 2) as shown in FIGS. C and D are determined to be even fields. In this case, as shown in FIG. 21, it is assumed that the scanning line of the even field is above the same scanning line of the odd field. FIG. 21 shows a case where the number of lines in one frame is nine.

The determination signal FD from the field determination circuit 15 is supplied to the read control circuit 16. The read control circuit 16 is supplied with the synchronization signals RVD and RHD separated by the synchronization separation circuit 14, and is also supplied with a read clock RCK from the clock generation circuit 13. Based on these, a read address of the frame memory 7 is formed, and the non-interlace signal written in the frame memory 7 is converted into an interlace signal that matches the interlace order of the reference video signal SVm and read. .

Here, it should be noted that a scanning line signal corresponding to the first line of the even field is not written on the frame memory 7 as shown in FIG.

That is, in order to match the interlace order with the video signal SVm, in the odd field, 1, 3, 5,
The scanning line signals of …… in the even fields are indicated by 2, 4, and 4 in FIG.
It is necessary to read out the scanning line signals of 6, .... in this case,
Since two fields of the non-interlaced signal are written in the frame memory 7, either field part may be assigned to either field of the video signal SVm. That is, signals are read from the two field portions of the frame memory 7 alternately in accordance with the field determination result of the video signal SVm as described above.

FIG. 22 is a diagram showing a specific configuration example of the read control circuit 16.

In the figure, the read clock RCK from the read clock generation circuit 13 is supplied to a counter 161. The horizontal synchronization signal RHD from the synchronization separation circuit 14 is supplied to the counter 161 via a delay circuit 162 as a reset signal.
The count output of the counter 161 is supplied to the frame memory 7 as a horizontal address.

In this case, the horizontal synchronization signal RHD is supplied to the horizontal position adjustment circuit 163.
Is supplied to the counter 161 after being delayed by the time set in (1), and the counter 161 is reset. That is, the horizontal readout of the frame memory 7 is started from this reset timing, and the horizontal display start position is determined.

Note that the delay amount is configured to be adjusted in units of, for example, one cycle of the read clock RCK. here,
As the delay amount increases, the display position of the screen is on the right side.

The horizontal synchronization signal RHD from the synchronization separation circuit 14 is supplied to the counter 164 as a clock. This counter 164
The vertical synchronization signal RVD from the synchronization separation circuit 14 is
It is supplied via 62 as a load signal. The field determination signal FD from the field determination circuit 15 is a counter.
164 is supplied as the LSB of the load data. The other bits of the load data are set to, for example, low level “0”. Although not described above, for example, the field determination signal FD is set to a low level “0” in an odd field, and is set to a high level “1” in an even field. And
The count output of the counter 164 is supplied to the frame memory 7 as MSB-1 to LSB + 1 of the line address (vertical address).

The field determination signal FD from the field determination circuit 15 is supplied to the inverter 166, and the output signal of the inverter 166 is supplied to the frame memory 7 as the MSB and LSB of the line address.

In this case, since the state of the MSB of the line address changes according to the field determination signal FD, reading is performed alternately from the two field portions of the frame memory 7 according to the even or odd field of the video signal SVm.

In the case of an odd field, the lower two bits of the line address are initially set to "01" and the LSB is fixed to "1", so that the scanning line signals of 1, 3, 5,... On the other hand, in the case of an even field, the lower two bits of the line address are initially "10" and the LSB is fixed at "0", so that the scanning line signals of 2, 4, 6,... Is read.

In this case, the vertical synchronization signal RVD is supplied to the counter 164 after being delayed by the time set by the screen vertical position adjustment circuit 167, and the load data is loaded into the counter 164. That is, the reading of the frame memory 7 in the vertical direction is started from the load timing, and the display start position in the vertical direction of the screen is determined.

The horizontal synchronizing signal RHD delayed by the delay circuit 162 is supplied to a high-definition screen length generating circuit 168. From the generating circuit 168, for example, a high level “1” is displayed only during the period of displaying the screen from the timing of the horizontal synchronizing signal RHD. And a signal which becomes low level “0” during the other periods. Then, the output signal of the creation circuit 168 is supplied to the OR circuit 160.

The vertical synchronizing signal RVD delayed by the delay circuit 165 is supplied to the high-vision screen height creating circuit 169. From the creating circuit 169, the high level “1” is output only during the period of displaying the screen from the timing of the vertical synchronizing signal RVD. And a signal which becomes low level “0” during the other periods. Then, the output signal of the creation circuit 169 is supplied to the OR circuit 160.

Further, the MSB of the read line address output from the inverter 166 is supplied to the overtaking determination circuit 11.

Although not described above, the overtaking determination circuit 11 always monitors the MSB of the read line address and the MSB of the write line address (output of the counter 82), and when these have the same polarity, the high level "1" for inverting the write field is used. Is output.

The read control circuit 16 in the example of FIG. 22 shows an example in which a normal RAM is used as the frame memory 7, but the frame memory 7 is formed using an IC dedicated to a field memory. In that case, a simpler configuration can be achieved.

Returning to FIG. 1, the video signal for the high-definition screen read from the frame memory 7 as described above is D / A
After being converted into an analog signal by the converter 17, the analog signal is supplied to the fixed terminal on the s side of the changeover switch 2. An output signal of the OR circuit 160 of the read control circuit 16 is supplied to the changeover switch 2 as a changeover control signal. The switch 2 is connected to the s side when the output signal of the OR circuit 160 is at the high level “1”, and is connected to the m side when the output signal is at the low level “0”. As mentioned above, OR circuit
The output signal 160 becomes high level "1" during the display period of the high-definition screen, and only during this period, the changeover switch 2 is connected to the s side, and the reference video signal SVm is read from the frame memory 7 for the high-definition screen. A video signal is inserted.

The output signal of the changeover switch 2 is supplied to the monitor receiver 18. Here, the high-definition image is switched to the NTSC screen and displayed satisfactorily by the video signal inserted into the reference video signal SVm.

It should be noted that the monitor receiver 18 may be an IDTV or an EDTV (for example, a Nikkei Electronics 19) as well as a current television receiver.
(See the September 8, 1986 issue, high-definition television using digital technology, which is expected to become a pillar of the next home appliance). In this case, as described above, if a signal is read out in a non-interlace manner using RHD and RVD and supplied to the monitor receiver 18, higher image quality can be expected.

In the above embodiment, the reference video signal SVm is supplied to the input terminal 1 in the form of an analog signal.
Assuming that the video signal SVm is digitized and supplied to the input terminal 1, the D / A converter 17 shown in FIG. 1 becomes unnecessary, and the reference / high-vision signal is switched as it is and the monitor receiver is switched. You will be led to 18.
This is one application example for effectively using the present invention for digital television. Digital TV is known as ID
Since high image quality can be obtained as a TV, EDTV, or the like, the above-described application example is suitable for use in displaying a high-definition screen on an IDTV or EDTV.

Although the description is duplicated, in this case, the frame memory 7 is used.
If the signal is read out from the non-interlace, an effect of higher image quality can be expected.

Although the above description does not refer to a color signal, the color signal can be processed in exactly the same manner as described above, if demodulated to baseband. In this case, a suitable demodulator,
Modulators will be added before and after processing. Of course, a video signal may be supplied to the monitor receiver 18 as a baseband component signal. In this case, a modulator is not required.

In any case, if the two color difference signals are subjected to TCI or TDM in consideration of the color signal band or the like, the memory capacity can be effectively reduced.

As described above, in this example, regardless of whether or not the high-vision video signal SVs is interlaced, it is written into each field portion of the frame memory 7 in a non-interlaced manner. Then, based on the field determination result of the reference video signal SVm, the high-definition screen video signal is sent from the frame memory 7 so that the high-definition screen video signal has the correct interlace order with respect to the reference video signal SVm. Are read out while performing interlace conversion.

Therefore, according to this example, the interlacing relationship between the reference video signal SVm and the high-vision screen video signal always coincides, and no line flicker or double image disturbance occurs.

In this example, since the video signal for the high-definition screen is written in each field of the frame memory 7 in a non-interlaced manner, the write field of the frame memory and the field of the video signal SVs for the high-definition screen do not always match. No need. And
It is checked which field is being written or read from the frame memory 7, and the writing field is inverted so that writing and reading to the same field portion of the frame memory 7 do not occur simultaneously. Therefore, no boundary problem occurs due to erroneous field determination of the video signal SVs for a high-definition screen.

As described above, according to this example, it is unnecessary to perform the field determination of the video signal SVs for the high-definition screen on the writing side,
Even if any video signal is used as the video signal SVs for the HDTV screen, it is possible to downconvert and display a good HDTV screen without image quality degradation due to erroneous field determination.

Finally, a two-screen television receiver with a built-in downconverter device according to the third invention of the present invention will be described.

In the two-screen television receiver with a built-in down-converter device of this example, most of the signal processing circuits can be shared with the above-described down-converter device. The points to be changed when the down-converter device is commonly used as a two-screen television signal processing circuit are the frequency of the writing clock WCK, the writing range and the reading range of the frame memory, and the like.

First, the reason why the frequency of the write clock WCK needs to be changed will be described.

The reason is that the display area of the child screen is always smaller than the display area of the parent image quality. For example, if the horizontal length of the child screen is 1 / of the parent screen, the number of pixels of the child screen in the horizontal direction is also な る of the parent screen.

In response to this, the frequency of the write clock WCK is changed. For example, in the above example, the write clock WCK
Is set to be 1/3 of the frequency of the read clock RCK. Such a change is made by the write clock generation circuit.
It can be easily realized by changing 10 constants.

Next, control of the writing range and the reading range of the frame memory 7 will be described.

As described above, in the case of a two-screen television, the frequency of the write clock WCK is selected to be, for example, 1/3 of the frequency of the read clock RCK. Also, the number of scanning lines converted by the scanning line number conversion device needs to be, for example, 1/3 of the parent screen ratio according to the length of the child screen in the vertical direction. As a result, the total number of pixels of the child screen is 1/9 of the parent screen. This means that the number of pixels actually written to and read from the frame memory 7 may be 1/9 of the parent screen.

That is, control is performed such that only the actually necessary pixels are written to and read from the predetermined range of the frame memory 7.

The above control is performed by the function control unit 19 in the example of FIG.

 FIG. 23 shows a part of the function control unit 19.

FIG. 23A shows a configuration for changing the clock frequency. The clock frequency is determined by the configuration of the write clock generation circuit 10, but it is assumed here that an appropriate voltage-controlled oscillator is used. Therefore, a changeover switch that can be switched according to the purpose of the user
231 and fixed voltage sources 232 and 233 for changing the transmission frequency are required. The output signal of the changeover switch 231 is supplied as a control signal to the clock generation circuit 10 to be written.

In the case of a two-screen television, the HDTV screen length creation circuit 168, HDTV screen height creation circuit 169, HDTV screen horizontal position adjustment circuit 163 and HDTV screen vertical position adjustment circuit 167 in FIG. It is necessary to control the timing of reading from the frame memory 7 and the switching of the changeover switch 2 in accordance with the position of the screen.

FIGS. 23B and 23C show configurations for controlling the screen length creation circuit 168 and the screen height creation circuit 169, respectively.

In this case, the changeover switches 234 and 239 are used. Also, assuming that the screen length creation circuit 168 and the screen height creation circuit 169 are configured by counters, the load data 235 to 238
To be changed.

Although not shown, circuits for controlling the screen horizontal position adjustment circuit 163 and the screen vertical position adjustment circuit 167 are also configured, for example, in the same manner as in FIGS. 23B and 23C, respectively.

Note that the above-described changeover switches 231, 234, and 239 are
It is configured to switch in conjunction with the purpose of the user. The changeover switches 231, 234, and 239 are connected to the a side when a dual screen television is used, for example, and are connected to the b side when a down converter is used.

As described above, with the slight addition of the function control unit 19,
The down-converter device functions as a two-screen television receiver with a built-in down-converter device.

It should be noted that the function of the dual-screen television receiver thus configured is not limited to the conventional configuration in which the NTSC child screen is included in the NTSC main screen. For example, a configuration in which a high-definition child screen is included in the NTSC main screen can also be realized. Of course, it also functions as a Hi-Vision down converter, so that it is possible to display only the Hi-Vision image on the entire screen of the monitor receiver 18 according to the user's preference.

Further, the configuration of the monitor receiver 18 is as described above, and a configuration such as an IDTV or an EDTV can be adopted. In this case, it can be expected that both the down-converted high-definition image and the small screen have very high image quality.

[Effect of the Invention] As described above, according to the first aspect of the present invention,
By generating a non-interlaced signal while thinning out the video signal without performing field determination on the input interlaced video signal, the field determination circuit and its malfunction prevention circuit can be eliminated.

According to the second aspect of the present invention, a non-interlaced signal is generated while decimating a video signal without performing field determination on an input interlaced video signal. Thus, there is no possibility of erroneous field determination, and the number of scanning lines can be reduced. Further, there is an effect that the circuit configuration is further simplified.

According to the third aspect of the present invention, a non-interlaced signal is generated while decimating a video signal without performing field determination on an input interlaced video signal, so that an input video signal having any number of scanning lines can be obtained. Thus, the number of scanning lines can be reduced without a risk of erroneous field determination. Further, the circuit configuration for that purpose can be simplified.

According to the fourth aspect of the present invention, a non-interlaced signal is generated while decimating a video signal without performing field determination on an input interlaced video signal, so that an input video signal having any number of scanning lines can be obtained. In addition, the number of scanning lines can be reduced without erroneous field determination, and even if the video signal is any signal, the required number of scanning lines is 1 / 2n or 1 / 3n (n is a natural number). If the relationship is satisfied, a complete non-interlaced signal can be formed by the thinning circuit, and the number of scanning lines can be reduced. Also, there is an effect that the circuit configuration is simplified.

According to the fifth aspect of the present invention, the latest non-interlaced signal is always stably written in the memory without overtaking without causing a problem due to the unstable operation of the field determination circuit and its malfunction prevention circuit. be able to. Further, the control may start from any of the odd and even fields. As a result, it is possible to convert an interlaced signal into an interlaced signal without performing the field determination of the video signal on the writing side.

According to the invention of claim 6, in addition to the effect of the invention of claim 5, there is an effect that a stable two-screen processing can be realized.

According to the invention described in claim 7, one memory can be shared for many functions, and in addition to the effect of the invention described in claim 6, there is an effect that the cost of the device can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a scanning line structure of an interlaced signal and a non-interlaced signal, and FIG. 4 and 6 are diagrams for explaining interlacing when the number of scanning lines is halved, and FIG. 7 is a thinning circuit and a thinning control when the number of scanning lines is halved. 8 to 16 are explanatory diagrams of interlacing when the number of scanning lines is reduced to 1/3, and FIG. 17 is a diagram illustrating the number of scanning lines.
FIG. 18 is a configuration diagram of a thinning circuit and a thinning control circuit in the case of 1/3, FIG. 18 is a configuration diagram of a write control circuit, FIG. 19 is a diagram showing a write state of the frame memory, FIGS.
FIG. 21 is an explanatory diagram of the even / odd field determination, FIG. 22 is a configuration diagram of the read control circuit, and FIG. 23 is a configuration diagram of a part of the function control unit. 1,3 Input terminal 2 Changeover switch 4 A / D converter 5 Thinning circuit 6 Thinning control circuit 7 Frame memory 8 Write control circuit 9,14 Synchronous separation circuit 10 Write clock generation circuit 11 Overtaking judgment circuit 12 Read control circuit 13 Read clock generation circuit 15 Field judgment circuit 16 Read control circuit 17 D / A converter 18 Monitor Receiver 19 …… Function control unit

Claims (7)

(57) [Claims] 1. Line number counting means for counting the number of scanning lines of one frame of an interlaced input video signal, and a plurality of weighted averaging means for weighting and averaging over one or more scanning lines of the input video signal, respectively. A video signal processing device for reducing the number of scanning lines in one frame of the input video signal and outputting the same as a non-interlaced signal, wherein the weighted averaging means constitutes each of the fields of the input video signal To compensate for the difference in scan line position and the position between each scan line of the non-interlaced signal,
As many as necessary to generate video signals of each scanning line of the non-interlaced signal from the scanning lines constituting each of the fields of the input video signal, the video signal processing device is configured to count the number of lines. A thinning circuit for selectively selecting and outputting one of the plurality of weighted averaging means for each scanning line of the input video signal according to the number of scanning lines counted by the means; Based on the order in which the outputs of the plurality of weighted averaging means are selected in the frame according to the number of scanning lines of one frame counted by the line number counting means, A video signal processing apparatus, wherein the output of the plurality of weighted averaging means is selected and output alternatively for each scanning line. 2. An image processing apparatus comprising: a line number counting means for counting the number of scanning lines in one frame of an interlaced input video signal; and a plurality of weighted averaging means for performing weighted averaging over one or more scanning lines of the input video signal. A video signal processing apparatus for reducing the number of scanning lines in one frame of the input video signal and outputting the same as a non-interlaced signal, wherein the input video signal is processed in accordance with the number of scanning lines counted by the line number counting means. A thinning circuit for selecting and outputting one of the plurality of weighted averaging means for each scanning line of the signal, wherein the weighted averaging means calculates the weighted average of the input video signal over two scanning lines A first weighted averaging unit that performs weighted averaging of the input video signal over three scanning lines; When the number of lines of one frame of the input video signal counted by the stage is an even number, the number of lines from the 3n, 3n + 1, 3n + 2 (n is a positive integer) scanning line signal is 2 for each field of the input video signal. This scan line signal is formed, and these signals are assigned to the scan line signals of each field of the non-interlace signal. In the 3nth line, the current scan line signal and the previous scan line signal are respectively The non-interlaced signal is added at a ratio of 1/2 to be a scanning line signal of a non-interlaced signal. The scanning line signal of the non-interlaced signal is not formed in the (3n + 1) th line, and the current scanning line signal is formed in the (3n + 2) th line. A scanning line signal of one line before and a scanning line signal of two lines before are added at a ratio of 1/4, 1/2 and 1/4, respectively, to obtain a scanning line signal of a non-interlace signal; The number of lines in one frame of the input video signal is 6k + 3 (k
Is a positive integer), the control is repeated every three lines in each frame period based on the frame pulse obtained by dividing the vertical synchronization signal by 1/2, and the scanning line signal of the non-interlace signal is obtained. In the 3n-th line from the frame pulse, the current scanning line signal and the previous scanning line signal are added at a ratio of 1/2, respectively, to obtain a scanning line signal of a non-interlace signal, On the third line, no scanning line signal of a non-interlace signal is formed. On the 3n + 2nd line, the current scanning line signal, the previous scanning line signal, and the second preceding scanning line signal are respectively 1 / The signals are added at a ratio of 4, 1/2 and 1/4 to form a scanning line signal of a non-interlace signal, and the number of lines of one frame of the input video signal is 6k + 1 (k
Is a positive integer), the control is made different between the field where the frame pulse obtained by dividing the vertical synchronization signal by 1/2 and the field where the frame pulse does not exist are controlled every three lines. Are repeated to form a scanning line signal of a non-interlace signal. In a field where a frame pulse exists, the current scanning line signal, the scanning line signal of one line before and the scanning line signal of two lines before in the 3nth line from the frame pulse. The scanning line signal is
Scanning line signals of non-interlaced signals are formed at the ratios of 1/4, 1/2, and 1/4, respectively. On the 3n + 1th line, scanning line signals of non-interlaced signals are not formed, and 3n + 2nd In the line, the scanning line signal of one line before and the scanning line signal of two lines before are added at a ratio of 1/2, respectively, to form a scanning line signal of a non-interlaced signal. On the 3n-th line from the pulse, the current scanning line signal and the previous scanning line signal are added at a rate of 1/2 each to form a scanning line signal of a non-interlaced signal. No scanning line signal of the interlace signal is formed. In the 3n + 2nd line, the current scanning line signal, the scanning line signal one line before and the scanning line two lines before. The line signals are added at 1/4, 1/2, and 1/4, respectively, to form a scanning line signal of a non-interlaced signal, and the 3n + 1st line of the field where the frame pulse exists has the current scanning line. A scanning line signal of a non-interlaced signal is formed from the signal and the scanning line signal of the previous line, and a scanning line signal of a non-interlaced signal is not formed in the (3n + 2) th line. Is 6k + 5, the control is different between the field where the frame pulse obtained by dividing the vertical synchronization signal by 1/2 and the field where the frame pulse does not exist, and the control is repeated every three lines. In the field where the frame pulse exists, the scanning line signal of the non-interlace signal is formed, and in the 3nth line from the frame pulse, Standing of the scanning line signal and 1
The scanning line signals before the line are each added at a ratio of 1/2 to form a scanning line signal of a non-interlaced signal, and the scanning line signal of the non-interlaced signal is not formed in the (3n + 1) th line. In the second line, the current scanning line signal, the scanning line signal one line before and the scanning line signal two lines before are added at a ratio of 1/4, 1/2 and 1/4, respectively, and the non-interlaced signal is added. In a field where a scanning line signal is formed and no frame pulse is present, the current scanning line signal,
The scanning line signal of one line before and the scanning line signal of two lines before are added at a ratio of 1/4, 1/2 and 1/4, respectively, to form a scanning line signal of a non-interlace signal, In the line, the scanning line signal of the non-interlace signal is not formed, and in the 3n + 2nd line, the scanning line signal of the previous line and the scanning line signal of the previous line are added at a rate of 1/2, respectively, and the non-interlaced signal is added. A scanning line signal of an interlaced signal is formed, and a scanning line signal of a non-interlaced signal is formed on a (3n + 1) th line of a field where no frame pulse is present, with respect to a current scanning line signal and a preceding scanning line signal. A video signal processing device characterized in that a scanning line signal of a non-interlace signal is not formed in the 3n + 2nd line. 3. A line number counting means for counting the number of scanning lines of one frame of an interlaced input video signal, and a plurality of weighted averaging means for performing weighted averaging over one or more scanning lines of the input video signal. A video signal processing apparatus for reducing the number of scanning lines in one frame of the input video signal and outputting the same as a non-interlaced signal, wherein the input video signal is processed in accordance with the number of scanning lines counted by the line number counting means. A thinning circuit for selectively selecting and outputting one of the plurality of weighted averaging means for each signal scanning line, wherein the thinning circuit comprises one frame of scanning lines counted by the line number counting means. When the number is even,
The scanning line signal of any field of the video signal is directly assigned to the scanning line signal of each field of the non-interlace signal. When the number of lines of one frame of the input video signal is 2n + 1, the vertical synchronizing signal is halved. (A) The first n scanning line signals of the input video signal are directly assigned to the scanning line signals of one field of the non-interlaced signal in each frame period with reference to the frame pulse obtained by frequency division. b) Subsequently, using the remaining (n + 1) scan line signals of the input video signal, an interpolated scan line signal is formed so that a scan line exists at the same position as the n scan lines. A scanning line signal is assigned to a scanning line signal of the other field of the non-interlace signal, wherein the processing is performed in each frame period;
Video signal processing device. 4. A line number counting means for counting the number of scanning lines in one frame of an interlaced input video signal, and a plurality of weighted averaging means for performing weighted averaging over one or more scanning lines of the input video signal. A video signal processing device for reducing the number of scanning lines in one frame of the input video signal and outputting the reduced number as a non-interlaced signal, wherein the video signal processing device has a number of scanning lines counted by the line number counting means. A thinning circuit for selectively selecting and outputting one of the plurality of weighted averaging means for each scanning line of the input video signal, wherein the thinning circuit counts by the line number counting means. When the number of scanning lines in one frame is an even number,
The scanning line signal of any field of the input video signal is directly assigned to the scanning line signal of each field of the non-interlace signal, and the number of lines of one frame of the input video signal is 2n + 1 (n is a positive integer). Sometimes, the vertical sync signal is
(A) The first n scanning line signals of the input video signal are directly assigned to the scanning line signals of one field of the non-interlace signal, based on the frame pulse obtained by frequency division. The remaining n + 1 scanning line signals of the input video signal are used to form an interpolation scanning line signal such that scanning lines are present at the same positions as the n scanning lines, and the interpolation scanning line signal is (C) The image signal thus formed is arithmetically averaged every two lines to reduce the number of scanning lines to half, and the processing is performed for each frame period. Characterized by being performed in
Video signal processing device. 5. Writing and reading of a signal are performed.
A frame memory capable of asynchronously controlling writing and reading; and write control means for starting writing to the field portion after reading of a signal for one field from the frame memory is completed. 2. The video signal processing device according to claim 1, wherein the video signal output from the thinning circuit is written into the frame memory. 6. The video signal processing device according to claim 5, wherein a signal is read from said frame memory in synchronization with a second video signal different from said input video signal. 7. A function switching means for storing and switching a plurality of sets of a clock frequency, a write range and a read range of the frame memory, and switching the plurality of sets of the clock frequency, the write range and the read range. 7. The video signal processing apparatus according to claim 6, wherein a clock frequency, a writing range, and a reading range can be changed by selecting one set.