JP3394060B2 - Horizontal pan system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub-screen in a wide-screen television, for example, an in-screen screen (P
The present invention relates to the field of wide-screen televisions, in particular the display of IP) displays, in particular the use of sub-video signal processing circuits designed for normal television for mapping sub-screen positions or determining sub-screen positions.

[0002]

BACKGROUND OF THE INVENTION Televisions with a format display ratio of 4: 3, often also referred to as 4x3, have limitations in the way they can display a single video source and multiple video sources. Except for the experimental ones, the transmission of television signals of commercial broadcasting stations is broadcast in a display ratio of 4 × 3 format. Many viewers see that the 4x3 display format is a movie
I think that there is no better than the wider format display ratio than in. Wide format display ratio television
Not only can the display be more comfortable, but the signal source in the wide display format can be displayed in the corresponding wide display format. Movies look like movies without being truncated or distorted. The video source need not be truncated, for example when it is converted from film to video by a telecine device, or even by a television processor.

Televisions with a wide display format ratio display both normal display format signals and wide display format signals in various forms, and display in the form of a multi- screen display that combines signals of these formats. Suitable to do. However, there are many problems associated with using a wide display ratio screen. Common among such problems are changing the display format ratio of multiple sources, generating consistent timing signals from video sources that are displayed asynchronously but simultaneously.
Switching between a plurality of signal sources for multi-screen display, and a high-resolution screen may be generated from the compressed data signal.
Such problems are solved in the wide screen television according to the present invention. Widescreen televisions according to various configurations of the present invention are capable of displaying high resolution single and multiple screen displays from single and multiple video signal sources having the same or different format ratios with selectable display format ratios.

Televisions with a wide display format ratio are both interlaced and non-interlaced, and basic,
That is, it can be implemented in a television system displaying a video signal at both the standard horizontal scanning frequency and its multiples. For example, a standard NTSC video signal is displayed by interlacing successive fields of each video frame, each of which is produced by a raster scan at a basic or standard horizontal scan frequency of approximately 15,734 Hz. The basic scanning frequency for the video signal is variously called f _H , 1 f _H or 1 _H. 1f
The actual frequency of the _H signal will change for different video formats.

In an effort to improve the picture quality of television devices, systems have been developed for sequentially displaying video signals in a non-interlaced manner. Sequential scanning requires each display frame to be scanned at the same time allotted to scan one of the two fields in the interlaced format. Flicker-free AA-BB display requires scanning each field twice in succession. In each case, the horizontal scan frequency should be twice the standard horizontal frequency. The scanning frequency for such progressive scanning display or flicker-free display is 2f _H or 2
There are various names such as H. For example, the 2f _H scan frequency according to the American standard is approximately 31,468 Hz.

Overlay in simultaneous screen display
The rlay-overlap function provides a timing signal to the display to switch from large screen to small screen again at the correct time. Both horizontal and vertical timing of the small screen overlay is important for displaying the small screen. PIs designed for use with 4x3 indicators
The P Processor is a CPIP chip developed by Thomson Consumer Electronics Incorporated of Indianapolis, Indiana, for which the publication CTC 140 In-Screen Display (CPIP) Technical Publications available from the same company.・ Training Manual (The CTC
Picture in Picture (CPIP)
Technical Training Manua
There is a more detailed description in l). This CPIP chip is
It can be used in such a way that the sub-video information is stored in a 6-bit Y, U, V, 8: 1: 1 video RAM field memory.

This video RAM is located in multiple memory locations,
Holds two fields of video data. Each memory location holds 8 bits of data. At each 8-bit position there is one 6-bit Y (luminance) sample and two other bits. These other two bits carry one of the fast switch data and a portion of the U or V samples. The fast switch value is decoded to indicate which of the field formats was written to the video RAM as either an upper (odd) field, a lower (even) field, or no screen (invalid data). A field occupies a spatial location in video RAM with boundaries defined by horizontal and vertical addresses. This boundary is defined at the above address by the change of the fast switch data from no screen to valid field or from valid field to no screen. Such transitions of fast switch data define the perimeter of the screen overlay.

It will be appreciated that the image aspect ratio of objects in the overlay can be controlled independently of the overlay's own format display ratio, eg 4x3 or 16x9. The position of the overlay on the screen is determined by the starting address of the read pointer of the video RAM at the beginning of the scan for each field of the main signal. Since two fields of data are stored in the video RAM and the entire video RAM is read during the display period, both fields are read during the display scanning . Fi <br/> Lumpur de read from memory for display decodes the fast switch data, video RAM
Is determined by setting the starting position of the read pointer of

The problem is that the PIP video processing circuit for the sub video signal is, for example, the CPIP chip described above.
Originally, it would occur with a structure intended for use with a television having a normal format display ratio, i.e. 4x3. Many of such processing circuits are powerful for performing multi-screen display, and by using them, the development of a wide screen television is simplified or promoted. In fact, such a 4x3
Video processing circuits can be PIP'd in many locations depending on the design.
It can be programmed to position the insert screen.

Even in the PIP circuit, which has the widest degree of freedom regarding the layout of the PIP, its position is limited within the boundary of the 4 × 3 display in the horizontal direction, and the vertical dimension is the vertical direction of the widescreen display. Equivalent to the height of. That is, it is impossible to define the position beyond the horizontal boundary of the 4 × 3 video display map defined by the PIP circuit. This display map is a function of the write / read address control associated with the video RAM and PIP circuitry.

There are two approaches, each with significant drawbacks. One is to allow the screen to stretch to fill the widescreen display,
It causes considerable image aspect ratio distortion on both the main screen and the PIP insertion screen. In another method, the sub-video signal is asymmetrically thinned (decimated) to form a small screen, so that the horizontal stretching can be avoided. However, this approach is very difficult because all reduction factors except 3 require a non-integer process, and most PIP processors cannot do any non-integer decimation process. Therefore,
The size of the PIP insertion screen is practically limited to 1/3 of the size of the original screen. In order to embody many possible display formats in widescreen televisions, a wide flexibility in PIP insertion size is needed.

[0012]

SUMMARY OF THE INVENTION A widescreen television device in accordance with the present invention includes a video display having a wide format display ratio and synchronized with a first video signal representing a first screen. The second where the PIP processor represents the second screen
In response to the video signal of the sub-display, the sub-screen having a smaller size than the video display is defined. A FIFO (first in, first out) line memory stores successive lines of video information representing the sub-screens, these lines of video information being combined with certain successive lines of video information representing the first screen. A counter initialized at a time corresponding to the start of each horizontal line of the first video signal produces a variable time delay. A FIFO control circuit causes the lines of video information representing the sub-screen from the line memory to be sequentially transferred for combination with the video information representing the main screen after a variable time delay. This variable time delay
Determine one of a plurality of horizontal pan positions of the sub-screen across the video display. A manual controller, eg, a remote controller, can be used to adjust the variable time delay and thus the horizontal pan position.

The video information representing the sub-screen is generated by the operation of the PIP processor or by the PIP processor and the FI.
Due to the cooperative operation of the FO line memory, it is vertically synchronized with the video display. Each line of the sub-screen displayed on the video display has a number of Bideosa sample with, also, each of the lines of video information to be written to FIFO line memory, with approximately equal number of video samples to the number in the ing.

Each of FIG. 1 illustrates some of the various combinations of single and multiple screen display formats that can be implemented in accordance with the different configurations of the present invention. The ones chosen for illustration are to facilitate the description of certain specific circuits that make up a widescreen television in accordance with the principles of the present invention. The construction of the invention is in some cases directed to the display format itself, apart from the particular underlying circuitry. For convenience of illustration and description, it is generally assumed that the width-to-height ratio of a video source or a normal display format for a video signal is 4 × 3, and the width of a wide-screen display format for a video source or a video signal is generally The height ratio is 16 × 9. The structure of the present invention is not limited by these definitions.

FIG. 1A shows a direct-view type or projection type television having a display ratio of 4 × 3 in a normal format. 16 × 9 format display ratio screen is 4 × 3
When transmitted as a format display ratio signal, black bars appear at the top and bottom. This is generally called a mail box format. In this case, the observed screen is small with respect to the display area available for display.
Alternatively, a 16 × 9 format display ratio source may be converted prior to transmission to fill the viewing plane vertically of a 4 × 3 format display. However, in that case, considerable information is truncated from the left and / or right side. In yet another alternative, the postbox format can be stretched vertically instead of horizontally, but this causes distortion due to vertical stretching. None of these three methods are particularly attractive.

FIG. 1B shows a 16 × 9 screen. Video sources with a display ratio of 16x9 format are perfectly displayed without truncation and without distortion. 16 × 9 format display ratio letterbox display (which is in the form of a 4 × 3 format display ratio No. signal originally) is to perform large display with sufficient vertical resolution, Senbaika (line doubling ) Or line addition (line addition). A widescreen television according to the present invention can display such a 16x9 format display ratio signal regardless of the primary video source, secondary video source, or external RGB source.

FIG. 1 (c) shows a main signal of 16 × 9 format display ratio in which an insertion screen of 4 × 3 format display ratio is inserted and displayed. If both the primary and secondary video signals are 16x9 format display ratio sources, the inset screen will also have a 16x9 format display ratio. The inset screen can be displayed in many different positions.

FIG. 1D shows a display format in which the main and sub video signals are displayed as a screen of the same size. Each display area has a format display ratio of 8x9, which of course differs from 16x9 and 4x3. In order to display a 4 × 3 format display ratio source in such a display area without horizontal or vertical distortion, the left and / or right side of the signal must be truncated. If you tolerate some aspect ratio distortion due to horizontal screen squeezing, more of the screen can be displayed. As a result of the horizontal packing, things in the screen become vertically elongated. The wide-screen television of the present invention can perform any combination of truncation and aspect ratio distortion, from maximum truncation processing with no aspect ratio distortion to no truncation with maximum aspect ratio distortion.

[0019] the sub-video signal processing paths have data sampling limitations, display the same size as the generation of high-resolution screen from the main video signal becomes complicated. Various methods can be developed to eliminate such complications.

FIG. 1 (e) shows a display format in which a display ratio screen of 4 × 3 format is displayed in the center of a 16 × 9 format display ratio screen. Black bars appear on the left and right sides.

FIG. 1 (f) shows a display format in which one large 4 × 3 format display ratio screen and three small 4 × 3 format display ratio screens are displayed simultaneously.
A small screen outside the periphery of a large screen is sometimes a PI
P, that is, not the in-screen screen (parent-child screen), but POP,
That is, it is called an off-screen screen. The term PIP or in-screen screen (picture in picture) is used in these specifications for these two display formats. If two tuners widescreen television is provided, even if <br/> provided inside both, in one of the interior, one is outside, for example, it is provided in the video cassette recorder Even then, two of the display screens can display movement in real time according to the video source. The remaining screens can be displayed in still screen format. If a tuner and a sub-signal processing path are added, 3
It can be understood that the above moving screen can be displayed. Also,
It is also possible to switch the positions of the large screen and the three small screens as shown in FIG.

FIG. 1 (h) shows another display in which the 4 × 3 format display ratio screen is displayed in the center and the six small 4 × 3 format display ratio screens are displayed in columns on both sides.
Similar to the format described above, a wide screen television provided with two tuners can display two moving screens. Then, the remaining 11 screens are displayed in the still screen format.

FIG. 1 (i) shows a checkerboard display format of 12 4 × 3 format display ratio screens. Such a display format is particularly suitable for channel selection guides, where each screen is at least a static screen from a different channel. As in the previous example, the number of moving screens depends on the number of tuners and signal processing paths available.

The various formats shown in FIG. 1 are exemplary and not limiting, and are shown in the remaining figures,
It can be realized by a wide screen television described in detail below.

A general block diagram of a wide screen television for 2f _H horizontal scanning according to the arrangement of the present invention is shown in FIG. Generally speaking, the television 10 includes a video signal input unit 20, a chassis or TV microprocessor 216, a wide screen processor 30, 1f _H.
A −2f _H converter 40, a deflection circuit 50, an RGB interface 60, a YUV-RGB converter 240 (for which industrial type TA7730 can be used), a picture tube drive circuit 242, a direct-view type or projection type tube 244, and , Power supply 70 is included. The grouping of various circuits into different functional blocks is for convenience of description and is not intended to limit the physical positional relationship between such circuits.

The video signal input section 20 is adapted to receive a plurality of composite video signals from different video sources. Video signals as the main video signal and the sub video signal, can be switched to the selected択的for display. The RF switch 204 has two antenna inputs AN1 and AN2. These inputs represent inputs for both reception by the radio broadcast antenna and reception from the cable. RF
The switch 204 controls which antenna input is supplied to the first tuner 206 and the second tuner 208. The output of the first tuner 206 is one chip 2
It becomes the input to 02. One chip 202 is a tuning control,
It performs many functions related to horizontal and vertical deflection control, video control. One chip shown is TA7777 for industrial use.
Is.

Baseband video signal VIDEO generated in one chip from the signal from the first tuner 206
OUT becomes an input to the TV1 input of the video switch 200 and the wide screen processor 30. The other baseband video input to the video switch 200 is AUX1.
And AUX2. These inputs can be used in video cameras, laser disc players, video tape players video games and the like. The output of the video switch 200 controlled by the chassis or the TV microprocessor 216 is the switching video ( SWITCH
ED VIDE O) . This SWITCH
The ED VIDEO is provided as a separate input to the widescreen processor 30.

Referring to FIG. 3, widescreen pro <br/> switch SW1 in set Sa 30, Y / C decoder 21
One of the TV1 signal and the SWITCHED VIDEO signal is selected as the SEL COMP OUT video signal to be an input to 0. The Y / C decoder 210 can be implemented in the form of an adaptive line comb filter. Y / C decoder 21
Two video sources S1 and S2 are also input to 0. S1 and S2 each represent a different S-VHS source,
Each consists of a separate luminance signal and chrominance signal. Y / with some adaptive line comb filters
A switch that may be implemented as part of the C decoder or may be implemented as a separate switch is a TV
In response to the microprocessor 216, Y_M and C_
A pair of luminance and chrominance signals is selected as the output labeled IN.

The selected paired luminance and chrominance signals are then regarded as the main signal and are processed along the main signal path. Signal notations including _M or _MN represent the main signal path. Chrominance signal C_IN
Is therefore a widescreen-processor 30, returned again to one chip, the color difference signals U_M and V_M is generated. Here, U represents the same as (RY), and V
Is equivalent to (BY). Y_M, U_M and V_M
Signal for subsequent signal processing, to convert widescreen <br/> processor 30 to digital form.

Functionally, the wide screen processor 3
A second tuner 208, defined as part of 0, produces the baseband video signal TV2. Switch SW2
The TV2 signal and the S signal are input to the Y / C decoder 210 .
Select one of the WITCHED VIDEO signals. Y / C
Decoder 210 can be implemented as an adaptive line comb filter. The switches SW3 and SW4 are used for the Y / C decoder 22.
0 luminance and chrominance outputs, and Y_
Select one of the luminance and chrominance signals of the external video source designated EXT and C_EXT. The Y_EXT and C_EXT signals correspond to the S-VHS input S1. Y
The / C decoder 220 and the switches SW3 and SW4, as is done in some adaptive line comb filters,
You may combine.

The outputs of the switches SW3 and SW4 are then considered the sub-signal and are processed along the sub-signal path. The selected luminance output is shown as Y_A. Signal notations including _A, _AX and _AUX are used for the sub-signal paths. The selected chrominance is converted into color difference signals U_A and V_A. Y_A signal,
The U_A and V_A signals are converted to digital form for subsequent signal processing. The configuration of switching video signal sources in the main and sub-signal paths allows for greater flexibility in how to select video sources for different portions of different screen display formats.

Composite sync signal COMP corresponding to Y_M
SYNC is provided from widescreen processor 30 to sync separator 212. Horizontal and vertical sync components H and V
Is input to the vertical countdown circuit 214. The vertical countdown circuit generates a VERTICAL RESET (vertical reset) signal supplied to the wide screen processor 30. Widescreen processor 30
Generates an internal vertical reset output signal INT VERT RST OUT which is supplied to the RGB interface 60. A switch in the RGB interface 60 selects between the internal vertical reset output signal and the vertical sync component of the external RGB source. The output of this switch is the deflection circuit 5.
Selected vertical sync component SEL_VER supplied to 0
T_SYNC. The horizontal and vertical sync signals of the secondary video signal are generated by sync separator 212 in widescreen processor 30.

The 1f _H -2f _H converter 40 functions to convert the interlaced scanning video signal into a non-interlaced signal which is sequentially scanned. For example, each horizontal line is displayed twice, or additional horizontal line sets are generated by interpolation of adjacent horizontal lines in the same field. In some examples, whether to use the previous line or the interpolated line depends on the level of motion detected between adjacent fields or frames. The conversion circuit 40 operates in association with the video RAM 420 . This video RA M
420 is used to store one or more fields of a frame for sequential display. Y
The converted video data as the —2f _H , U — 2f _H and V — 2f _H signals are provided to the RGB interface 60.

The RGB interface 60, shown in detail in FIG. 14, for display by the video signals input section, allow conversion video data or <br/> selection of external RGB video data. The external RGB signals are wide format display ratio signals adapted for 2f _H scanning. The vertical sync component of the main signal is sent to the RGB interface by the wide screen processor and the internal vertical
Tsu Doo output (I NT VERT RST OU T) and to be supplied, selected vertical sync _{(f Vm} or f
_Vext ) can be supplied to the deflection circuit 50. By this operation of the wide screen television, the internal / external control signals INT / EXT are generated to generate the external RG.
The user can select the B signal. However, if such an external RGB signal does not exist, the external RGB
The choice of signal input can result in vertical collapse of the raster and damage to the cathode ray tube or projection tube. Therefore, the RGB interface circuit detects the external sync signal to nullify the nonexistent external RGB input selection. The WSP microprocessor 340 also
Perform color and tone control for the external RGB signal.

The wide screen processor 30 includes a picture-in-picture circuit 301 which performs special signal processing of the sub video signal. The term screen-on-screen sometimes refers to PIP or pix-in-pix (p
ix-in-pix). Gate array 30
0 as shown in the example of FIGS. 1 (a)-(i),
Combines primary and secondary video signal data in various display formats. The picture-in-picture circuit 301 and gate array 300 are under the control of a widescreen processor microprocessor (WSP μP) 340. The microprocessor 340 is connected to the T bus via the serial bus.
Responsive to the V microprocessor 216. The serial bus contains four signal lines for data, clock signals, enable signals and reset signals. The widescreen processor 30 also provides a composite vertical blanking / reset (COMPOSITE VERTICA) as a 3-level sandcastle (castle made of sand) signal.
L--BLANKING / RESET) signal.
Alternatively, the vertical blanking signal and the reset signal may be generated as separate signals. The composite blanking signal is supplied to the RGB interface 60 by the video signal input section.

The deflection circuit 50 is shown in more detail in FIG. 13 is a widescreen-processor 30 or we vertical reset signal, the 2f _H horizontal synchronizing signal is selected from the RGB interface 60, also widescreen-processor 30
Receive pressurized et additional control signal. This additional control signal relates to horizontal phase adjustment, vertical size adjustment, and left / right pin adjustment. The deflection circuit 50 outputs the 2f _H flyback pulse to the wide screen processor 30, 1f _H −.
The 2f _H converter 40 and the YUV-RGB converter 240 are supplied.

The operating voltage for the entire widescreen television is generated, for example, by a power supply 70 which can be powered by an AC mains power supply.

The widescreen processor 30 is shown in more detail in FIG. The main <br/> principal components of the wide screen-processor 30, the gate array 300, picture-in-picture circuit 30
1, an analog-digital converter and a digital-analog converter 342, 346, a second tuner 208, a widescreen processor / microprocessor 340 and a widescreen output encoder 227. A detailed portion of the widescreen processor common to both 1f _H and 2f _H chassis, eg, PIP circuitry, is shown in FIG. The in-screen screen processor 320, which forms an important part of the PIP circuit 301, is shown in more detail in FIG. The gate array 300 is also shown in more detail in FIG. The large number of elements forming the main and sub-signal paths shown in FIG. 3 have already been described in detail.

The second tuner 208 includes an IF stage 224.
And an audio stage 226 is attached. The second tuner 208 also works with the WSP μP 340.
WSP μP 340 includes input / output I / O unit 340A and analog output unit 340B. I / O section 340A
Is a tint control signal and color control signal, external R
An INT / EXT signal for selecting a GB video source and a control signal for the switches SW1 to SW6 are supplied.
I / O unit, and in order to protect the deflection circuit and cathode ray tube, EXT SYNC of RGB interface 60 or al
Monitor the DET signal. Analog output section 340B
Supplies control signals for vertical size, left and right adjustment and horizontal phase through respective interface circuits 254, 256 and 258.

The gate array 300 by combining the video information from the main and auxiliary signal paths, the composite wide screen display, for example, although shown in the individual parts of the FIG. 1 1
Work to make one. The clock information for the gate array is provided by the phase locked loop 374 which works in concert with the low pass filter 376. The main video signal is in analog form and is provided to the widescreen processor in YUV format as the signals labeled Y_M, U_M and V_M. These main signals are converted from analog to digital form by analog-to-digital converters 342 and 346 shown in more detail in FIG.

The color component signals are designated by the superordinate notations U and V, which are RY or
It can be attached to the BY signal or the I and Q signals. Since the system clock frequency is a 1024f _H (This is Ru about 16MHz der), samples bandwidth luminance is limited to 8 MHz. 50 U and V signals
0 KHz or 1.5 MHz for wide I
Because it is limited to, the color component data sampling
Is one analog - may be performed by the digital converter and an analog switch. This analog switch, that is,
The select line UV_MUX for the multiplexer 344 is
It is an 8 MHz signal obtained by dividing the system clock by 2.

A 1 clock wide line start SOL pulse synchronously resets this signal to 0 at the beginning of each horizontal video line. The UV_MUX line then reverses state every clock cycle through its horizontal line. Since the line length is an even multiple of the clock cycle, once initialized, the UV_MUX state is 0, without interruption.
It changes to 1, 0, 1, ... The Y and UV data streams from analog to digital converters 342 and 346 are
The analog-to-digital converters each have a delay of one clock cycle and are therefore shifted. This to accommodate the data shift, must also be delayed like clock gate information of the interpolator controller 349 or al of the main signal processing path 304. If this clock gating information is not delayed, the UV data will not be properly paired when the deletion is performed. This point is for each U
This is important because the V pair represents a vector.

When the U component from one vector is paired with the V component from another vector, a color shift occurs. The V samples from the preceding pair are deleted along with the current U samples. This UV multiplex method
It is called 2: 1: 1 because there are two luminance samples for each color component (U, V) sample pair. U
And the Nyquist frequency for both V and V is effectively reduced to one half of the Nyquist frequency of the luminance. Therefore, the Nyquist frequency of the output of the analog-digital converter for the luminance component is 8 MHz, while
The Nyquist frequency of the output of the analog-digital converter for the color component is 4 MHz.

The PIP circuit and / or the gate array is
Means may be included so that the resolution of the sub-data is enhanced even with data compression. For example, paired
Pixel compression and dithering and Dedizarin grayed (Gyakude
Data reduction and data recovery schemes have been developed , including Furthermore, different dithering sequences with different numbers of bits and different pairs of pixel compressions with different numbers of bits have been considered. One of a number of specific data reduction and recovery schemes can be selected by the WSP μP 340 to maximize the resolution of the displayed video for each particular screen display format.

[0045] Getoare over 300 includes interpolators which operate in conjunction with line memories, which can be implemented as FIFO356 and 358. The interpolator and FIFO are used to resample the main signal as needed. The side signal can be resampled by a separate interpolator. Clock and synchronizing circuits in Getoare over 300 is a combination of primary and secondary signals, Y_MX, U_MX and V
Controls data manipulation of both primary and secondary signals, including producing one output video signal with the _MX component. The output components are converted to analog form by digital-to-analog converters 360, 362 and 364. Y, the signal in analog form indicated by U and V, for conversion to non-interlaced _scanning, are supplied to the 1f H -2f _H converter 40.
Also, the Y, U and V signals are output by the encoder 227 to Y
Wide format ratio output signal Y_OUT_EXT encoded into the C / C format and output to the jack on the panel.
_ / C_OUT_EXT is generated. Switch SW5
Provides a sync signal for encoder 227 with C_SYNC_MN from the gate array and C_ from the PIP circuit.
Select from SYNC_AUX. The switch SW6 serves as a synchronization signal for outputting the wide screen panel, Y_M.
Or C_SYNC_AUX.

The portion of the horizontal sync circuit is shown in more detail in FIG. The phase comparator 228 is part of a phase locked loop including a low pass filter 230, a voltage controlled oscillator 232, a divider 234 and a capacitor 236. The voltage controlled oscillator 232 operates at 32f _H in response to a ceramic resonator or equivalent 238. The output of the voltage controlled oscillator is divided by 32 and provided to the phase comparator 228 as a second input signal at the appropriate frequency. The output of divider 234 is the 1f _H REF timing signal. 32f _H REF timing signal and 1f _H REF
The timing signal is supplied to the 1/16 counter 400. The 2f _H output is supplied to the pulse width circuit 402. By presetting the frequency divider 400 with the 1f _H REF signal, the frequency divider is guaranteed to operate synchronously with the phase locked loop of the video signal input.

The pulse width circuit 402 ensures that the 2f _H -REF signal has a sufficient pulse width to allow the phase comparator 404, eg, CA 1391, to operate properly. The phase comparator 404 includes a low pass filter 406.
And a 2f _H voltage controlled oscillator 408 to form part of a second phase locked loop. Voltage controlled oscillator 408 generates an internal 2f _H timing signal, which is used to drive a progressively scanned display. The other input signal to the phase comparator 404 is a 2f _H flyback pulse or timing signal associated therewith. The use of a second phase locked loop including phase comparator 404 helps to make each 2f _H scan period symmetrical within each 1f _H period of the input signal. Failure to do so would result in raster separation, eg, half of the video lines would shift to the right and half of the video lines would shift to the left.

The deflection circuit 50 is shown in detail in FIG. Circuitry 500 is provided to adjust the vertical size of the raster depending on the amount of vertical overscan required to achieve different display formats. As shown diagrammatically, a constant current source 502 provides a constant amount of current I _RAMP that charges a vertical ramp capacitor 504.
A transistor 506 is coupled in parallel with the vertical ramp capacitor and periodically discharges this capacitor in response to a vertical reset signal. Without any adjustment, the current I _RAMP gives the raster the maximum possible vertical size. This is an enlargement 4 ×, as shown in FIG.
The 3 format display ratio signal source accommodates the magnitude of vertical overscan required to fill a widescreen display.

If a smaller vertical raster size is required, the adjustable current source 508 diverts a variable amount of current I _ADJ from I _RAMP to provide vertical ramp capacitor 5
Charge 04 more slowly to a smaller peak value. The variable current source 508 is responsive to the vertical size adjustment signal, eg, in analog form, generated by the vertical size control circuit. 0 vertical size adjustment circuit 50 is independent of a manual vertical size adjustment circuit 51 0, the manual vertical size adjustment can be performed by a potentiometer or back panel adjustment knob. In any case,
The vertical deflection coil 512 receives an appropriate amount of drive current. Horizontal deflection is provided by the phase adjustment circuit 518, the left and right pin correction circuit 514, the 2f _H phase lock loop 520, and the horizontal output circuit 516.

The RGB interface 60 is shown in more detail in FIG. The final signal displayed is
It is selected from the output of the 1f _H -2f _H converter 40 and the external RGB input. To describe the widescreen television described herein, assume that the external RGB input is a progressive scan source with a wide format display ratio. The external RGB signal and the composite blanking signal from the video signal input unit 20 are input to the RGB-YUV converter 610. External RGB
The external 2f _H composite sync signal for the signal is input to the external sync signal separator 600. The vertical synchronizing signal is selected by the switch 608. The switch 604 selects the horizontal synchronizing signal. The selection of the video signal is performed by the switch 606. Switches 604, 60
6, 608 each responds to internal / external control signals generated by WSP μP 340.

The choice of internal video source or external video source is a user choice. However, the external RG
If the user inadvertently selects such an external source when the B source is not connected or turned on, or if there is no external source, the vertical raster collapses and the cathode ray tube is broken. Can cause serious damage. Therefore, the external sync detector 602 detects the presence of the external sync signal. If this signal is not present, the switch invalidation control signal will be sent to each switch 604, 606, 608.
To prevent such an external RGB source from being selected when there is no signal from the external RGB source. RGB
The-YUV converter 610 also receives color and color control signals from the WSP μP 340.

Although not shown, the wide-screen television according to the structure of the present invention can be implemented by 1f _H horizontal scanning instead of 2f _H horizontal scanning. 1f
_{If the H} circuit is used, neither the 1f _H -2f _H converter nor the RGB interface is required. Therefore, there is no means for displaying the external wide format display ratio RGB signal of the 2f _H scanning frequency. The wide screen processor for the 1f _H circuit and the in-screen screen processor will be very similar. The gate array may be substantially the same, but not all inputs and outputs will be used. The various resolution enhancement schemes described herein generally refer to televisions operating at 1f _H scan, 2f _H
It can be adopted regardless of whether it operates by scanning.

[0053] Figure 4 is a block diagram depicting in further detail the wide screen processor 30 shown in FIG. 3 that can be the same for both the 1f _H and 2f _H chassis. In-screen screen processor 3 where Y_A, U_A and V_A signals may include resolution processing circuitry 370.
It becomes 20 inputs. A widescreen television according to one aspect of the invention is capable of video decompression and compression. A special effect realized by various composite display formats, a part of which is shown in FIG.
Generated by 20. The processor 320 can be configured to receive the resolution processed data signals Y_RP, U_RP and V_RP from the resolution processing circuit 370. Resolution processing is not always necessary and is done during the selected display format. In-screen screen processor 320 is shown in more detail in FIG. Major component of the screen within the screen processor 320, an analog - digital converter section 322, an input unit 324, fast switch (F
SW) and bus unit 326, timing and control unit 32
8 and a digital-analog converter 330. Details of the timing and control unit 328 are shown in FIG.

The screen processor 320 in the screen is, for example,
It can be implemented as a modification of the basic CPIP chip developed by Thomson Consumer Electronics Incorporated. Details of this basic CPIP chip can be found in "The CTC 140," published by Thomson Consumer Electronics, Inc. of Indianapolis, Indiana.
Picture in Picture (CPIP) Te
mechanical Training Manual (C
TC 140 In-Screen Display (CPIP) Technical Training Manual) ”.

Many features or special effects are possible. The following is an example. The basic special effects are shown in Figure 1.
A small screen is placed on a large screen as shown in (c). These large and small screens may come from the same video signal or different video signals, and they can be interchanged. In general, audio signals are always switched to accommodate large screens. It small picture can be moved to any position on the screen, or can be moved to a number of predetermined positions. The zoom effect increases or decreases the size of the small screen to, for example, any of a number of preset sizes. At a certain point, for example, in the case of the display format shown in FIG. 1D, large and small screens have the same size.

Single screen mode, eg, FIG.
In the case of the mode shown in (e) or (f), the user
The content of the single screen is, for example, 1.0: 1 to 5.1:
It that-out is in <br/> to zoom in stepwise in a range of 1 ratio. The's Mumodo, the user searches the screen contents, or panning, the image on the screen can be moved in different regions of the screen. In any case, a small screen, a large screen, or a zoomed screen can be displayed as a still screen (still screen format).
This feature enables a strobe format that repeatedly displays the last 9 frames of video on the screen. The frame repetition rate can vary from 30 to 0 frames per second.

The in-screen screen processor used in a widescreen television according to another configuration of the present invention differs from the current configuration of the basic CPIP chip described above. If the basic CPIP chip is used with a television having a 16x9 screen and no video speedup circuit is used, by scanning a wide 16x9 screen, the effective horizontal 4/3 times is obtained. Is increased, which causes distortion of the aspect ratio. Things on the screen are horizontally elongated. When the external speedup circuit is used, aspect ratio distortion does not occur, but the screen does not fill the entire screen.

Existing in-screen screen processors based on basic CPIP chips, such as those used in conventional television, are operated in a special way with some undesirable consequences. Incoming video is sampled with a 640f _H clock locked to the horizontal sync signal of the primary video source. That is, the data stored in the video RAM associated with the CPIP chip is not ortho-gonally sampled with respect to the incoming secondary video source. This is the fundamental limitation on field synchronization by the basic CPIP method. Due to the non-orthogonal nature of the input sampling rate, skewed errors occur in the sampled data. This limitation is the video RAM
Is the result of using a CPI chip that must use the same clock to write and read data. When data from video RAM, such as video RAM 350, is displayed, skew errors appear as random jitter along the vertical edges of the screen and are generally considered very annoying.

Unlike the basic CPIP chip, the in-screen screen processor 320 according to the present invention has been modified to asymmetrically compress the video data in one of a plurality of display modes. In this mode of operation, the screen is compressed 4: 1 horizontally and 3: 1 vertically. This asymmetric compression mode produces a screen with aspect ratio distortion and stores it in video RAM.
Things on the screen are packed horizontally. However, when these screens are read as usual, for example in channel scan mode, and displayed on a 16x9 format display ratio screen, the screens look correct. This screen fills the screen and has no aspect ratio distortion. With the asymmetric compression mode according to this aspect of the invention, it is possible to create a special display format on a 16x9 screen without the use of external speedup circuitry.

FIG. 11 is a block diagram of the timing and control unit 328 of the in-screen screen processor in which the above CPIP chip is changed, for example, and this timing and control unit 328 is one of a plurality of selectable display modes. Decimation (deci) for performing asymmetric compression as
mation-decimation) circuit 328C. The remaining display modes can generate sub-screens of different sizes.
Each horizontal and vertical decimation circuit is WSP μP
It includes a counter programmed under 340 control to determine the compression factor from a table of values. The range of values can be 1: 1, 2: 1, 3: 1 etc. The compression factors can be symmetrical or asymmetrical, depending on how the table is organized. The compression ratio is controlled by WSP
It can be done by a fully programmable general purpose decimation circuit under the control of the μP340.

[0061] In all screen PIP modes, picture-in-picture processor 320 work with free-running oscillator 348, for example receives the Y / C input from a decoder, which may be adapted shape line comb filter, the signals Y, U , V color components to generate horizontal and vertical sync pulses.
These signals are processed by the in-screen screen processor 320 for various full screen modes such as zoom, still, and channel scan. For example, during the channel scan mode, horizontal and vertical syncs from the video signal input may be such that the sampled signals (different channels) have unrelated sync pulses, and are apparently random in time. It will be interrupted many times because it can be switched with. Therefore, the sample clock (and read / write video RAM clock) is determined by the free running oscillator. For stationary and zoom modes, the sample clock is locked to the incoming video horizontal sync signal. In these special cases, the frequency of the incoming video horizontal sync is the same as the display clock frequency.

[0062] Referring again to FIG. 4, picture-in-picture process <br/> Tsu support 320 or these analog form of Y, U, V and C_
The SYNC (composite sync) output can be re-encoded into Y / C components at encoder circuit 366. The encoder circuit 366 operates in cooperation with the 3.58 MHz oscillator 380. This Y / C_PIP_ENC signal is a re-encoded Y
The / C component may be connected to a Y / C switch (not shown) that allows the / C component to be used in place of the Y / C component of the main signal. From this point onward, the PIP encoded Y, U, V and sync signals are the basis for horizontal and vertical timing in the rest of the chassis. This mode of operation is suitable for implementing the zoom mode of the PIP based on the operation of the interpolator and FIFO in the main signal path.

Still referring to FIG. 5, the in-screen screen processor 320 includes an analog-digital conversion section 322, an input section 324, a high speed switch FSW and a bus control section 32.
6, a timing and control unit 328, and a digital-analog conversion unit 330. In general, the in-screen screen processor 320 digitizes the video signal into luminance (Y) and color difference signals (U, V), subsamples the results, and stores them in the 1 Mbit video RAM 350 as described above. In-screen screen processor 32
The video RAM 350 attached to 0 has a memory capacity of 1 megabit, which is not large enough to store one full field of video data in 8 bit samples. Increasing memory capacity would be expensive and would require more complex operating circuitry.
Reducing the number of bits per sample in the sub-channel means a reduction in quantization resolution or bandwidth for the main signal, which is processed with 8-bit samples throughout.

This effective bandwidth reduction is usually not a problem when the sub-display screen is relatively small, but when the sub-display screen is relatively large, for example, the same size as the main display screen. , Could be a problem. The resolution processing circuit 370 may selectively implement one or more concepts to enhance the quantization resolution or effective bandwidth of the secondary video data. For example, numerous data reduction and data recovery schemes have been developed that include anti-pixel compression and dithering and inverse dithering. The dithering circuit is located downstream of the video RAM 350, eg, in the sub-signal path of the gate array, as will be described in more detail below. Furthermore, different dithering and de-dithering sequences with different numbers of bits and different pairwise pixel compression with different numbers of bits are possible. In order to maximize the resolution of the displayed video for each particular screen display format, one of many specific data reduction and recovery schemes is used.
It can be selected depending on SP μ P340.

The luminance and color difference signals are stored in 8: 1: 1 6-bit Y, U, V format. That is, each component is quantized into 6-bit samples. There are 8 luminance samples for each pair of color difference samples. Picture-in-picture processor 320, the incoming video data is caused to operate in a mode as samples in locked to incoming sub video synchronization signal 640 f _H clock frequency. In this mode, the data stored in video RAM is orthogonally sampled. When the data is read from the video RAM 350 of the in-screen screen processor, this data is read using the same 640f _H clock locked to the incoming secondary video signal. However, this data is orthogonally sampled and stored, and can be read orthogonally, but due to the asynchrony of the primary and secondary video sources, cannot be directly displayed from video RAM 350. The primary and secondary video sources are considered to be in sync only when they are displaying signals from the same video source.

Further processing is required to synchronize the sub-channel, which is the output of data from the video RAM 350, with the main channel. Referring again to FIG. 4, two 4-bit latches 352A and 352B are used to recombine the 8-bit data block from the 4-bit output port of the video RAM. The 4-bit latches, the data clock frequency from 1280f _H 640
Lower to f _H.

Generally, the video display and deflection system is synchronized to the main video signal. As mentioned above, the main video signal must be sped up in order to fill the widescreen display. The secondary video signal must be vertically synchronized with the first video signal and the video display. The sub video signal can be delayed in the field memory by a fraction of one field period and expanded in the line memory. The synchronization of the sub video data to the main video data is performed by using the video RAM 350 as a field memory and the first-in first-out (FIFO) line memory device 354 for signal expansion. The size of the FIFO 354 is 2048 × 8.
The size of the FIFO is related to the minimum line storage capacity reasonably considered necessary to avoid read / write pointer collisions. Read / write pointer collisions occur when old data is read from the FIFO before it is time for new data to be written to the FIFO. Collision of the read / write pointer is, also, before you come when the old data is read from the FIFO, write it heavy the new data on the Note Li (overwr
It also occurs when you ite). .

8-bit DA from video RAM 350
TA_PIP data block, the same picture-in-picture as that used to sample the video data processor 3
20 of 64 0f _H clock, i.e., using a 640 f _H clock which is locked to the auxiliary signal rather than the main signal 2048
Written to × 8 FIFO 354. FIFO354 is
10 locked to the horizontal sync component of the main video channel
It is read using the display clock of 24f _H. By using a multi-line memory (FIFO) having independent read and write port clocks, data sampled orthographically at the first frequency can be orthographically displayed at the second frequency. However, due to the asynchronous nature of both read and write clocks, it is necessary to take measures to avoid read / write pointer collisions .

The main signal path 304, the sub-signal path 306 and the output signal path 312 of the gate array 300 are shown in block diagram form in FIG. The gate array further includes a clock / synchronization circuit 320 and a WSP μP decoder 310. WSP DAT of WSP μP decoder 310
The data and address output lines indicated by A are similar to the in-screen screen processor 320 and the resolution processing circuit 370.
It is also supplied to the main circuit and signal path described above. Whether or not a circuit forms a part of the gate array is almost a matter of convenience for facilitating the description of the structure of the present invention.

The gate array acts to decompress, compress, or truncate the main video channel as needed to implement different screen display formats. Luminance component Y_MN is a first-in first-out (FIFO) for a length of time according to the nature of the interpolation of the luminance component.
It is stored in the line memory 356. The combined chrominance component U / V_MN is stored in FIFO 358. Luminance and chrominance components of the side signal Y_PIP, U
_PIP and V_PIP are generated by the demultiplexer 355. If necessary, the luminance component is subjected to resolution processing by the circuit 357, and if necessary, the interpolator 3
It is expanded by 59 to produce the signal Y_AUX as output.

In some cases, the sub-display may have the same size as the main signal display as shown in FIG. 1 (d). Due to the memory limitations associated with the on-screen screen processor and the video RAM 350, there may be a lack of data points, or pixels, to fill such a large area. In such a case, the resolution processing circuit 357 can be used to recover the pixels that should replace the pixels lost during data compression or reduction into the sub video signal. This resolution processing is performed by the circuit 370 shown in FIG.
Can correspond to what is done by. For example, the circuit 370 is a dithering circuit and the circuit 357 is
It can be Gyakude Izaringu circuit.

Sub-signal interpolation can be performed on the sub-signal path 306. The PIP circuit 301 has a 6-bit Y, U,
V, 8: 1: 1 field memory, video RAM 350
To store incoming video data. Video R
The AM 350 holds two fields of video data in a plurality of memory locations. Each memory location holds 8 bits of data. One 6-bit Y for each 8-bit position
There is a (luminance) sample (sampled at 640f _H ) and two other bits. These two other bits carry part of the fast switch data (FSW_DAT) or U or V samples (sampled at 80f _H ). This FSW_DAT value indicates which type of field has been written in the video RAM as follows.

[Equation 1]

These fields are in the video RAM,
It occupies a spatial location with boundaries defined by horizontal and vertical addresses, as suggested by the diagram showing memory locations in FIG. This boundary is defined for each address by changing the fast switch data from no screen to a valid field or from a valid field to no screen. Such transitions of fast switch data define the perimeter of the PIP insertion screen, also called the PIP box or PIP overlay. The image aspect ratio of objects in the PIP screen can be controlled regardless of the format display ratio of the PIP box or overlay, eg 4x3 or 16x9.

The position of the PIP overlay on the screen is determined by the start address of the video RAM read pointer at the start of the scan for each field of the main signal. Data for two fields is stored in the video RAM 350, and the video RAM 3 is stored during the display period.
Since the entire 50 is read, both fields are read during the display scan. The PIP circuit 301 uses the fast switch data and the start position of the read pointer to determine which field should be read from memory for display. When the display locked to the main video source is displaying the upper field of the main screen, the part of the video RAM corresponding to the upper field of the sub screen is then read from the video RAM and converted into analog data. It seems to be done and displayed.

This is true for about half of all possible phase relationships between the primary and secondary video sources. The problem arises because for compressed screens in PIP mode, reading video RAM is always faster than writing to video RAM. If the same field format is written and read at the same time, the read memory pointer will catch up with the write pointer. When this happens, there is a 50% chance of a motion tear somewhere on the small screen. Therefore, in order to address this motion decoupling problem, the PIP circuit always reads the field format opposite the one currently written. If the field format being read is the reverse of the field format being displayed, then the video RA
The even field stored in M is inverted when read from memory, with the top line of the field removed. As a result, the small screen maintains the correct interlaced relationship without causing motion segmentation. This field synchronization will eventually cause the CPIP chip to
It provides a signal called IP_FSW. This is the overlay signal that the PIP circuit supplies to the analog switch that switches between the main and sub channel Y / C (luminance information and modulated chrominance video information) signals.

Referring to FIGS. 4 and 10, the secondary video input data is sampled at a frequency of 640f _H and video R
It is stored in the AM 350. Sub data is video RAM35
It is read from 0 and is shown as VRAM_OUT. The PIP circuit 301 can also reduce the sub-screen asymmetrically in the horizontal and vertical directions, and at the same time, reduce it by a factor of the same integer. The sub-channel data includes 4-bit latches 352A and 352B and sub-F.
IFO 354, timing circuit 369 and synchronization circuit 37
1 buffered and synchronized to the main channel digital video. The VRAM_OUT data is supplied to the Y (luminance), U, and V by the demultiplexer 355.
(Color component) and FSW_DAT (high speed switch data). FSW_DAT indicates which field type was written to the video RAM. PIP_F
The SW signal is supplied directly from the PIP circuit and applied to the output control circuit. Here, it is determined which of the fields read from the video RAM will be displayed. Finally, the sub-channel video component data is selected to be provided as output to the display through the three output multiplexers 315, 317 and 319 of FIG. WSP instead of overlapping PIP small screens using analog switches in composite or Y / C interface
The μP340 digitally performs PIP superposition.

The sub-channel is sampled at 640f _H , while the main channel is sampled at 1024f _H. The sub-channel FIFO 354 (2048 × 8) is
The data is converted from the sub-channel sample frequency to the main channel clock frequency. In the process, the video signal undergoes 8/5 (1024/640) compression.
This is necessary for displaying the sub-channel signal correctly.
Greater than / 3 compression. Therefore, the sub-channel is 4x
In order to properly display the small screen of 3, it must be expanded by the interpolator 359. The interpolator 359 is controlled by the interpolator control circuit 371, and the interpolator control circuit 371
It responds to the WSP μP340. The amount of decompression required by the interpolator is 5/6. The expansion coefficient X is determined as follows.

[Equation 2] Therefore, no matter how the small screen is reduced by the PIP processor, the interpolator 359 is set to perform 5/6 expansion (input 5 samples and output 6 samples) to display the small screen. It can be displayed correctly in a 4x3 format on the display.

The PIP_FSW data is CPIP VRA because the PIP video data is horizontally raster mapped to maintain the correct PIP aspect ratio.
It is not a good enough way to determine which field of M should be displayed. PIP small screens will retain the correct interlace, but in general PIP
The overlay area has the wrong horizontal size. P
The only case where the IP overlay size will be correct is for 5/8 decompression using interpolator 359, which is 16x9.
This results in a small screen. For all other interpolator settings, the overlay box will maintain 16x9, but the inset screen will fluctuate horizontally. PIP_FSW
The signal has no information about the correct horizontal size of the PIP overlay. The video RAM data is read before the PIP circuit finishes the synchronization algorithm. Therefore, the high-speed switch data FSW_DAT embedded in the video RAM data stream VRAM_OUT corresponds to the field format written in the video RAM. Video RAM Video component data (Y, U, V) is compensated for motion disruption and correct interlacing is performed.
FSW_DAT is unchanged.

According to the configuration of the present invention, the PIP overlay box has the correct size because the FSW_DAT information is expanded and interpolated together with the video component data (Y, U, V). The FSW_DAT information has the correct size information for the overlay area but does not indicate which field is the correct field to be displayed.
PIP_FSW and FSW_DAT can be used together to solve the problem of maintaining interlace integrity and correct overlay size. In normal operation, CPIP
Since the chip is used in a 4x3 television receiver,
The position of the field in the video RAM is arbitrary.
Fields may be aligned vertically or horizontally,
It doesn't have to be aligned at all. In order for the widescreen processor and the CPIP chip to be compatible, it is necessary to ensure that the PIP field positions are not stored on the same vertical line. That is, the PIP field will be programmed so that the same vertical address is not used for both upper and lower field formats. From a programming perspective, P
It is convenient to store the IP field in the video RAM 350 in a vertically aligned manner, as shown in FIG.

When the signal PIP_OVL is active, ie high, this signal causes the output control circuit 321 to display the sub-data. A block diagram of a circuit for generating the PIP_OVL signal is shown in FIG. Circuit 680
Includes a JK flip-flop 682 whose Q output is one input of a multiplexer 688. The output of the multiplexer 688 is input to the D-type flip-flop 684, and the Q output of the D-type flip-flop 684 is the other input of the multiplexer 688 and the AND gate 69.
0 is connected to one input. The PIP_FSW signal and the SOL (line start) signal are sent to the J of the flip-flop 682.
And K inputs. Exclusive OR gate 686
Has two fast switch data bits FSW_DAT0
And the FSW_DAT1 signal is provided as an input.

Logical exclusive inputs (1, 0) and (0,
The values of 1) indicate even-numbered and odd-numbered valid fields, respectively. Not logically exclusive (0,0) and (1,
The value of 1) indicates that the video data is not valid. A transition from either (0,1) or (1,0) to either (0,0) or (1,1),
Alternatively, a transition from either (0,0) or (1,1) to either (0,1) or (1,0) indicates a boundary transition that defines a PIP box or PIP overlay. The output of exclusive-OR gate 686 is the second input to AND gate 690. AND gate 690
The third input of the RD_EN_AX signal is the sub-FIF
This is a read enable signal for O354. AND
The output of gate 690 is the PIP_OVL signal. Circuit 680 introduces a delay of one line (field line) period from when PIP_FSW becomes active until the overlay area is actually enabled. This is illustrated by the fact that FIFO 354 also introduces one field line delay into the PIP video data being displayed in the video data path.

Thus, the PIP overlay is one field line slower than when programmed by the PIP circuit, but is completely overlaid on the video data. RD_EN_
As for the AX signal, valid sub FIFO data is FIFO 354.
The PIPs are displayed in a superimposed manner (overlaid) only when they are read from. This is an important point. Because the FIFO data is
This is because the O data may be held. This may cause the PIP overlay logic to determine that the PIP overlay is active outside of valid PIP data. RD_EN_A PIP overlay
Enabling with X ensures that the PIP data is valid. According to the configuration of the present invention, the overlay or box of the small-screen sub-video is in the correct position regardless of how the sub-video is expanded, compressed, or interpolated. And displayed in size. This operation is 4x3, 1
Useful for 6x9, and other formats of small screen video sources.

Chrominance components U_PIP and V_PIP
Is delayed by a circuit 367 for a length of time determined by the content of the interpolation of the luminance component, and the signals U_AUX and V
_AUX is produced as output. The Y, U and V components of each of the main signal and the sub signal are stored in the FIFO 354, 356.
And 358 by controlling the read enable signal, each multiplexer 3 in the output signal path 312.
15, 317 and 319 combined. The multiplexers 315, 317, 319 are responsive to the output multiplexer control circuit 321.

This output multiplexer control circuit 321
Is the clock signal CLK, line start signal SOL, H_COUNT from the in-screen screen processor and WSP μP340.
Signal, vertical blanking reset signal and output of the high speed switch. Multiplexed luminance and chrominance components Y_MX, U_MX and V_MX
Are respective digital / analog converters 360, 36.
2 and 364. As shown in FIG. 4, low-pass filters 361, 363, and 36 are provided in the subsequent stages of the digital-analog converters 360, 362, and 364, respectively.
5 is connected. Picture-in-picture processor 320, various functions of Getoare over 300及 beauty data subsampling circuit W
By SP μP340 that are controlled. W SP μP3
40 is a TV μP connected to this via a serial bus
216. The serial bus can be a four wire bus with lines for data, clock signals, enable signals and reset signals, as shown. W
The SP μP 340 communicates with various circuits in the gate array through the WSP μP decoder 310.

In one case, it is necessary to compress the 4 × 3 NTSC video by a factor of 4/3 to avoid aspect ratio distortion of the display screen. In another case,
The video may be stretched to provide horizontal zooming, which typically also involves vertical zooming. Horizontal zooming operations up to 33% can be achieved by reducing the compression to less than 4/3. The sample interpolator is S
Luminance video bandwidth of up to 5.5MHz in -VHS format, since the time of 1024F _H occupies a large percentage of the Nyquist folding frequency is 8 MHz, is used to recalculate the incoming video to a new pixel positions .

As shown in FIG. 6, the luminance data Y_
The MN recalculates the sample value based on the compression or decompression of the video signal.
4 through the interpolator 337. The function of the switches or route selectors 323 and 331 is to invert the topology of the main signal path 304 with respect to the relative positions of the FIFO 356 and the interpolator 337. That is, these switches are used by the interpolator 3 when needed for compression, for example.
37 precedes the FIFO 356, or the FIFO 356 causes the interpolator 3 to
Choose whether to precede 37. Switch 32
3 and 331 respond to the route control circuit 335, which itself responds to the WSP μP 340. It will be recalled that in the small screen mode, the auxiliary video signal is compressed for storage in the video RAM 350 and for practical purposes only decompression is required. Therefore, switches corresponding to these are not required in the sub signal path.

The main signal path is shown in more detail in FIG. Switch 323 has two multiplexers 325 and 3
27. The switch 331 is embodied by a multiplexer 333. These 3
One multiplexer responds to the route control circuit 335,
The route control circuit 335 itself responds to the WSP μP 340. A horizontal timing / synchronization circuit 339 controls the operation of the latches 347, 351 and the multiplexer 353 and also generates timing signals that control the writing and reading of the FIFO. The clock signal CLK and the line start signal SOL are generated by the clock / synchronization circuit 320. The analog-digital conversion control circuit 369 uses Y_M.
Respond to the most significant bits of N, WSP μP 340, and UV_MN.

The interpolator control circuit 349 provides the clock gating information CG for the intermediate pixel position value (K), the interpolator compensation filter weight (C), and the luminance.
Clock gating information CG for Y and color components
Generates UV. FIFO data decimation so that samples are not written at some clocks to perform compression, or some samples can be read multiple times for decompression.
Alternatively, it is this clock gating information that causes the repetition.

It is possible to implement video compression and decompression using a FIFO. For example, WR_EN_MN_
Data can be written to the FIFO 356 by the Y signal. It is possible to prevent every fourth sample from being written to this FIFO. By this, 4 /
3 compression is performed. It is the function of the interpolator 337 to recalculate the luminance samples written to the FIFO so that the data read from the FIFO is smooth rather than bumpy. Stretching can be done in the exact opposite way of compression. In the case of compression, the write enable signal is provided with clock gating information in the form of an inhibit pulse. For data expansion, clock gating information is applied to the read enable signal. This causes a data interruption when the data is read from the FIFO 356.

In this case, the recalculation of the sampled data so that it is smooth from the uneven state is performed by the interpolator 3 located at the position following the FIFO 356 during this process.
37 functions. In the case of decompression, the data is FIFO3
It must be interrupted when it is being read from 56 and when it is being clocked into the interpolator 337. This is different from the compression case where the data is continuously clocked in the interpolator 337. In both compression and decompression cases, clock gating operations can be easily and synchronously performed. That is, the event occurs based on the rising edge of system clock 1024f _H.

There are numerous advantages to this configuration for luminance interpolation. Clock gating operations, i.e., data decimation and data repetition, can be performed synchronously. Unless a switchable video data topology is used to switch the positions of the interpolator and FIFO, the write or read clock will be double clocked due to the interruption or repetition of the data.
k) It has to be done. The word "double clocked" means that two data points are written to the FIFO in one clock cycle, or 1
This means that two data points must be read from the FIFO during one clock cycle. as a result,
Since the write or read clock frequency must be twice the system clock frequency, it is not possible to operate the circuit configuration in synchronization with the system clock. Moreover, this switchable topology uses one interpolator and one FIFO for both compression and decompression purposes.
I only need it. Without using the video switching arrangement described here, in order to achieve both compression and decompression functions, two
Double clocking can be avoided only with one FIFO. In that case, one FI for expansion
The FO must be placed before the interpolator and one FIFO for compression placed after the interpolator.

The widescreen processor can also control vertical deflection to perform the vertical zoom function. The topology of the widescreen processor is such that the mapping (interpolation) functions of the secondary and main channel horizontal rasters are independent of each other (and manipulates the vertical deflection).
This is done independently of the vertical zoom. For this topology, the main channel in order to retain the main channel zoom correct aspect ratio, it may be extended in the horizontal and vertical directions. However, if the setting of the sub-channel interpolator is not changed, the PIP (small screen) is zoomed vertically but not horizontally. Therefore, the sub-channel interpolator can be made to perform a larger decompression to maintain the correct image aspect ratio of the PIP small screen when vertical decompression is performed.

A good example of this process is when the main channel is displaying 16x9 mailbox material. The main horizontal raster mapping is set to 1: 1 (ie no decompression). The vertical is zoomed 33% (ie stretched by 4/3) to remove the black bars associated with the postal stock. The main channel image aspect ratio is now correct. The normal setting of the sub-channel for 4 × 3 material without vertical zoom is 5/6. Different values of the expansion coefficient X are obtained as follows.

[Equation 3] When the sub-channel interpolator 359 is set to 5/8, the correct small screen image aspect ratio is maintained and the PIP
Things inside are displayed without aspect ratio distortion.

The interpolators for the luminance components of the main and sub-signals can be skew correction filters. For example,
As described therein, a four-point interpolator includes a two-point linear interpolator with associated filters and multipliers cascaded to provide amplitude and phase correction. A total of four adjacent data samples are used to calculate each interpolation point. The input signal is supplied to the two-point linear interpolator. The delay given to the input is proportional to the value of the delay control signal (K). The amplitude and phase error of the delayed signal can be minimized by adding the correction signal obtained by the added cascaded filters and multipliers. This correction signal causes peaking to equalize the frequency response of the two-point linear interpolation filter for all (K) values. This original 4-point interpolator is tuned to be optimal for use with a signal having a fs / 4 passband, with fs as the data sample frequency.

Alternatively, a process called a two-stage interpolation process can be used for both channels according to the configuration shown in the Copending application. The frequency response of the original variable interpolation filter is such a two-stage process,
This can be improved by using a so-called interpolator. The two-stage interpolator is, for example, 2n having a fixed coefficient.
It includes a +4 tap finite impulse response (FIR) filter and a 4-point variable interpolator. The FIR filter output is spatially at an intermediate location between the input pixel samples. FIR
The output of the filter is combined by interleaving with the delayed original data samples to produce an effective 2fs
Create a sample frequency. This is a valid assumption for frequencies in the pass band of FIR filters. As a result, the effective passband of the original 4-point interpolator is significantly increased.

The clock / synchronization circuit 320 is a FIFO 35.
It generates the read, write, and enable signals needed to operate 4, 356 and 358. The FIFOs for the primary and secondary channels are enabled to write data for storage for the portion needed to display after each video line. Data is written from one (but not both) of the main and sub-channels required to combine the data from each source on the same line or lines of display. Sub-channel FI
The FO 354 is written in synchronization with the sub video signal, but is read out in synchronization with the main video signal. The main video signal component is synchronized with the main video signal by the FIFOs 356 and 358.
Read out from the memory in synchronization with the main video. The frequency with which the read function is switched between the main channel and the sub-channel is a function of the particular special effect selected.

The generation of another special effect, such as a truncated juxtaposed screen, is done by manipulating the read and write enable control signals for the line memory FIFO. The process for this display format is shown in FIGS.
In the case of the truncated side-by-side display screen, the sub channel 204
The write enable control signal (WR_EN_AX) for the 8 × 8 FIFO 354 is, as shown in FIG. 7, (1/2) * (4/3) = 0.67 of the display effective line period , that is,
It will be active for 67% of the active time period of the sub- channel (in the case of pre speed up). This is about 33% truncation (about 67%
Is effective screen) and 4/3 compression to sub-channel video
Equivalent to the ratio . In the main video channel shown in the upper part of FIG. 8, a write enable control signal (WR_EN_MN_Y) to 910 × 8 FIFOs 356 and 358.
Is (1/2) * (4/3) of main channel effective line period
= 0.67, ie active for 67%. This corresponds to a truncation of about 33% and a compression ratio of 4/3 applied to the main channel video by a 910 × 8 FIFO.

In each of the FIFOs, video data is buffered so that it can be read at a particular point in time. The effective area of time in which data can be read from each FIFO depends on the selected display format.
In the illustrated side-by-side truncation mode example, the primary channel video is displayed in the left half of the display and the secondary channel video is displayed in the right half of the display. The arbitrary video portion of each waveform is different for the primary and secondary channels, as shown. The main channel 910 × 8 FIFO read enable control signal (RD_EN_MN) is active for 50% of the display effective line period of the display starting at the beginning of the effective video immediately following the video back porch. Sub-channel read enable control signal (RD_E
N_AX) is activated for the remaining 50% of the display valid line period starting at the falling edge of the RD_EN_MN signal and ending at the beginning of the front porch of the main channel video. The write enable control signal is synchronized with each FIFO input data (main or sub),
On the other hand, the read enable control signal is synchronized with the main channel video.

The display format shown in FIG. 1D is 2
This is especially desirable because it allows you to display the screens of almost one field in side-by-side format. This display is particularly effective and suitable for a wide format display ratio display, for example, 16 × 9. Most NTSC signals are represented in 4x3 format, which of course corresponds to 12x9. Two NTSC screens with 4x3 format display ratio, these screens are truncated by 33% or 3
3% stuffed, same aspect ratio distortion introduced, 16
It can be displayed on a display with a × 9 format display ratio. Depending on the user's preference, the ratio of screen truncation to aspect ratio distortion can be set to any point between the limits of 0% and 33%. For example, it is possible to display two juxtaposed screens with 16.7% cut and 16.7% cut.

The horizontal display time required for displaying the display ratio of 16 × 9 format is the same as that for displaying the display ratio of 4 × 3 format. This is because both of them have a regular line length of 63.5 μsec. Therefore, the NTSC video signal must be sped up by 4/3 times to maintain the correct aspect ratio without causing distortion. This 4/3 coefficient is the ratio of the two display formats,

[Equation 4] Calculated as A variable interpolator is used in accordance with aspects of the invention to speed up and slow down the video signal. In the past, FIFOs with different clock frequencies at the input and the output have been used to perform similar functions. For comparison, two NTSC x 3 format display ratio signals are combined into one 4 x 3
If displayed on a format display ratio display, each screen must be distorted, truncated, or a combination of both by 50%. There is no need for a speedup equivalent to that required for widescreen applications.

According to the configuration of the invention disclosed herein, the first
A means for receiving video signals representing the screen and the second screen; a video display means having a wide format display ratio synchronized with the first video signal; and a sub-screen for the video display means .
1 small rather defines in size than the screen (Defin
It is stored and means for processing the second video signal so as e) to the successive lines of video information representative of the sub-screen memory
Means for storing the video information representing the sub screen.
Read from the column and combine it with the video information that represents the first screen
In order to realize multiple horizontal pan positions on the sub screen,
Since the start of reading the video information representing the sub-screen is controlled by the variable delay time with respect to the synchronization component of the screen, the viewer can determine the horizontal position of the PIP by the remote controller. The method and apparatus described below allows smooth horizontal movement of the PIP over the entire range of a 16x9 display.

As described above, the characteristic of this PIP is that C
It can be realized by combining the PIP chip (and its associated VRAM) with a wide screen processor (including a FIFO). In this system, CPIP is the PIP required to display PIP on a 4x3 display.
Performs most of the functions (data sampling, decimation, and VRAM control). A widescreen processor corrects the aspect ratio distortion caused by the widescreen display ratio of widescreen televisions and does the actual overlay.

In addition to the functions described above, it is desirable that the wide screen processor (WSP) be able to perform PIP horizontal pan. This is because it is not possible to have CPIP perform this function with the required pan resolution. FIG. 10 shows a block diagram of the sub data path in the WSP.

The key features of operation in the secondary data path associated with horizontal panning of the PIP are as follows. Sub data is sampled at a frequency of 640 f _H by Cpip. The CPIP data is VRAM_OUT in the block diagram.
The VRAM is read to the circuit point indicated by. CPI
P processes the PIP by filtering and decimating to the correct horizontal and vertical size (as a 4x3 display) before writing the data to VRAM.

The INTERP_AX block 359 performs the necessary horizontal interpolation. CPIP is active when V
A signal called _CGR is generated which allows the RAM to be read. The WSP uses the falling edge of this signal to initialize the counter that controls the writing of the secondary FIFO. When the VRAM is read, the data is again in the secondary FIFO.
Stored in and synchronized with the display. The sub-channel data includes 4-bit latches 352A and 352B and sub-F.
IFO (2048 × 8) 354, timing block 3
Buffered by 69 and sync block 368 and synchronized to the display. The PIP_FSW signal is received from CPIP and output multiplexer control block 3 of FIG.
21. This CPIP_FSW signal is VRA
Encoded control bits from M (FSW_DAT
(1: 0)) to determine when the secondary video should be selected for display. The sub-channel video component is
Three output multiplexers 31 for Y, U and V signals
5, 317 and 319 are selected for display.

The actual memory location in VRAM where the PIP is stored is determined by the CPIP software. The panning algorithm does not depend on the memory location used, but for simplicity of explanation it is assumed that the data is stored in VRAM as shown in FIG. Writing of VRAM is started by the sub video vertical sync signal, but reading of VRAM is performed by the display (or
2 fields of the secondary video are stored in the VRAM to prevent the motion tear from occurring in the secondary video since it is initiated by the main vertical sync signal. By storing both fields of the secondary video it is always possible to read the unwritten field. The interlace relationship is maintained by the synchronization algorithm in CPIP.

The programming of CPIP can be somewhat simplified if the data is stored in VRAM as shown in FIG. As a result, the VRAM containing the PIP information
Will be the first horizontal address read following the falling edge of _CGR. Therefore, deputy F
The IFO is enabled to write immediately after the falling edge of _CGR so that all of the PIP information is written to the sub-FIFO.

The results of these assumptions are shown in FIG. The data representing the PIP is shown stored in the "top" (ie, lowest address) of the FIFO. Strictly this is true only for the first line following the write pointer reset (because the length of the FIFO is not necessarily a multiple of the number of samples written to the FIFO for each line). ), Nevertheless, the figure is useful for understanding the principle.

The reading of the sub-FIFO is synchronous with the display and may or may not be associated with the writing of the sub-FIFO. Read is
It is controlled by a counter that is initialized at the start of the display line period (line start, SOL). The SOL is normally aligned with the starting point of the horizontal sync signal. Since it is assumed that the PIP is stored at the "top" of the FIFO, the sub-F
If the IFO read is delayed from SOL by about 9.4 μs (distance from the sync signal to the end of blanking), P
The IP will appear on the left edge of the display. All that must be done to pan the PIP to the right is to delay the start of reading the sub-FIFO by an additional required amount of pan. To get the pan range across the display
It is necessary to limit the number of points written to the IFO to the number of points actually included in the PIP. That is, for example, PI
If P has a width of 200 samples, then sub-F
Only about 200 samples should be written to the IFO. This is because the number of points written in the FIFO for each line is
This must be equal to the number of points read from the FIFO for each line.

[Brief description of drawings]

FIG. 1 is a diagram useful in explaining various display formats of a wide screen television.

FIG. 2 is a block diagram of a widescreen television adapted to operate at 2f _H horizontal scanning in accordance with various aspects of the present invention.

3 is a block diagram of the widescreen processor shown in FIG. 2. FIG.

4 is a block diagram showing details of the widescreen processor shown in FIG. 3. FIG.

5 is a block diagram of an in-screen screen processor shown in FIG. 4. FIG.

6 is a block diagram of the gate array shown in FIG. 4, showing a main signal path, a sub signal path, and an output signal path.

FIG. 7 is a timing diagram used to describe the generation of the display format shown in FIG. 1 (d) using a fully truncated signal.

FIG. 8 is a timing diagram used to describe the generation of the display format shown in FIG. 1 (d) using a fully truncated signal.

9 is a block diagram showing the main signal path of FIG. 6 in more detail.

10 is a block diagram showing the sub-signal path of FIG. 6 in more detail.

11 is a timing chart of the screen processor in the screen of FIG.
It is a block diagram of a control unit.

FIG. 12 is a block diagram of a circuit that generates an internal 2f _H signal in the 1f _H -2f _H conversion.

13 is a combination block and circuit diagram for the deflection circuit shown in FIG.

FIG. 14 is a block of the RGB interface shown in FIG.

FIG. 15: Video RAM attached to the in-screen screen processor
6 is a diagram for explaining memory mapping in FIG.

FIG. 16 is a block diagram of a circuit for controlling output switching between main and sub video signals.

FIG. 17 is a diagram useful in explaining the operation of the video RAM during horizontal PIP panning.

FIG. 18 is a diagram useful for explaining the operation of the sub-FIFO during horizontal PIP pan.

[Explanation of symbols]

224 video display means 301 Means for processing secondary video signal 354 Means for storing video information representing a sub-screen 300 Means of combining video information 339 Means for generating a variable time delay 320 screen processor 350 video RAM

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tamothy William Sager               United States of America               46260 Indianapolis Nashiyu               A drive 8318 (72) Inventor Nataniel Hulk Asoz               United States of America               46112 Brownsburg East               State Road 136 6565                (56) References JP-A-63-290079 (JP, A)                 JP 63-169186 (JP, A)                 Japanese Patent Laid-Open No. 2-50681 (JP, A)                 JP-A-6-90414 (JP, A)                 JP-A-4-313984 (JP, A)                 JP-A-50-68411 (JP, A)                 International publication 91/19378 (WO, A1)                 International publication 91/19379 (WO, A1)

Claims (2)

(57) [Claims] 1. Means for receiving first and second video signals respectively representing first and second screens; and video display means having a wide format display ratio and synchronized with said first video signals. Means for generating a continuous line of video information representative of the first screen without substantially distorting the aspect ratio of the image; processing the second video signal to display a sub-screen at the video display; Means and a means that is smaller in size than the first screen and substantially without distortion of the aspect ratio of the image; and a continuous line of video information representing the subscreen and the subscreen.
The edge around which the surface is overlaid on the first screen
Means for storing a peripheral definition information for constant; variable time delay from the synchronization component of said first video signal; the first screen and the sub screen and means to combine seen <br/> the video information representing the means and for generating a; after the variable time delay, from said storage means to said set look if <br/> Align unit, the line up for video information representing said sub-screen
And a means for sequentially starting the transfer of the margin defining information of the sub-screen, and the combining means receives the margin defining information.
Overlay the sub screen on top of the first screen.
And the variable time delay defines a smooth horizontal movement of the sub-screen across the video display means. 2. Means for receiving first and second video signals respectively representing first and second screens; and video display means having a wide format display ratio and synchronized with said first video signal. ; continuous means for generating a line was of video information representative of said first screen; be those to respond kinematic to the second video signal, defining a sub-screen of smaller size than said video display means, the video An in-screen screen (RAM) having an address means for writing video data to the video RAM and reading video data from the video RAM and defining an operation of a display range horizontally smaller than the video display ( A picture-in-picture processor; a continuous line of video information representing the sub-screen read from the video RAM and the sub-screen being the first line. screen
A first-in first-out multi-line memory for storing perimeter defining information defining a perimeter when overlaid with a line; and the line of video information representing the sub-screen from the line memory and the sub-screen according to a variable time delay. Marginal rule
Means for sequentially reading constant information ; the video information read from the line memory
Means for combining with the video information representing the screen of, and the combining means for combining the peripheral definition information.
Then, overlay the sub screen on top of the first screen.
Controlled to be read from the line memory in accordance with the variable time delay, when combined with the first screen, to define a smooth horizontal movement of the sub-picture throughout the above video display means Horizontal pan system featuring.