JPS61194981A - Television receiver with two picture planes - Google Patents

Abstract

PURPOSE:To enable a small screen to appear in any desired part of the screen on display with no adjustment required by controlling the small screen based on output signals from two PLL circuits and two flip-flop circuits of the D type. CONSTITUTION:Horizontal oscillation output Hc and vertical synchronization signal Vc delivered from the small screen synchronization separating section 19 are input in the lock signal generator section 60 for the small screen line to provide horizontal synchronization signals HC.CLK and vertical synchronization signals VC.LK which are synchronized with each other so that no adjustment is required. Both synchronization signals HC.LK and VC.LK are input in the small screen control section 33 where they are used as the timing signal for writing the small screen in the memory 34. The horizontal oscillation signal Hp and vertical oscillation signal Vp from the main screen synchronization separating section are input in the lock signal generator section 25 for the main screen line, where the said horizontal oscillation output HP.CLK and vertical synchronization signal VP.CLK for the small screen are generated to be used in the small screen control section 33 as the signal for reading memory 34.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for transmitting two video signals into one cathode ray tube (CR, T).
This invention relates to a two-screen television receiver capable of displaying images on the screen.

2. Description of the Related Art In general, the horizontal and vertical synchronizing signal generation circuits of a two-screen television receiver are composed of gate oscillation circuits (44
), (49). FIG. 3 shows the configuration of a conventional two-screen television receiver. The RF multiplied signal input from the antenna (+) is converted to an intermediate frequency by the tuner (2), and the output signal input to the video intermediate frequency amplification section (3) is converted to R, It is converted into the three primary colors of G and B, outputted to the video output section (6) via the signal switching circuit (5), and displayed as parent video information by CR'r (7). In addition, the output of the tuner (2) is connected to the hydrophilic early oscillation output HP and the parent vertical synchronization output VP through the coarse synchronization separation section (8).
1. This is input to the child screen control section (12). On the other hand, the video signal of the sub-screen is input from the video input terminal (9) and passed through the sub-demodulator (10).
-Y), is converted into a Y signal and input to the child screen control unit (12), and the signal of the video input terminal (9) is transmitted to the child horizontal oscillation output Hc and the child vertical Synchronous output Vc is obtained, which is also the sub-screen I11 control (12
) is entered. This child screen information is (RY), (
B-Y), Y signals are stored in the memory (13) by the sub-screen control unit (12), converted into three primary color signals R, G-B, and switched by the switching signal Ys multiplied signal signal switching circuit (5). The information is then displayed on the CRT (7) via the video output (6) as sub-screen information as shown in (16) in FIG.

(15) is the main screen.

In the conventional example shown in FIG. 2, the child video input terminal (9) is (39
), the child demodulation section (10) is (40), and the child synchronization separation section (11) is (41). Here, the child's horizontal oscillation output H
c is input to the monostable multivibrator (42) for positioning writing to the memory (59), and its output is input to the gate oscillation circuit (44), which generates the child horizontal oscillation signal Hc-(1!) for controlling the child screen. Child screen control unit (54) as LIm
is input. On the other hand, the hydrophilic early oscillation output HP is at the input terminal (
46) and via a monostable multivibrator (47) for read positioning from the memory (59).

The rough horizontal oscillation signals HP and aL for controlling the small screen are applied to the small screen control section (54) via the gate oscillation circuit (49). Further, the parent vertical synchronizing signal VP is inputted from the input terminal (51), and is inputted to the VP via the monostable multivibrator (52) for reading vertical positioning from the memory (59).
, (:L[) and enters the child screen control unit (54).

The (RY), (B-Y), and Y color difference signals of the slave demodulator (40) are also input to the slave screen controller (54). The sub-screen information controlled by the sub-screen control unit is converted into primary colors R, G, and B and sent to the third output terminals (55), (56, and 57).
It is input to the signal switching circuit (5) in the figure, and
) is switched by the switching signal Ys from the output terminal (58).

Problems to be Solved by the Invention However, as is clear from the explanation of the conventional example, memory (5
Monostable multivibrators (42) (47) (52) are used for write positioning and read positioning to 9), and variable resistors (43) (48) (52) for adjustment are used.
3) is required, and gate oscillation circuits (44) and (49) are used as write/read clock generators.
This also requires adjustment with variable resistors (45) (50).

SUMMARY OF THE INVENTION An object of the present invention is to provide a two-screen television receiver capable of obtaining a sub-screen without any adjustment of horizontal and vertical signals for memory writing and reading by a sub-screen control unit.

Means for Solving the Problems The two-screen television receiver of the present invention writes child screen information to a memory write position based on a horizontal synchronization signal Hc and a vertical synchronization signal Vc, which are synchronously separated from a video signal for a child screen, and The sub-screen information is read out from the memory based on the horizontal synchronization signal I (P and vertical synchronization signal Vp synchronously separated from the screen video signal) and the sub-screen information is displayed at a predetermined location in the main screen, and the horizontal A first PLL circuit receives a synchronizing signal Hc as an input and outputs a first signal IC0 (!L) whose frequency is n times (n is an integer), and a first PLL circuit receives the vertical synchronizing signal Vc as a data input. Signal H (!, C!
a first D-type flip-flop clocked by L[;
a second P which receives the horizontal synchronizing signal HP as an input and obtains a second signal HP-CLK whose frequency is m times (m is an integer);
An LL circuit, a second D-type flip-flop whose data input is the vertical synchronization signal Vp, a second signal HP, and eLIC are provided, and the write position to the memory is set to the first signals Ha, cLc. The third signal vc, ci, c of the output of the first D-type flip-flop determines the reading position from the memory, and the second signal Hp-aLK determines the reading position from the memory.
and the fourth signal vp of the output of the second D-type flip-flop.
, aLt. With this configuration, the output signal is determined based on the output signals of the first and second PLL circuits and the output signals of the first and second D-type flip-flops. Since the screen is controlled, there is no need to adjust the parts as in the conventional case, and the child screen can be displayed at a predetermined position on the main screen without any adjustment.

Example An embodiment of the present invention will be described below with reference to FIG.

In Figure 1, (17), (18), and (19) are the video input terminal of the child screen, child demodulation section, and child synchronization separation section, respectively, and these correspond to (9), (10), and (11) in Fig. 3. .

The horizontal oscillation output Hc and vertical synchronization signal Vc obtained from the synchronization separation section (19) are sent to the child line lock signal generation section (60).
is input. Horizontal oscillation output Hc is a phase comparator (21)
This output is applied to one input of the voltage control oscillation circuit (23) via a low-pass filter (22), and an analog signal is input as a control signal. Voltage controlled oscillation circuit (23
) has a horizontal oscillation frequency of 15°75KHz.
If the frequency is doubled, for example 468 times, it will be 7°361Ml.
1z, and this output HC,c, , is divided by 1/n, here (1/468), by the frequency dividing circuit (24), and is then used as the other input signal of the phase comparator (21). . That is, the horizontal synchronization signals Hc and ctsc for child screen control are n synchronized with the horizontal oscillation output Hc of the child synchronization separation section (19).
A stable output is always obtained as a double signal. Further, the vertical synchronization output Vc of the child synchronization separation section (19) is applied to the data input of the D-type flip-flop (60), and the horizontal synchronization signal Hc, cL output from the voltage controlled oscillation circuit (23) is applied to the D-type flip-flop (60).
As a clock for the D-type flip-flop (60), a vertical synchronization signal va-etc for child screen control is obtained at the output of the D-type flip-flop (60).

In this way, the vertical synchronization signal VC0cLK for child screen control is synchronized with the horizontal synchronization signals Ha, ci, and K for child screen control, and does not require any adjustment. These two synchronization signals ■c, c
LK, Ha, and aLtc are applied to the small screen control section (33) and are used as timing signals for writing the small screen into the memory (34).

In addition, (31) and (32) in FIG. 1 are input terminals to which the horizontal oscillation output Hp and vertical oscillation output Vp of the coarse synchronization separator (8) are input, respectively, and the signals Hp of the input terminals (31) and (32) are respectively input. , VP are applied to the parent line lock signal generator (25). In other words, the parent horizontal oscillation output Hρ is the input terminal (3
1) to one input of the phase comparator (26).

This output is applied to a voltage controlled oscillation circuit (2g) (having an oscillation frequency m times HP) via a low-pass filter (27), and the output HP, (!LIE) is a (1/m) frequency dividing circuit ( 29) to the other input of the 1-phase comparator (26) to form a closed loop.Also, the main screen synchronization signal Vp is applied to the D-type flip-flop (30) via the input terminal (32), Horizontal oscillation output HP for child screen control.

Vertical synchronization signal VP for small screen control using CLK as a clock
, CL, and K are obtained. HP obtained in this way - (!LI
E, VP, (!LK are used by the small screen control unit (33) as signals for reading the memory (34).

The video signal of the sub-screen input from the video input terminal (17) is transmitted via the sub-demodulator (18) to R-Y), (B-Y).
), is converted into a Y color difference signal, is applied to the sub-screen control unit (33), and is stored in the memory (34) as video information. The child screen information controlled by the child screen control unit (33) is converted into primary color R, G, and B signals, and the output terminal (35) (3
6) Signal switching circuit (5) shown in Figure 3 via (37)
The main screen is switched with the switching signal Ys from the output terminal (38), and displayed on the CRT (7) as a child screen (16) as shown in FIG.

In addition, in FIG. 1, the child line lock signal generation section (6
phase comparator (21) and low-pass filter (
22), a voltage controlled oscillation circuit (23), and an l/n frequency dividing circuit (24) is the first PLL circuit in the claims, and the parent line lock signal generating section (25)
), the D-type flip-flop (3
0) is the second PLL circuit.

As described in the detailed description of the invention, the two-screen television receiver of the present invention has the following features:
Horizontal synchronization signal Hc synchronously separated from the video signal for the sub-screen
a first PLL circuit which takes as an input a first signal Hc, cL whose frequency is n times higher (n is an integer) as an output, and a vertical synchronization signal Vc synchronously separated from the video signal for the small screen as a data input. A first D-type flip-flop clocked by the first signal Ha-cLK, and a second flip-flop whose frequency is m times (m is an integer) whose input is the horizontal synchronizing signal Hp synchronously separated from the main screen video signal. a second PLL circuit that obtains signals HP and cLK, and a second D-type flip-flop whose data input is a vertical synchronization signal VP synchronously separated from the main screen video signal and whose clock is a second signal HP-CL. A write position in the child screen information memory is determined by the first signal Hc-cLK and a third signal Vc-cL+c of the output of the first D-type flip-flop, and a read position from the memory is determined. to the second signal Hp-aI- and the fourth signal vP of the output of the second D-type flip-flop.
, cLK, it is possible to obtain the horizontal and vertical synchronization signals of the child screen and the main screen without any adjustment, making it extremely effective for streamlining factory production lines and reducing production costs. be.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a sub-screen control system according to an embodiment of the present invention, Fig. 2 is a block diagram of a sub-screen control system of a conventional two-screen television receiver, and Fig. 3 is a block diagram of a sub-screen control system of a conventional two-screen television receiver. FIG. 4 is an explanatory diagram of the display screen of the two-screen television receiver. (15)...Main screen, (16)...Sub screen, (1
8)...prognosis control unit, (19)...child synchronization separation unit, (
20) (30)...D type flip-flop, (21
)(26)...Phase comparator, (22)(27)...
・Low pass filter, (23) (2g)...Voltage controlled oscillation circuit, (24)...1/n frequency dividing circuit, (25)
...Parent line lock signal generation section, (29)...1/
m frequency dividing circuit, (33)...Small screen control section, (34)
...Memory, (60)...Child line lock signal generation section agent Yoshihiro Morimoto Figure 1 6θ-J Line mouth, 4th verse f'f92θ, 30-v
彎lfrideff. Tsufu - Figure 2 Figure 3

Claims (1)

[Claims] 1. A horizontal synchronizing signal Hc synchronously separated from a video signal for a child screen, writing child screen information to a memory write position based on a vertical synchronizing signal Vc, and a horizontal synchronizing signal synchronously separating from a video signal for a main screen. Hp, the sub-screen information is read from the memory based on the vertical synchronization signal Vp, and the sub-screen is displayed at a predetermined location in the main screen, and the horizontal synchronization signal Hc is input and the frequency is n times the output. a first PLL circuit that obtains a first signal H_C_·_C_L_K where n is an integer]; a first D-type flip-flop whose data input is the vertical synchronization signal Vc and which uses the first signal H_C_·_C_L_K as a clock; a second PLL circuit that receives the horizontal synchronization signal Hp as an input and outputs a second signal H_P_·_C_L_K with a frequency multiplied by m (m is an integer);
The vertical synchronization signal Vp is used as a data input and a second signal H_
A second D-type flip-flop clocked by P_・_C_L_K is provided, and the writing position to the memory is determined by the first signal H_C_・_C_L_K and the third signal V_C_・_C_L_K of the output of the first D-type flip-flop. and the reading position from the memory is determined by the second signal H_P_·_C_L_K and the fourth signal V_P_·_C_L_K output from the second D-type flip-flop. Machine.