JPS6064391A - Synchronous connector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Subject of invention) The present invention relates to a synchronous coupling device.

(Object of the Invention) The present invention aims at synchronously combining video signals having the same number of scanning lines in the vertical and horizontal directions in order to generate a superimposed (superposition with IN priority order) signal. The purpose of the present invention is to provide a synchronous coupling device capable of

(Contents of conventional examples and their problems) With the progress of electronic technology in recent years, the prices of LSIs, ICs, etc. have been decreasing. For this reason, computers that used to be mainly used for business purposes are now becoming popular as personal computers.
It often outputs text (text, pictures, etc.). Therefore, by superimposing an image of a personal computer and another video source with a set priority, so-called superimposing, the scope of use of the personal computer can be expanded. In order to do this, as shown in FIG. A video disc, a personal computer, etc.) is similarly supplied to the superimpose signal synthesis circuit 2, and the superimposition signal synthesis circuit 2 superimposes the supplied signal, and the superimposition signal is received by the television. By supplying the image to the lff 14, it is possible to display an image obtained by superimposing an image from a personal computer and an image from a video source.

However, for example, when superimposing a television video signal that is another video source and a personal computer video signal, the number of scanning lines is different between the television video signal and the personal computer video signal. However, if E is simply mixed, synchronous combination in the vertical and horizontal directions cannot be achieved, resulting in an image in which it is unclear what is being displayed.

In order to produce a clear superimposed image, it is necessary to synchronize the video signals to be superimposed in the horizontal and vertical directions using a synchronization combining device or the like. However, because conventional devices for combining synchronization are expensive and have complicated circuit configurations, most of them are used for business purposes, and many are unsuitable for consumer use. There was a problem.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a video signal output from an external video signal generator and an output from a non-increment video signal generator having a clock input terminal. and a non-interlaced video signal having the same number of scanning lines as a video signal outputted from the external video signal generator in the vertical and horizontal directions, the synchronous combining device comprising: A horizontal synchronizing signal HN of a non-interlaced video signal output from a generator and a horizontal synchronizing signal HE of a video signal output from the external video signal generator are supplied, and the phase difference between the horizontal synchronizing signal HN and the horizontal synchronizing signal HE is a phase difference detection circuit that generates a phase error voltage converted into a voltage form; a voltage controlled oscillator that outputs a clock signal with a frequency corresponding to the phase error voltage output from the phase difference detection circuit; A clock signal supplied from the voltage controlled oscillator is supplied to the clock input terminal of the non-interlaced video signal generator, and in a phase modulating state in which a phase modulating signal is supplied to the phase modulating signal input terminal, the clock signal supplied from the voltage controlled oscillator is supplied to the clock input terminal of the non-interlaced video signal generator. a phase adjustment circuit that selects and switches to supply a clock signal with a frequency of the non-interlace video signal generator to the clock input terminal of the non-interlace video signal generator; A vertical synchronization signal VN of an interlaced video signal and a vertical synchronization signal VE of a video signal output from the external video signal generator.
is supplied, and when the vertical synchronization signal @VE arrives, the vertical synchronization signal V
A state in which V is present is determined to be a locked state, and a lock signal is output, and a state in which the vertical synchronizing signal VN is not present when the vertical synchronizing signal VE arrives is determined to be an unlocked state, and an unlock signal is output, and the unlocked state is determined. Unless the start of the vertical synchronizing signal VN is within the period of the vertical synchronizing signal VE when determining the unlock state, the time width from the arrival of the vertical synchronizing signal VN to the arrival of the vertical synchronizing signal VE immediately after determining the unlocked state is adjusted. a lock detection circuit that supplies a phase signal to a phase adjustment signal input terminal of the phase adjustment circuit; and a non-interlace signal that is output from the non-interlace video signal generator during a period when the lock detection circuit is determining the lock state. The first field and the second field of the video signal are discriminated, and at the beginning of one field, [n
-1] A phase modulation signal of the horizontal scanning period is supplied to the phase modulation signal input terminal of the phase modulation circuit, and [ n] A scanning line number matching circuit that supplies a phase adjustment signal during a horizontal scanning period to a phase adjustment signal input terminal of the phase adjustment circuit.

(Example of the invention) FIG. 2 shows an embodiment 7 of the synchronous coupling device according to the present invention. FIG.

In FIG. 2, 5 is a non-interlaced video signal generator (hereinafter referred to as NG), 6 is a synchronization signal separation circuit, 7 is a phase difference detection circuit, and 8 is an external video signal generator (hereinafter referred to as E).
9 is a synchronizing signal separation circuit, 10 is a voltage controlled oscillator (hereinafter referred to as VCO), 11 is a phase adjustment circuit, 12 is a lock detection circuit, 13 is a lock/unlock signal output terminal, and 14 is a scanning circuit. The line number matching circuit 15 is an OR circuit.

NG5 has a clock input terminal, divides the clock signal supplied from the clock input terminal to generate a horizontal synchronous scanning frequency, divides the horizontal scanning frequency to generate a vertical scanning frequency, and divides the clock signal supplied from the clock input terminal to generate a vertical scanning frequency. The NG5 reads data stored in digital memory, etc. according to the frequency and vertical scanning frequency and outputs a non-interlaced video signal.
It is one of the components of a so-called personal computer, consisting of memory, input/output interface circuits, etc., and is inserted between the CPU and a display device such as a rafter display or graphic display. , CPIJ, and outputs non-interlaced video signals to display devices such as character displays and graphic displays.

The luminance signal component of the non-interlaced video signal output from the NG 5 is supplied to the synchronization signal separation circuit 6. The synchronization signal separation circuit 6 extracts the horizontal synchronization signal HN from the input luminance signal component.
and vertical synchronization signal VN are separated and output. The horizontal synchronization signal 1-IN separated by the synchronization signal separation circuit 6 is supplied to one input terminal of the phase difference detection circuit 7.

The luminance signal component of the video signal output from the EG 8 is supplied to the synchronization signal separation circuit 9. A synchronization signal separation circuit 9 extracts a horizontal synchronization signal HE and a vertical synchronization signal V from the input luminance signal component.
Separate and output E. The horizontal synchronization signal 1''E separated by the synchronization signal separation circuit 6 is supplied to the other input terminal of the phase difference detection circuit 7.

The phase difference detection circuit 7 outputs a phase error voltage obtained by converting the phase difference between the horizontal synchronizing signals HN and HE into a voltage form, and this phase error voltage is supplied to the control voltage input terminal of the v co io. VCO10 outputs an output signal that is a clock signal of a frequency corresponding to the voltage value input to the control voltage input terminal, and the output signal of VCOlo is output to phase modulator circuit 1.
1, and the output signal of the phase adjusting circuit 11 is supplied to the clock input terminal of NG5.

The phase adjusting circuit 11 receives the output signal of VCOlo and the output signal of VCO10.
Output] The signal with the frequency of the signal and the phase modifier circuit 11
The selection is switched by the phase adjustment signal supplied to the phase adjustment signal input terminal of NG5, and the selected signal is outputted to the clock input terminal of NG5. In other words, the phase modulation circuit 11 outputs the output signal of v c o io to the clock input terminal of NG5 in the normal state (state where the phase modulation signal is not supplied), and the phase modulation circuit 11 outputs the output signal of v c o io to the clock input terminal of NG5, and the phase modulation circuit 11 outputs the output signal of v c o io to the clock input terminal of NG5, and the phase modulation circuit 11 is in the phase modulation state (state where the phase modulation signal is supplied). , V CO1
A signal obtained by increasing the frequency of the output signal of 0 is output to the clock input terminal of NG5. Therefore, when the phase adjustment circuit 11 enters the phase adjustment state, the clock frequency supplied to the clock input terminal of NG5 becomes -IN, so the period of the horizontal synchronization signal )-IN outputted from NG5 becomes twice.

Note that the above-described NG5, synchronization signal separation circuit 6, phase difference detection circuit 7, VCOlo, and fill phase circuit 11 form a phase-locked loop. Therefore, in the normal state described above, the horizontal synchronizing signals 1-IN and I-IE have the same frequency and the same phase. In other words, the non-interlaced video signal output from NG5 and the video signal output from EG8 are locked in the horizontal direction, making it possible to synchronously combine them in the horizontal direction.

Vertical synchronization signals VN and VE output from the synchronization signal separation circuit 6 and the synchronization signal separation circuit 97'+1 are supplied to the lock detection circuit 12.

The lock detection circuit 12 compares the phase of the vertical synchronizing signal VN output from the synchronizing signal separating circuit 6 with the vertical synchronizing signal VE output from the synchronizing signal separating circuit 9,
It is determined whether the non-interlaced video signal generated by G5 and the video signal generated by EG8 are in a locked state or an unlocked state in the vertical direction.

When a locked state is detected, a lock signal is output from the lock/unlock signal output terminal 13, and a signal for activating the scanning line number matching circuit 14 is output.

When an unlocked state is detected, an unlock signal is output from the lock/unlock signal output terminal 13, and a signal that does not operate the scanning line number matching circuit 14 is output. Further, a phase adjustment signal is supplied to the phase adjustment circuit 11 via the OR circuit 15 in order to shift the unlocked state to the locked state.

Note that by using the lock signal/unlock signal described above, for example, by muting the superimpose signal when the unlock signal is output, it is possible to remove image disturbances that occur in the unlocked state. can.

The video signal output by EG8 (for example, the number of scanning lines is 52
5 lines), the number of scanning lines of the non-increment video signal (for example, 524 scanning lines) output by NG5 is less by [2n-1] lines (for example, 1 line) per 2 fields. 12- By the phase-locked loop described above, NG5 and EG
Horizontal synchronization signal HN with 8,! : Even if synchronization with HE is achieved to achieve horizontal synchronization, the synchronization of vertical synchronization signals VN and VE does not match (the period of vertical synchronization signal VN is shorter than that of vertical synchronization signal VE). In order to achieve synchronized coupling in the vertical direction, it is necessary to synchronize the vertical synchronizing signals VN and VE by some method. The scanning line number matching circuit 14 is a circuit that operates to synchronize the vertical synchronizing signals VN and VE when the lock detection circuit 12 detects a locked state.

The scanning line number matching circuit 14 uses the frequency of the vertical synchronizing signal VN to identify the first field and the second field (even field, odd field), and uses this frequency divided signal to distinguish between the first field and the second field (even field, odd field). A delayed signal of [nl horizontal scanning periods (hereinafter referred to as H) is output, and a delayed signal of [n-1]H is output at the beginning of the other field. These delayed signals are supplied to the OR circuit 15 as phase adjustment signals. Therefore, when the lock detection circuit 12 detects a locked state, the phase modulating circuit 11 enters the phase modulating state for a period of [n]t1 (period for n scanning lines) in one field, and Then, the phase modulating circuit 11 is in the phase modulating state for a period of [n-1] 1-1 (a period corresponding to [n-1] scanning lines).

In other words, since the number of scanning lines of the NG5 non-interlaced video signal is [2n-1] fewer per two fields than the number of scanning lines of the EG8 video signal, the number of scanning lines of the NG5 non-interlaced video signal is [2n-1] fewer in one field. n], and by correcting the time for [n-1] scanning lines in the other field, it is possible to correct the time for [2n-1] scanning lines per 2 fields. , synchronous coupling can be realized in the vertical direction.

The lock detection circuit 1 will be described below with reference to FIGS. 3 and 4.
Let me explain 2. FIG. 3 is a circuit diagram for explaining the lock detection circuit 12 and the scanning line number matching circuit 14, and FIG.
>(B) and (C) are diagrams for explaining the operation of the lock detection circuit 12 when transitioning from the unlocked state to the locked state.

In FIG. 3, the same components as in FIG. 2 are given the same reference numerals and their explanations will be omitted.

16 is a vertical synchronizing signal input terminal, 17 is a D-type flip-flop circuit (hereinafter simply referred to as DFF), 18 is a vertical synchronizing signal input terminal, 19 is a NOR circuit, 20 is a DFF, 21
is an output terminal, 22 is a DFF, 23 is a shift (~register,
24 is a shift register, 25 is an inverter, 26 is an AN
D circuit, 27 is an inverter, 28 is an AND circuit, 29 is an output terminal, and 30 is an output terminal.

A vertical synchronizing signal VN as shown in FIG. , this vertical synchronization signal VN is D
It is input to the D terminal of FF17.

Further, a vertical synchronization signal VE as shown in FIG. 4(B) separated by the synchronization signal separation circuit 9 is inputted to the vertical synchronization signal input terminal 18 from the luminance signal component of the video signal output from the EG8. This vertical synchronizing signal VE is applied to the OK (clock) terminal of the DFF 17.

In other words, the signal obtained by sampling the vertical synchronization signal 'rVx at the beginning (rising edge) of the vertical synchronization signal VE is the DFF.
It is output from the Q terminal of 17. The signal output from the Q terminal of the DFF 17 and the vertical synchronization signal VE are connected to the NOR circuit 19.
supplied to Therefore, from the NOR circuit 19, the beginning (rising edge) of the vertical synchronizing signal VE is the vertical synchronizing signal V.
When the state is within the period of N (locked state), an L level signal is output, and when the start (rising edge) of the vertical synchronizing signal VE is outside the period of the vertical synchronizing signal VN (a<unlocked state), a signal of L level is output. In this case, an L level signal is output only during the period of the vertical synchronizing signal VE.

The output signal of the NOR circuit 19 mentioned above is the CL of the DFF 20.
It is supplied to the R (clear) terminal. Also, DFF20
(7) D terminal niha power supply fH pressure V c c , CK (
A vertical synchronizing signal VNz is supplied to the clock terminal. Therefore, the Q terminal of the DFF 20 outputs a signal as shown in FIG. 4(C). That is, in the locked state, the DFF 20 is preset and the output of the terminal Q is always at L level. In the unlocked state, the vertical synchronizing signal V
Until the arrival of E, the vertical synchronization signal error time [VN
-VE] outputs an H level signal.

The Q terminal of the DFF 20 is connected to the lock/unlock signal output terminal 13 and also to the output terminal 21.

The output terminal 21 is connected to the OR circuit 15 shown in FIG.

Therefore, in the unlocked state, while the signal shown in FIG. 4(C) is output, the vertical synchronizing signal y difference time [VN - V
E], the phase adjustment circuit 11 enters the phase adjustment state. In other words, N
G5 clock frequency is vertical synchronization signal error time [VN
-VE], the next vertical synchronization signal error time [VN -VE] is reduced to -VE]. By continuing such operations, a lock state is finally reached, and the phase adjustment circuit 11 ceases to operate.

In addition, the above-mentioned DFF17, NOR circuit 19, DFF20
are elements constituting the lock detection circuit 12.

The vertical synchronization signal VN is input to the vertical synchronization signal input terminal 16 to the OK (clock) terminal of the DFF 22, and the PR(
The output signal of the Q terminal of DF17 is input to the preset) terminal. Therefore, when the DFF1 is in the unlocked state,
The output of the Q terminal of No. 7 is at L level, and the DFF 22 is preset and therefore does not operate.

Furthermore, in the locked state, the output of the QGm element of the DFF 17 is at H level, and the DFF 22 is not preset, so the operation described below is performed.

The terminal of DFF22 is connected to the D terminal. In other words,
DFF22 sets the frequency of the input vertical synchronization signal VN to 4.
By setting -, the first field and the second field are detected. The Q terminal of the DFF 22 supplies the serial input terminal S1 of the shift register 23 with a signal based on the frequency of the vertical synchronization signal VN, and the 0 terminal of the DFF 22 supplies a vertical synchronization signal to the serial input terminal Si of the shift register 24. Since a signal based on the frequency of @V ry is supplied, the shift register 23 operates at the beginning of one field, and the shift register 24 operates at the beginning of the other field.

Shift 1 - Terminal Q1 which is the first stage output terminal of register 23
The AND circuit 26 calculates the product of the output of the terminal Q old which is the output terminal of the [n-1]th stage and the output obtained by inverting the output of the terminal Q old which is the output terminal of the [n-1]th stage.
outputs a delayed signal.

The AND circuit 28 multiplies the output of the terminal Q1, which is the first stage output terminal of the shift register 24, and the output of the terminal Qn, which is the output terminal of the [n]th stage, inverted by the inverter 27. The circuit 28 outputs a delayed signal of [n]H.

Therefore, in one field, a delayed signal of [n]l-1 time is output from the output terminal 30 of the AND circuit 28, and in the other field, a delayed signal of [n-1]H time is outputted from the AND circuit 26. Output from terminal 29. These delayed signals, which are phase modulation signals, are supplied to an OR circuit 15.

Therefore, when the lock detection circuit 12 detects a lock state, the phase adjusting circuit 12 waits for a period of [n]H (for n scanning lines) at the beginning 19 of one field.
1 is in the phase adjustment state, and in the first part of the other field, the phase adjustment circuit 11 is in the phase adjustment state for a period of [n-1]H (scanning line [n-1]).

In other words, the number of scanning lines of the NG5 non-interlaced video signal is [2n-1] fewer per two fields than the number of scanning lines of the EG8 video signal, so the number of scanning lines of the NG5 non-interlaced video signal is [n-1] fewer in one field. ] By correcting the time for [n-1] scanning lines in the other field, it is possible to correct the time for [2n-1] scanning lines per two fields. Therefore,
Synchronous coupling can be realized in the vertical direction. In other words, in the locked state, the lock detection circuit 12 does not output a phase adjustment signal, and the scanning line number matching circuit 14 operates to output a phase adjustment signal, and in the unlocked state, the lock detection circuit 12 is in the locked state. In order to shift to , a phase adjustment signal is output, and the scanning line number matching circuit 14 is not operated.

In addition, the above-mentioned DFF 22, shift 1 to register 23°2
0-24, inverters 25.27, and AND circuits 26.28 are elements constituting the scanning line number matching circuit 14.

Further, for example, when the number of scanning lines of NG5 is 524 and the number of scanning lines of EG8 is 525, the difference in the number of scanning lines is as described above.
2n-1] When applied to the general form of a book, [n] is 1.
In this case, the shift register 2 shown in FIG.
3. Consists of an inverter 25 and an AND circuit 26 [
The [n-1]H delay circuit is not required, and the number of scanning lines can be matched only with the [n]H delay circuit.

Further, the above-mentioned synchronous coupling device has the same configuration and can be applied not only when the difference in the number of scanning lines is [2n-1] but also when the number of scanning lines is the same as shown below. In the case of signals with the same number of scanning lines as shown below (for example, NG
When the number of scanning lines of the non-increment video signal outputted from EG 5 and the number of scanning lines of the video signal outputted from EG 8 are both 524, the lock detection circuit 12 and the number of scanning lines matching circuit 14 are Since the operation is different from that described above, the two circuits, the lock detection circuit 12 and the scanning line number matching circuit 14, will be explained with reference to FIGS. 4 and 5. FIGS. 5A>(B) and 5C are diagrams for explaining the operation of the lock detection circuit 12 in a locked state between signals having the same number of scanning lines.

First, the operation upon transition from the unlocked state to the locked state is the same as that when the difference in the number of scanning lines is [2n-1], so a description thereof will be omitted.

However, since the operation after entering the locked state is different from that when the difference in the number of scanning lines is [2n-1], this will be explained below. When the lock state is reached, the scanning line number matching circuit 14 starts operating, so as shown in FIGS.
The period of the vertical dosing signal VN of G5 gradually becomes longer, and R
Hiiragi is in an unlocked state. At this time, the vertical synchronization signal V
The signal obtained by sampling N at the beginning (rising edge) of the vertical synchronizing signal VE, that is, the signal output from the Q terminal of the DFF 17 is at the top level. Also, the signal from the Q terminal of 0FF17 and the vertical synchronization signal VE are supplied to the N
The OR circuit 19 outputs an H level signal from the end (falling edge) of the vertical synchronization signal VE to the beginning (rising edge) of the next vertical synchronization signal VE. In other words, an L level signal is output only during the period of the vertical synchronizing signal VE.

Therefore, as shown in FIGS. 5(A) and 5(B), when the vertical synchronizing signal VN arrives at the CK (clock) terminal of the DFF 20 immediately after the unlock state is detected, it is within the vertical synchronizing signal VE period, so the NOR The circuit 19 outputs an L level signal, and the L level signal is supplied to the CLR (clear) terminal of the DFF 20, and the DFF 20 is preset, so when the difference in the number of scanning lines is [2n-1], As shown in FIG.
Since it does not output an H level signal (signal indicated by a dotted line in FIG. 5C) with a time width of E], but outputs an L level signal, no phase modulation signal is supplied to the phase modulation circuit 11. Furthermore, since it is in the unlocked state, the scanning line matching circuit 14 does not operate. Therefore, since no phase modulating signal is supplied to the phase modulating circuit 11 from anywhere, the vertical synchronizing signals VN and VE will change from the state immediately after the transition from the locked state to the unlocked state due to some external factor. This will continue unless the condition is forcibly removed.

In other words, although the lock detection circuit 12 detects the unlocked state, the vertical synchronizing signals @VN and VE are actually almost in the locked state, so that synchronous coupling in the vertical direction is possible. In other words, if the start (rising edge) of the vertical synchronization signal VN is within the period of the vertical synchronization signal VE,
Since the DFF 20 is connected to [Pricera], it does not output a harmonic signal.

The phase adjusting circuit 11 will be explained below with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram for explaining the harmonic circuit 11, and FIG. 7 is a diagram for explaining the operation of the phase adjusting circuit 11.

In FIG. 6, the same components as in FIG. 2 are given the same reference numerals and their explanations will be omitted.

31 is a VCO signal input terminal, 32 is a DFF, 33 is a phase adjustment signal input terminal, 34 is OFF, 35 is a NOR circuit, 36
is a NOR circuit, 37 is a clock signal output terminal, 3824
- is a NOR circuit.

The VCO signal input terminal 31 has signals from VCO10 to FIG.
A lock signal is supplied as shown in A), and this clock signal is supplied to the OK (clock) terminal of the DFF 32. The DFF 32 outputs a lock signal from the terminal Q as shown in FIG. 7(B) with a cycle twice as long as the clock signal supplied from the VC010.

The phase adjustment signal input terminal 33 is connected to the OR circuit 15 (not shown in FIG. 6), and is supplied with a phase adjustment signal.

In the locked state, the scanning line number matching circuit 14 outputs the DFF from the phase adjustment signal input terminal 33 only while outputting the phase adjustment signal.
Since an H level signal (phase adjustment signal) is supplied to the D terminal of FF 34, an H level signal is output from the Q terminal of the FF 34, and an L level signal is output from the 0 terminal. Therefore, the lock signal as shown in FIG. 7(B) supplied from the Q terminal of the DFF 32 to the NOR circuit 35 is NOR.
This clock signal is output from the circuit 35 and furthermore, this clock signal is output from the circuit 35.
The clock signal is output from the clock signal output terminal 37 via the OR circuit 36.

When the supply of the phase adjustment signal from the scanning line number matching circuit 14 is completed, an L level signal is supplied from the OR circuit 15 to the D terminal of the DFF 34, so an L level signal is output from the Q terminal of the DFF 34, and the Q An H level signal is output from the terminal. Therefore, the seventh
A lock signal is output from the NOR circuit 35 as shown in FIG.
The clock signal is output from the clock signal output terminal 31 via the clock signal 6.

The clock signal output from the clock signal output terminal 37 is supplied to the clock input terminal of NG5. Therefore, in the locked state, the frequency of the clock signal supplied to the clock input terminal of NG5 changes only while the phase adjustment signal for matching the number of scanning lines is output from the scanning line number matching circuit 14, and In the locked state, the frequency of the clock signal supplied to the clock input terminal of NG5 remains constant only while the lock detection circuit 14 outputs a phase adjustment signal for synchronizing the vertical synchronization signal.

Note that from the clock signal shown in FIG. 7(A>) to the clock signal shown in FIG.
The timing for switching to the clock signal shown in B) or vice versa is the CK (clock) of the DFF34.
Since the terminal is connected to the Q terminal of the DFF 32, the processing is always performed at the rising edge of the clock signal shown in FIG. 7(B). Therefore, the clock signal is always switched between the clock signal shown in FIG. 7(A) and the clock signal shown in FIG. 7(B).
Since the switching is performed at the common part of the waveform with the clock signal shown in FIG. 1, the switching is performed smoothly without disturbing the clock signal, so that the operation of NG5 is not affected.

In addition, in the unlocked state, the lock detection circuit 12 supplies an H level signal to the D terminal of the DFF 34 for the vertical synchronization signal error time [VN - VE], so that the lock detection circuit 12 supplies the D terminal of the DFF 34 with the vertical synchronization signal error time [VN - VE ], so that the lock detecting circuit 12 supplies the D terminal of the DFF 34 with a signal of the H level for the vertical synchronization signal error time [VN - VE ]. A lock signal is output from the clock signal output terminal 37 as shown in (B). In other words,
In the locked state, the lock signal is output from the clock signal output terminal 37 only while the scanning line number matching circuit 14 is outputting the delayed signal, as shown in FIG. In this state, the lock detection circuit 12 detects the vertical synchronization signal error time [
Vh-VE], a lock signal as shown in FIG. 7(B) is output from the clock signal output terminal 37. Therefore, in the unlocked state, compared to the locked state, the only difference is the type of phase adjustment signal that is supplied, and the rest is the same, so a description thereof will be omitted.

In addition, the above-mentioned DFF32, DFF34, NOR circuit 3
5, 36, and 37 are elements constituting the phase adjustment circuit 11.

As mentioned above, when in the locked state, the clock signal supplied to the clock input terminal of NG5 becomes the frequency of the urn to match the number of scanning lines, and when in the unlocked state, the clock signal supplied to the clock input terminal of NG5 synchronizes the vertical synchronizing signals VN and VE. Become the frequency of the master in order to do it. When the clock signal has a frequency of 2, the operating speed of NG5 becomes 2. However, since the CPLI clock signal is always constant, a situation arises in which the operating speeds of the NG5 and the CPU are different. In such a state, the CPLI is unable to write information to the display memory, etc.
When accessing G5, there is a possibility that the interface between the CPU and NG5 becomes uncertain. To prevent this kind of phenomenon, NG
If the clock frequency of No. 5 is low, it is possible to stop the operation of the CPU, that is, to provide a WAIT signal generation circuit that outputs a WAIT<wait) signal to the CPU.

FIG. 8 is a diagram for explaining the WAIT signal generation circuit. In FIG. 8, the same components as in FIG. 1 are given the same reference numerals and their explanations will be omitted. 39 is AND
40 is a CPU, and 41 is a WAIT signal generation circuit.

The AND circuit 39 includes the OR circuit 15 and the 5E of the CPU 40.
LCT terminal (terminal where a signal is output while CRtJ40 is transmitting data, address, etc. to NG5)
The signal is supplied from.

When the phase adjustment signal is supplied from the OR circuit 15, the CPU 40
When a signal is supplied from the 5ELE'CT terminal of the AND
The circuit 39 supplies pulses to the WAIT signal generating circuit 41. The WAIT signal generation circuit 41 is composed of a heavy stable multivibrator circuit, a counter circuit, etc.
Due to the pulses supplied from the D circuit 39, the W
It generates an AIT (wait) signal, outputs this WAIT (wait) signal to the CPU 40, and stops the operation of the CPU 40.

Therefore, when the operating speeds of NG5 and CPU differ, the CPU is prohibited from accessing NG5 for writing information to display memory, etc.
It is possible to prevent the occurrence of a phenomenon in which the interface between the NG5 and the NG5 becomes uncertain.

By the way, in order to superimpose a television video signal and a personal computer video signal, that is, to prioritize multiple video signals and display them superimposed according to this priority, it is necessary to combine the video signals synchronously. It is conceivable to select and switch as shown in FIG. 9 and output it to a television receiver. FIG. 9 is a diagram for explaining superimposition.

In FIG. 9, the same components as in FIG. 2 are given the same reference numerals, and their explanations will be omitted. 42 is a changeover switch circuit, and 43 is a personal computer.

A personal computer 43 is connected to the changeover switch circuit 42.
and video signals from the video equipment 3 are supplied. The video signal supplied from the personal computer 43 and the video signal supplied from the video equipment 3 are synchronously coupled.

The switch circuit 42 also includes a personal computer 4.
A control signal is supplied from 3. This control signal indicates that when the video signal from the personal computer 43 is output, the video signal from the personal computer 43 is transmitted to the television! This is a signal for selectively switching the selector switch circuit 42 so as to be supplied to fi4.

Accordingly, a video in which the video signal output from the personal computer 43 is superimposed on the video signal output from the video equipment 3 is displayed on the television receiver 4.

Furthermore, as shown in Figure 9, it is possible to connect multiple personal computers and video equipment in a cascade configuration and synchronize the video signals of each video signal. pose image) is obtained. Therefore, the scope of application of the present invention is extremely wide.

Note that the above-described synchronous coupling device according to the present invention can be applied to any format in which the video signal outputted from the external video signal generator 8 is the NTSC format, the PAL format, or the SECAM format.

In addition, since the vertical scanning frequency generated by the non-interlaced video signal generator 5 is equivalently made equal to the video signal generated by the external video signal generator 8, once the lock state is reached, the vertical scanning frequency of the television signal is The lock state can be maintained even if the synchronization signal is lost.

Further, even when the scanning line number counter of the non-interlaced video signal generator 5 cannot be operated from the outside, synchronous coupling can be achieved.

(Effects of the Invention) Since the present invention has the above-described configuration, in order to generate a superimposed signal (overlapping with priority), video signals having the same number of scanning lines are connected in the vertical direction. It also has the advantage that it is possible to achieve synchronized coupling in the horizontal direction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the synthesis of superimposed signals, FIG. 2 is a block diagram of an embodiment of the synchronous coupling device according to the present invention, and FIG. 3 is a block diagram of the lock detection circuit 12 and scanning lines. FIGS. 4(A), 4(B), and 4(C) are circuit diagrams for explaining the number matching circuit 14, and FIGS. Figure 5 <A), (B), and (C) show the lock detection circuit 1 in a locked state between signals with the same number of scanning lines.
2 is a diagram for explaining the operation of the harmonic circuit 11, FIG. 7 is a diagram for explaining the operation of the phase adjusting circuit 11, and FIG. 8 is a WΔIT signal generation circuit. FIG. 9 is a diagram for explaining superimposition. DESCRIPTION OF SYMBOLS 1...Personal computer, 34-2...Superimposed signal synthesis circuit, 3...Video equipment, 4...Television receiver, 5...Non-interlaced video signal generator (NG) ,
6... Synchronization signal separation circuit, 7... Phase difference detection circuit,
8... External video signal generator (EG), 9... Synchronization signal separation circuit, 10... Voltage controlled oscillator (VCO), 11... Phase adjustment circuit, 12... Lock detection circuit, 13 ...Lock/unlock signal output terminal, 14...
・Scanning line number matching circuit, 15...OR circuit, 16...
Vertical synchronization signal input terminal, 17...D type flip 70 tube circuit (OFF), 18
...Vertical synchronization signal input terminal, 19...NOR circuit,
20...DFF, 21...Output terminal, 22...O
FF. 23... Shift 1-register, 24... Shift 1-register, 25... Inverter, 26... AND circuit,
27... Inverter, 28... AND circuit, 29.
...Output terminal, 30...Output terminal, 31...VCO
Signal input terminal, 32...DFF, 33...Phase adjustment signal input terminal, 34...DFF, 35...NOR circuit,
36...NOR circuit, 37...Clock signal output terminal, 3B...NOR circuit 39...AND circuit, 40
...cpu. 41... WAIT signal generation circuit, 42... Changeover switch circuit, 43... Personal computer. Patent Applicant: Victor Company of Japan Co., Ltd. Relationship with Patent applicant address: 3-12 Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Voluntary amendment 5, Detailed description of the invention and drawing 6 in the specification subject to the amendment, Contents of the amendment (1), page 17 Correct "Because it is preset" written in line 20 to line 1 of page 18 to "because it continues to be cleared." (2) Before "shift register 23" written in line 4 of page 20. Insert the following sentence: [Note that the horizontal synchronization signal HE separated by the synchronization separation circuit 9 from the luminance signal component of the video signal output from the EG8 is input to the horizontal synchronization signal input terminal 44; The synchronization signal HE is supplied to the GK (clock) terminal of the shift registers 23 and 24. Therefore, ] (3) [[n-11J to r[n+
1] Correct J. (4) Replace [Q n−+ J with “Qn
+1” and correct it. (5) r[n-11J written in page 20, line 8 as r[n]
Correct it with J. (6) r[n]J written on page 20, line 13 is set to r[n-1
]J and correct it. (7) r[n]J written in page 20, line 14 as r[n-1
]J and correct it. (8) [[n-1] J to r[ described on page 20, line 16
n]J. (9) Correct "shift register 23, inverter 25, AND circuit 26" written in lines 7 to 8 of page 22 to "shift register 24, inverter 27, AND circuit 28". (10) "Preset" in line 10 of page 24 and lines 10 to 11 of page 25 is replaced by "cleared"
and correct it. (11) l stated in page 27, lines 5 to 6 and line 7
"NOR circuit 35" is corrected to "INOR circuit 38". (12) "37" written in line 8 of page 29 is corrected to "38". (13) Delete "in order to" written on page 29, line 13. (14) Page 29, line 20 and page 31, lines 8 to 9
Correct "interface" in the line to "interface". (15) Change the rcRUJ described in page 30, line 12 to “CPU
” he corrected. (16) Figures 3 and 4 of the attached drawings are amended as per the attached sheet. 4- 4-year-old

Claims (1)

[Claims] A video signal output from an external video signal generator and a non-interlace video signal having the same number of scanning lines as the video signal output from a non-interlace video signal generator having a clock input terminal and output from the external video signal generator. A synchronous coupling device that performs vertical and horizontal synchronous coupling with a video signal, the horizontal synchronizing signal HN of a non-interlaced video signal output from the non-interlaced video signal generator and the external video signal generator. a phase difference detection circuit that is supplied with a horizontal synchronization signal HE of a video signal outputted from the horizontal synchronization signal HN and generates a phase error voltage by converting the phase difference between the horizontal synchronization signal HN and the horizontal synchronization signal HE into a voltage form; a voltage controlled oscillator that outputs a clock signal with a frequency corresponding to the phase error voltage output from the circuit, and a clock input terminal of the non-interlaced video signal generator that, under normal conditions, receives the clock signal supplied from the voltage controlled oscillator. In a phase modulating state in which a phase modulating signal is supplied to the phase modulating signal input terminal, a clock signal with a frequency of 4- is applied to the clock signal supplied from the voltage controlled oscillator as the clock signal of the non-interlaced video signal generator. a harmonic circuit that selectively switches to supply the input terminal;
A vertical synchronization signal VN of a non-interlace video signal output from the non-interlace video signal generator and a vertical synchronization signal VE of a video signal output from the external video signal generator are supplied, and when the vertical synchronization signal VE arrives, A state where the vertical synchronizing signal VN is present is determined to be a locked state and a lock signal is output, and a state where the vertical synchronizing signal VN is not present when the vertical synchronizing signal VE arrives is determined to be an unlocked state and an unlock signal is output. When determining the unlocked state, the start of the vertical synchronization signal VN is the vertical synchronization signal VE.
If it is not within the period, a phase adjustment signal having a time width from the arrival of the vertical synchronization signal VN immediately after determining the unlocked state to the arrival of the vertical synchronization signal VE is supplied to the adjustment signal input terminal of the phase adjustment path. and a lock detection circuit that determines a first field and a second field of a non-interlace video signal output from the non-interlace video signal generator during a period in which the lock detection circuit is determining a lock state. A phase modulation signal for [n-1] horizontal scanning periods of the non-interlaced video signal outputted from the non-interlaced video signal generator at the beginning of one field is supplied to the modulation signal input terminal of the harmonic circuit. Scanning in which a phase shift signal for [n] horizontal scanning periods of a non-interlace video signal output from the non-interlace video signal generator at the beginning of the other field is supplied to a phase shift signal input terminal of the phase shift circuit. A synchronous coupling device consisting of a wire number matching circuit.