JPH0517750B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to an image memory device, and more particularly to an image memory device for obtaining a reduced image from a composite video signal.

BACKGROUND ART Such an image memory device is used to obtain a small screen when displaying another small screen within a monitor screen, and a conventional example thereof is shown in FIG. In this figure, a composite video signal for a child screen inputted to an input terminal IN ₁ is separated into a luminance (Y) signal and a color (C) signal by a Y/C separation circuit 1 .
The separated luminance signal is digitized by a direct analog/digital converter (hereinafter referred to as A/D converter) 2, and the color signal is demodulated into color difference signals (BY, RY) by a demodulation circuit 3. After that, they are each digitized by A/D converters 4 and 5. The synchronization separation circuit 6 separates and extracts the horizontal synchronization signal contained in the composite video signal and supplies it to the PLL circuit 7. The PLL circuit 7 generates a clock having a frequency that is an integral multiple of the horizontal scanning frequency based on the input horizontal synchronizing signal, and
It is supplied as a sampling clock to the D converters 2, 4, and 5, and as a write clock to a controller 9 that controls writing and reading of the image memories 8A to 8C. The digitized luminance signal and color difference signal (B-Y, R-Y) are stored in the image memory 8.
The signals A to 8C are respectively supplied and sequentially written to addresses specified by the controller 9 based on the previous write clock.

On the other hand, the composite video signal for the main screen input to the input terminal IN ₂ is sent to the sync separation circuit 10 and the APC
(Auto Phase Control) It is supplied to the circuit 11 and becomes one input of the switch 12. The output of the APC circuit 11 becomes the carrier of the balanced modulator 18.
The horizontal synchronization signal separated and extracted by the synchronization separation circuit 10 is multiplied several times as much as the write clock by the PLL circuit 13 and sent to the controller 9 as a read clock, and further to a digital/analog converter (hereinafter referred to as "sampling clock"). (referred to as D/A converters) 14 to 16, respectively. The luminance signal and color difference signal (BY, RY) data written in the image memories 8A to 8C are read out under the control of the controller 9 based on the read clock. Each of the read data is converted into analog data by D/A converters 14 to 16, and the luminance signal is supplied to a mixer 17, and the color difference signal (BY, RY) is supplied to a balanced modulator 18. The balanced modulator 18 performs balanced modulation on a carrier in which the color difference signal (BY, RY) is locked to the color subcarrier of the composite video signal for the main screen. The output of this balanced modulator 18 is mixed with a luminance signal in a mixer 17 and becomes the other input of the switch 12. The switch 12 is switched by a switch control circuit (not shown) at appropriate timing based on horizontal and vertical synchronizing signals included in the composite video signal for the main screen.

In this way, by making the speed at which data is read from the image memories 8A to 8C faster than the speed at which data is written, the time axis of the read data is compressed, and as a result, the image is reduced. In addition, the composite video signal is separated into a luminance signal and a color signal, and the luminance signal is directly A/D converted, and the color signal is demodulated to a color difference signal and then A/D converted, so the phase of the color subcarrier signal is Since the reduction process can be performed independently of the size, the colors can be maintained correctly even if the image is reduced at any magnification.

However, in the conventional device with such a configuration, three sets of A/D converter, image memory, and D/A converter are required by processing each signal of the luminance signal and color difference signal (B-Y, R-Y) separately. Moreover, since circuits such as a demodulator and a balanced modulator are necessary, the circuit configuration is complicated and the number of parts is large, resulting in high cost.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional devices as described above, and provides an image memory device for reduced images that achieves cost reduction by simplifying the circuit configuration and reducing the number of parts. The purpose is to

The image memory device according to the present invention provides a color subcarrier signal that synchronizes the sampling clock of an A/D converter that digitizes a composite video signal and the write clock of an image memory that stores the digitized composite video signal with a color subcarrier signal. The clock has a frequency that is n/(n+1) times the carrier frequency (n is an integer of 3 or more), and is the read clock of the image memory and the sampling clock of the D/A converter that converts digital data read from the image memory into analog. The clock has a frequency n times the color subcarrier frequency.

Embodiments Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the composite video signal for the small screen input to the input terminal IN ₁ is directly sent to the A/D converter 20.
is digitized by the synchronization separation circuit 21 and
It is also supplied to the PLL circuit 22. Synchronous separation circuit 2
1 separates and extracts the horizontal synchronization signal and vertical synchronization signal included in the composite video signal and stores it in the image memory 23.
Controller 2 controls writing and reading of
Supply to 4. The PLL circuit 22 has a color subcarrier frequency fsc ₁ n/(n+1) synchronized with the color subcarrier signal of the composite video signal for the child screen.
A clock of twice the frequency (n is an integer of 3 or more) is generated and supplied to the A/D converter 20 as a sampling clock and further to the controller 24 as a write clock. The digitized composite video signal is supplied to image memory 23 and is written sequentially to addresses specified by controller 24 based on the previous write clock.

On the other hand, the composite video signal for the main screen inputted to the input terminal IN ₂ is supplied to the synchronization separation circuit 25 and the PLL circuit 26 and becomes one input of the switch 27 . The synchronization separation circuit 25 separates and separates the horizontal synchronization signal and vertical synchronization signal contained in the composite video signal.
It is extracted and supplied to the controller 24. Also,
The PLL circuit 26 generates a clock having a frequency n times the color subcarrier frequency fsc ₂ (=fsc ₁ ) synchronized with the color subcarrier signal of the composite video signal for the main screen, and supplies the clock to the controller 24 as a readout clock. It is supplied to the D/A converter 28 as a sampling clock. The data of the composite video signal written in the image memory 24 is read out under the control of the controller 24 based on the read clock. The read data is sent to D/A converter 2
8 is converted into an analog signal and becomes another input to the switch 27. The switch 27 is switched by a switch control circuit (not shown) at appropriate timing based on the horizontal and vertical synchronizing signals contained in the composite video signal for the main screen.

Next, the operation of the present invention will be explained using an example in which the display screen is reduced to 1/5 in size and 1/25 in area, that is, the case where n=4.

First, the frequencies of the sampling clock of the A/D converter 20 and the writing clock of the image memory 23 are n/(n+1) times the color subcarrier frequency fsc ₁ of the composite video signal for the small screen, so (4 /5) fsc ₁ , and each frequency of the readout clock of the image memory 23 and the sampling clock of the D/A converter 28 is equal to the color subcarrier frequency fsc ₂ (=fsc ₁ ) of the composite video signal for the main screen. Since it is multiplied by n, it becomes 4fsc ₂ .

Here, in FIG. 2, a color signal component B is shown in which a part of the composite video signal A for the child screen is enlarged.
is sampled and written to the image memory 23,
If this is to be read out, the ↓ mark in the figure is 1/
It shows the period of 4fsc ₁ , and the circle indicates the point actually sampled with the sampling clock of the frequency of (4/5) fsc ₁ . Since the sampling clock is locked to the color subcarrier of the composite video signal A for the child screen, each sampling point is sampled at a point shifted by 90 degrees on the color subcarrier. After writing the data sampled by the A/D converter 20 into the image memory 23 in this way,
Read and D/A with 4fsc ₂ frequency clock
When converted, as shown in FIG. 2C, a waveform whose time axis is compressed to 1/5 and whose color subcarriers are continuous is obtained. Therefore, the image can be reduced in the horizontal direction while maintaining the composite video signal. Note that since the vertical direction can be reduced by thinning out the scanning lines, the entire screen can be reduced easily.

The reduced image information obtained in this manner is appropriately selected by the switch 27 in place of the composite video signal for the main screen according to the insertion position on the monitor screen, and is supplied to the monitor (not shown). This allows a child screen to be displayed within the monitor screen (main screen).

In the above embodiment, the case where n=4 has been described, but the present invention is not limited to this, and n can be arbitrarily selected as long as it is 3 or more. That is, the size of the reduced screen can be set to 1/n, which is 1/4 or less.

Effects of the Invention As explained above, according to the image memory device according to the present invention, the sampling clock of the A/D converter that digitizes the composite video signal and the writing of the image memory that stores the digitized composite video signal The color subcarrier frequency n/(n
+1) The clock has a frequency that is twice as high as the color subcarrier frequency, and the read clock of the image memory and the sampling clock of the D/A converter that converts digital data read from the image memory into analog are used as a clock that has a frequency that is n times the color subcarrier frequency. This makes it possible to reduce the image directly from the composite video signal while preserving the continuity of the color subcarriers, making it possible to simplify the circuit configuration and reduce the number of parts, resulting in lower costs. Become.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1, and FIG. 3 is a block diagram showing a conventional example. Explanation of symbols of main parts 2, 4, 5, 20...
A/D converter, 8A to 8C, 23...image memory,
14-16, 28...D/A converter.

Claims (1)

[Claims] 1. An A/D converter that digitizes a composite video signal, an image memory that stores the digitized composite video signal, and a D/A converter that digitizes digital data read from the image memory. , the sampling clock of the A/D converter and the writing clock of the image memory are synchronized with the color subcarrier signal at a frequency n/(n+1) times (n is an integer of 3 or more) the color subcarrier frequency. An image memory device characterized in that a read clock of the image memory and a sampling clock of the D/A converter are clocks having a frequency n times higher than a color subcarrier frequency.