JPH06253337A - Time base corrector device - Google Patents

Abstract

PURPOSE:To provide a time base corrector device which can generate plural frequency clocks without becoming complex in constitution by providing a reference frequency signal generating means, a switching means, and a phase modulating means. CONSTITUTION:A synchronous separation part 1 separates a horizontal synchronizing signal from an input video signal and supplies it to a phase modulation part 4. Clock sources 5 and 6 which generate reference clocks differing in frequency are connected to the phase modulation part 4 through a switch 7. The phase modulation part 4 matches the phase (rise timing) of a clock supplied through the switch 7 with the phase (fall timing) of a horizontal synchronizing signal outputted from the separation part 1 and outputs it as a sampling and write clock. Consequently, even when plural clock frequencies (sampling clock frequency) are required, the hardware constitution does not become complex correspondingly and the cost is reduced.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time base collector device, and more particularly to a time base collector device having a plurality of sampling clocks. 2. Description of the Related Art In order to remove a time base fluctuation of an input signal,
A time base collector (TBC) device is widely used in which the input signal is written in a memory by a write clock (first clock) and the written signal is read by a stable-phase read clock (second clock). A conventional example of such a time base collector is shown in FIG. In this example, the time-axis fluctuation of the image data is absorbed, and the horizontal separation signal is separated from the video signal by the synchronization separation unit 51 and is supplied to one input terminal of the phase comparator 52 forming the PLL circuit. Phase comparator 52
A low-pass component is extracted from the output of the low-pass filter 53, and is output to the voltage controlled oscillator (VCO) 54. The oscillating frequency signal of the voltage controlled oscillator defined by the output voltage of the low pass filter 53 is divided into 1 / N by the frequency divider 55 and supplied to the other input terminal of the phase comparator 52. The phase comparator 52, the low pass filter 53,
PL comprising a voltage controlled oscillator 54 and a frequency divider 55
The output clock (from the voltage controlled oscillator 54) obtained by the L circuit is supplied as the sampling clock of the A / D converter 56 and the write clock of the frame memory 58. The A / D converter 56 samples the video signal at the sampling clock, and the sampled data is written to the frame memory 58 at the writing clock. Video data without jitter is read from the frame memory 58 by the read clock from the stable clock source 57. The oscillation frequency of the voltage controlled oscillator 54 and the clock frequency from the clock source 57 are substantially equal,
Since the time constant of the low-pass filter 53 is set appropriately, the output of the voltage controlled oscillator 54 almost completely follows the horizontal sync signal separated by the sync separator 51. The time base corrector is also used for the purpose of adjusting the time difference between the Y signal and the C signal of the video signal. As described above, the conventional time base collector device generates the sampling clock using the PLL circuit for generating the write clock and the clock source for generating the read clock. However, when a plurality of sampling clocks are required, it is necessary to prepare a plurality of PLL circuits and a plurality of separate clock sources for read clocks. Therefore, not only the hardware structure becomes complicated, but also a problem occurs in terms of cost. Therefore, an object of the present invention is to provide a time base collector device capable of generating a plurality of frequency clocks without complicating the structure. In order to solve the above-mentioned problems, the time base collector device according to the present invention uses a signal written in a memory at a first rate that faithfully follows the phase fluctuation of the input signal. In the time base collector device configured to reduce the fluctuation of the time axis by reading out at a phase stable second rate, the first signal, which is a signal component corresponding to the phase fluctuation, is extracted from the input signal. Phase signal extracting means, reference frequency signal generating means for generating a plurality of reference frequency signals having different frequencies,
Switching means for selectively taking out the output of one of the plurality of reference frequency signal generating means as a second signal, and the first signal for the second signal depending on the first signal. Phase modulation means for obtaining a write rate signal that defines the first rate by applying a phase variation related to the signal. Further, in order to adjust the time difference between the Y signal and the C signal of the video signal, the signal written in the memory is read at a rate that faithfully follows the phase fluctuation of the input signal to read the signal on the time axis at a phase stable rate. In a time-base collector device configured to reduce fluctuations, the memories are separately provided in correspondence with the luminance system signal system and the chrominance signal system, and the signal from the memory in the luminance system signal system is provided. It is also possible to provide the reading timing with a delay corresponding to the transmission delay amount of the color system signal with respect to the luminance system signal. According to the present invention, for example, a horizontal synchronizing signal, which is a signal component corresponding to a phase variation of the input video signal, is extracted, and a reference frequency selected from a plurality of reference frequency signals having different frequencies. A phase change is given to the signal based on the extracted horizontal synchronizing signal. Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a time base collector device according to the present invention. The sync separator 1 separates the horizontal sync signal from the input video signal and supplies it to the phase modulator 4. Clock sources 5 and 6 that generate reference clocks of different frequencies are connected to the phase modulator 4 via a switch 7. As shown in FIG. 2, the phase modulator 4 matches the phase (rising timing) of the clock supplied via the switch 7 with the phase (falling timing) of the horizontal sync signal output from the sync separator 1. And outputs as sampling and writing clock. The A / D converter 2 converts the input video signal into a digital signal by the sampling clock output from the phase modulator 4 and sends it to the frame memory 3. Digital data from the A / D converter 2 is written in the frame memory 3 by the write clock from the phase modulator 4. The clocks from the clock sources 5 and 6 are also supplied to the frame memory 3 via the switch 8 as a read clock, and the jitter-free video data is read from the frame memory 3. The switches 7 and 8 select one of the clock sources 5 and 6 having the required clock frequency. By switching the switches 7 and 8 in conjunction with each other, the video data read from the frame memory 3 is displayed on the time axis. The data will be corrected. FIG. 3 is a block diagram showing a second embodiment of the time base collector device according to the present invention. In this embodiment, the time constant of the low-pass filter 15 constituting the PLL circuit is set to a value sufficiently larger than the jitter component of the input video signal, and the output locked to the average horizontal frequency of the input video signal is voltage controlled. A line memory 13 is used instead of the frame memory 3 of the first embodiment shown in FIG. The sync separator 11 separates the horizontal sync signal from the input video signal and sends it to one input terminal of the phase comparator 14. The phase comparator 14, the low-pass filter 15, the voltage controlled oscillator 16 and the frequency divider 17 have the same functions as the PLL circuit configuration of FIG. 6, and the output of the voltage controlled oscillator 16 is output as the write clock of the line memory 13. It
The clock from the voltage controlled oscillator 16 is sent to the phase modulator 20 having the same function as the phase modulator 4 of FIG.
Is supplied via. The output from the voltage controlled oscillator 16 and the clock from the clock source 18 are supplied to the input terminal of the switch 19, and the selection switching operation is performed to generate the clock of the required frequency. Similar to the operation of the phase modulator 4 in FIG. 1, the phase modulator 20 matches the timing of the clock input via the switch 19 with the horizontal sync signal from the sync separator 11 and outputs the sampling clock and A / D as write clock
It is supplied to the converter 12 and the line memory 13. In the present embodiment, if the clock frequency from the clock source 18 is higher than the output frequency from the voltage controlled oscillator 16, the image read from the line memory 13 is reduced in the horizontal direction and, conversely, is lowered. Will be expanded. Next, a third embodiment of the present invention will be described with reference to FIG. The device to which the present invention is applied includes, for example, a static memory camera (SMC) in which a portable card-shaped memory cartridge is used as a medium and image information of a still image is recorded on the medium. ,
In this SMC system, the Y signal and the C signal are separately A / D converted and stored. At this time,
Before performing the A / D conversion process, a low-pass filter is provided to prevent the generation of aliasing noise. But,
The characteristics of the low-pass filter are different between the Y signal and the C signal, and the delay amount is also different. Usually, it is considered to install an analog delay line in order to adjust the delay amount. Therefore, as shown in the first and second embodiments described above, when a plurality of clock frequencies are used, a plurality of delay lines are required, which again causes problems in terms of hardware and cost. Therefore, in this embodiment, the delay line is not required by changing the read timing from the memory between the Y signal and the C signal. In FIG. 4, in the input video signal, the horizontal separation signal is separated by the synchronization separation unit 31, and the Y signal and the C signal are separated by the Y / C separation unit 32. On the output side of the Y / C separation unit 32, the C signal of the first clock frequency and the Y
Low-pass filters 33 (1) and 33 for signals
(3) and low-pass filters 33 (2) and 33 (4) for the C and Y signals of the second clock frequency are provided. The C signal from the Y / C separation unit 32 is input to the low pass filters 33 (1) and 33 (2), and the Y signal is input to the low pass filters 33 (3) and 33 (4). The switch 34 is a low-pass filter 33.
The outputs from (1) and 33 (2) are selected and supplied to the A / D converter 36, while the switch 35 selects the outputs from the low pass filters 33 (3) and 33 (4) to A / D converter 36.
It is supplied to the / D converter 37. Clock sources 43 and 44 that generate clocks of different frequencies are connected to the input terminals of the switches 45 and 47, and either clock is selectively output. The phase modulator 46, like the phase modulator 4 of FIG. 1, adjusts the phases of the clock input via the switch 45 and the horizontal sync signal from the sync separator 31 to obtain a sampling clock and a memory. Output as a write clock to. That is, the clock from the phase modulator 46 is directly supplied to the A / D converter 37 for the Y signal as the sampling clock, and the clock divided by the 1/2 frequency divider 38 is used as the sampling clock for the C signal. Is supplied to the A / D converter 36.
Similarly, in the C signal memory (C memory) 39 and the Y signal memory (Y memory) 40, the digital data from the A / D converters 36 and 37 is output to the output clock from the 1/2 frequency divider 38 and the phase modulation. The output clock from the unit 46 is written as the write clock. The Y memory 40 and the C memory 39 are supplied with the output clock from the switch 47 and the frequency-divided clock from the 1/2 frequency divider 42 as read clocks, and the video data is read. The read timing controller 41 uses, for example, a switch 47 to generate clock sources 43 and 4
The read timing of the C memory 39 and the Y memory 40 is controlled by receiving the information indicating which of the four is selected.
In the above embodiment, the switches 34, 35, 45 and 4
7 works together. Switching of the clock frequency (sampling clock frequency) in the embodiment described above is
For example, it is practically effective in the following cases. That is, considering data transfer between the SMC system and the personal computer, in the SMC system, the number of pixels is 768 pixels in the horizontal direction, whereas in the personal computer, the number of pixels is 640 pixels in the horizontal direction. Therefore, as shown in FIG. 5 (A), when a picture recorded with 768 pixels on the memory card of the SMC system is directly displayed on the display of the personal computer, the picture stretches in the horizontal direction as shown in FIG. 5 (B). The picture on the edge cannot be displayed. Therefore, when capturing an image for a personal computer, the user operates a switch to switch the clock source so that a sampling clock corresponding to the number of pixels of the personal computer is used. Alternatively, such a problem can be solved by reading the attribute information of the used memory card and switching based on the result, or switching to a still screen stored in the memory card. In addition, in the present invention, the pixel size is not limited to the compatibility between the NTSC size and the personal computer size, and can be used in various modes such as enabling the compatibility between the NTSC size and the PAL size. It is a thing. Further, as described above, in the SMC system, it is also useful when recording an image by enlarging or reducing it in the horizontal direction. That is, for example, the picture is horizontally
When the data is reduced to / 6, the picture normally reproduced by normal reproduction becomes a picture reduced to 5/6 by taking in data of 768 × 5/6 = 640 pixels, which is normally 768 pixels in the horizontal direction. In the above, the case where a plurality of sampling clocks are required corresponds to the case where pixel data having different pixel sizes (aspect ratios) are obtained from a video signal, for example, as described below. That is, in a system such as an electronic camera (SMC) that uses a solid recording medium such as a so-called card memory, when an NTSC-compliant video signal is recorded on the medium, the sampling clock of the luminance system is about 910 fh.
(Fh is a horizontal synchronizing frequency, which is about 15.734 kHz, and therefore 910 fh is about 14.318 MHz). When the above video signal is sampled at this frequency, the aspect ratio of each pixel is 1: 0.83 (however, this is the case of frame recording. In the case of field recording, it is twice as long as this). . This pixel vertically 48
This is because the aspect ratio of one screen composed of 0 and 768 horizontally arranged is 3: 4 (3/4).
80: 4/768 = 0.83). On the other hand, the pixels of a personal computer (many models) have an aspect ratio of 1: 1. This is because the personal computer is defined so that the aspect ratio of one screen composed of 480 pixels vertically and 640 pixels horizontally becomes 3: 4 (3/480: 4/640 = 1: 3).
1). When pixel data of different sizes (aspect ratios) are obtained from video signals as described above, it is usually possible to keep the sampling number (frequency) constant in the vertical direction of the screen and apply sampling clocks with different frequencies in the horizontal direction. Done. This is because the video signal is a discrete signal for each scanning line in the vertical direction, but is a continuous signal in the horizontal direction, and therefore it is much more realistic to change the sampling clock in the horizontal direction. As described above, multiple sampling clocks with different frequencies are prepared, and the SM
Corresponding to C, sampled and recorded at 910fh,
Different frequencies (14.31818)
By sampling and recording at (640/768 = 11.932 MHz), it is possible to match each predetermined pixel size. As described above, according to the time base collector of the present invention, even when a plurality of clock frequencies (sampling clock frequencies) are required, the hardware configuration becomes complicated accordingly. This is also beneficial in terms of cost.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a first time base collector device according to the present invention.
It is a block diagram showing an example of. FIG. 2 is a timing chart for explaining the operation of the phase modulation unit in the first embodiment. FIG. 3 is a second time base collector device according to the present invention.
It is a block diagram showing an example of. FIG. 4 is a third time base collector device according to the present invention.
It is a block diagram showing an example of. FIG. 5 is a diagram for explaining an application example of the present invention. FIG. 6 is a block diagram of a conventional time base collector device. [Description of Codes] 1, 11, 31, 51 Sync Separation Units 2, 12, 36, 37, 56 A / D Converter 3, 58 Frame Memory 4, 20, 46 Phase Modulation Units 5, 6, 18, 43, 44 , 57 clock sources 7, 8, 19, 34, 35, 45, 47 switch 13 line memory 14, 52 phase comparator 15, 33 (1) to 33 (4), 53 low-pass filter 16, 54 voltage controlled oscillator 17, 55 1 / N frequency divider 32 Y / C separation sections 38, 42, 1/2 frequency divider 39 C memory 40 Y memory 41 Read timing controller

Claims (1)

What is claimed is: 1. A method for reducing fluctuation of a time axis by reading a signal written in a memory at a first rate that faithfully follows a phase fluctuation of an input signal at a second rate that is phase-stable. In the made time base collector device, the first component which is a signal component corresponding to the phase fluctuation from the input signal is provided.
A phase signal extracting means for extracting a signal of the reference signal, a reference frequency signal generating means for generating a plurality of reference frequency signals having different frequencies, and an output of one of the plurality of reference frequency signal generating means. Switching means for selectively extracting as the signal of the first signal, and the first signal by applying the phase fluctuation related to the first signal to the second signal depending on the first signal.
And a phase modulation means for obtaining a write rate signal that defines the rate of the time base collector device.