JPH077744A - Time base collector device - Google Patents

Abstract

PURPOSE:To adjust delay amount of signals C, Y and to correct time axis fluctuation without special provision of an analog delay line by controlling a read timing from C, Y memories with a timing controller. CONSTITUTION:A synchronizing separator circuit 31 separates a horizontal synchronizing signal from an input video signal and is separated into C, Y signals at a Y/C 32 and the result is fed to A/D converters 36, 37. Digital data from the A/D converters 36, 37 are written separately into a C memory 39 and a Y memory 40 based on an output clock from a 112 frequency divider 38 and a phase modulation section 46. In the case of reading, an output clock from a switch 47 and a frequency division clock from a 112 frequency divider 42 are fed to the memories 39, 40 as read clocks under the control of a read timing controller 41 to read video data. Thus, the delay of the signals C, Y is adjusted without special provision of an analog delay line and the device is made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time base collector suitable for use in a video signal processing system.

[0002]

2. Description of the Related Art In order to eliminate a time base fluctuation of an input signal,
A time base collector (TBC) device is widely used in which the input signal is written in a memory by a write clock (first clock) and the written signal is read by a stable-phase read clock (second clock).

A conventional example of such a time base collector is shown in FIG. In this example, the time-axis fluctuation of the image data is absorbed, and the horizontal separation signal is separated from the video signal by the synchronization separation unit 51 and is supplied to one input terminal of the phase comparator 52 forming the PLL circuit. Phase comparator 52
A low-pass component is extracted from the output of the low-pass filter 53, and is output to the voltage controlled oscillator (VCO) 54. The oscillating frequency signal of the voltage controlled oscillator defined by the output voltage of the low pass filter 53 is divided into 1 / N by the frequency divider 55 and supplied to the other input terminal of the phase comparator 52.

The phase comparator 52, the low pass filter 53,
PL comprising a voltage controlled oscillator 54 and a frequency divider 55
The output clock (from the voltage controlled oscillator 54) obtained by the L circuit is supplied as the sampling clock of the A / D converter 56 and the write clock of the frame memory 58. The A / D converter 56 samples the video signal at the sampling clock, and the sampled data is written to the frame memory 58 at the writing clock.

Video data without jitter is read from the frame memory 58 by the read clock from the stable clock source 57. The oscillation frequency of the voltage controlled oscillator 54 and the clock frequency from the clock source 57 are substantially equal,
Since the time constant of the low-pass filter 53 is set appropriately, the output of the voltage controlled oscillator 54 almost completely follows the horizontal sync signal separated by the sync separator 51.

[0006]

The video signal processing system to which the present invention is applied is generally configured to handle a composite video signal. In such a signal processing system, the composite video signal is initially A / D converted into a Y signal (luminance system signal) and a C signal (color system signal) and stored. At this time, before performing the A / D conversion process, a low-pass filter is provided in order to prevent the generation of aliasing noise.
However, the characteristics of the low-pass filter are different between the Y signal and the C signal, and therefore the delay amount is also different. An analog delay line may be installed to adjust this delay amount. However, the provision of the delay line increases the scale of the circuit, which not only hinders the downsizing of the device, but is also disadvantageous in terms of cost.

Therefore, an object of the present invention is to provide a time base collector device capable of adjusting the delay amounts of the Y signal and the C signal without separately providing an analog delay line.

[0008]

In order to solve the above problems, the time base collector according to the present invention stabilizes the signal written in the memory in a phase manner at a rate that faithfully follows the phase fluctuation of the input signal. In a time-base collector device configured to reduce fluctuations of the time axis by reading at a rate, the above-mentioned memories are separately provided corresponding to the system of luminance system signals and the system of chrominance system signals, and the luminance system signals are provided. A means for reading the signal read timing from the memory in the (color system signal) system with a delay corresponding to the transmission delay amount of the color system signal (luminance system signal) with respect to the brightness system signal (color system signal) is provided. Characterize.

[0009]

[Operation] By controlling the read timing from each memory corresponding to the system of the luminance system signal and the system of the color system signal,
The adjustment of the delay amount of the luminance system signal and the color system signal and the time axis fluctuation correction are simultaneously performed.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a time base collector device according to the present invention. The sync separator 1 separates the horizontal sync signal from the input video signal and supplies it to the phase modulator 4. Clock sources 5 and 6 that generate reference clocks of different frequencies are connected to the phase modulator 4 via a switch 7. As shown in FIG. 2, the phase modulator 4 matches the phase (rising timing) of the clock supplied via the switch 7 with the phase (falling timing) of the horizontal sync signal output from the sync separator 1. And outputs as sampling and writing clock. The A / D converter 2 converts the input video signal into a digital signal by the sampling clock output from the phase modulator 4 and sends it to the frame memory 3. Digital data from the A / D converter 2 is written in the frame memory 3 by the write clock from the phase modulator 4.

The clocks from the clock sources 5 and 6 are also supplied to the frame memory 3 via the switch 8 as a read clock, and the jitterless video data is read from the frame memory 3. The switches 7 and 8 select one of the clock sources 5 and 6 having the required clock frequency. By switching the switches 7 and 8 in conjunction with each other, the video data read from the frame memory 3 is displayed on the time axis. The data will be corrected.

FIG. 3 is a block diagram showing a second embodiment of the time base collector device according to the present invention. In this embodiment, the time constant of the low-pass filter 15 constituting the PLL circuit is set to a value sufficiently larger than the jitter component of the input video signal, and the output locked to the average horizontal frequency of the input video signal is voltage controlled. A line memory 13 is used instead of the frame memory 3 of the first embodiment shown in FIG.

The sync separator 11 separates the horizontal sync signal from the input video signal and sends it to one input terminal of the phase comparator 14. The phase comparator 14, the low-pass filter 15, the voltage controlled oscillator 16 and the frequency divider 17 have the same functions as the PLL circuit configuration of FIG. 6, and the output of the voltage controlled oscillator 16 is output as the write clock of the line memory 13. It
The clock from the voltage controlled oscillator 16 is sent to the phase modulator 20 having the same function as the phase modulator 4 of FIG.
Is supplied via. The output from the voltage controlled oscillator 16 and the clock from the clock source 18 are supplied to the input terminal of the switch 19, and the selection switching operation is performed to generate the clock of the required frequency. Similar to the operation of the phase modulator 4 in FIG. 1, the phase modulator 20 matches the timing of the clock input via the switch 19 with the horizontal sync signal from the sync separator 11 and outputs the sampling clock and A / D as write clock
It is supplied to the converter 12 and the line memory 13.

In the present embodiment, when the clock frequency from the clock source 18 is higher than the output frequency from the voltage controlled oscillator 16, the image read from the line memory 13 is reduced in the horizontal direction and, conversely, is lowered. Will be expanded.

Next, a third embodiment of the present invention will be described with reference to FIG. A device to which the present invention is applied is, for example, a static memory camera (SMC or digital still camera (DSC) in which a portable card-shaped memory cartridge is used as a medium and image information of still images is recorded on the medium. )), But in this SMC system, the Y signal and the C signal are A / D converted separately and stored. At this time, A
Before performing the / D conversion process, a low-pass filter is provided to prevent the generation of aliasing noise. However, the characteristics of the low-pass filter are different between the Y signal and the C signal, and the delay amount is also different. Usually, it is considered to install an analog delay line in order to adjust the delay amount. Therefore, as shown in the first and second embodiments, when a plurality of clock frequencies are used,
A plurality of delay lines are required, which again causes problems in terms of hardware and cost. Therefore, in this embodiment,
By changing the read timing from the memory between the Y signal and the C signal, the delay line is unnecessary.

In FIG. 4, the input video signal is separated into a horizontal sync signal by a sync separator 31 and a Y / C signal by a Y / C separator 32. On the output side of the Y / C separation unit 32, the C signal of the first clock frequency and the Y
Low-pass filters 33 (1) and 33 for signals
(3) and low-pass filters 33 (2) and 33 (4) for the C and Y signals of the second clock frequency are provided. The C signal from the Y / C separation unit 32 is input to the low pass filters 33 (1) and 33 (2), and the Y signal is input to the low pass filters 33 (3) and 33 (4).

The switch 34 is a low-pass filter 33.
The outputs from (1) and 33 (2) are selected and supplied to the A / D converter 36, while the switch 35 selects the outputs from the low pass filters 33 (3) and 33 (4) to A / D converter 36.
It is supplied to the / D converter 37. Clock sources 43 and 44 that generate clocks of different frequencies are connected to the input terminals of the switches 45 and 47, and either clock is selectively output.

The phase modulator 46, like the phase modulator 4 of FIG. 1, adjusts the phases of the clock input via the switch 45 and the horizontal sync signal from the sync separator 31 to obtain a sampling clock and a memory. Output as a write clock to. That is, the clock from the phase modulator 46 is directly supplied to the A / D converter 37 for the Y signal as the sampling clock, and the clock divided by the 1/2 frequency divider 38 is used as the sampling clock for the C signal. Is supplied to the A / D converter 36.
Similarly, in the C signal memory (C memory) 39 and the Y signal memory (Y memory) 40, the digital data from the A / D converters 36 and 37 is output to the output clock from the 1/2 frequency divider 38 and the phase modulation. The output clock from the unit 46 is written as the write clock.

The Y memory 40 and the C memory 39 are supplied with the output clock from the switch 47 and the frequency-divided clock from the 1/2 frequency divider 42 as read clocks, and the video data is read. The read timing controller 41 uses, for example, a switch 47 to generate clock sources 43 and 4
The read timing of the C memory 39 and the Y memory 40 is controlled by receiving the information indicating which of the four is selected.
In the above embodiment, the switches 34, 35, 45 and 4
7 works together.

Switching of the clock frequency (sampling clock frequency) in the embodiment described above is
For example, it is practically effective in the following cases.

That is, considering data transfer between the SMC system and the personal computer, in the SMC system, the number of pixels is usually 768 pixels in the horizontal direction, whereas in the personal computer, there are 640 pixels in the horizontal direction. Therefore, as shown in FIG. 5 (A), when a picture recorded with 768 pixels on the memory card of the SMC system is directly displayed on the display of the personal computer, the picture stretches in the horizontal direction as shown in FIG. 5 (B). The picture on the edge cannot be displayed.

Therefore, when capturing an image for a personal computer, the user operates the switch to switch the clock source so that the sampling clock corresponding to the number of pixels of the personal computer is used. Alternatively, such a problem can be solved by reading the attribute information of the used memory card and switching based on the result, or switching to a still screen stored in the memory card. In addition, in the present invention, the pixel size is not limited to the compatibility between the NTSC size and the personal computer size, and can be used in various modes such as enabling the compatibility between the NTSC size and the PAL size. It is a thing.

Further, as described above, the SMC system is also useful when recording an image by enlarging or reducing it in the horizontal direction. That is, for example, the picture is horizontally
When the data is reduced to / 6, if the horizontal 768 pixels are taken in by 768 × 5/6 = 640 pixels, the picture reproduced by normal reproduction becomes a picture reduced to 5/6.

In the above description, the case where a plurality of sampling clocks are necessary corresponds to the case where pixel data having different pixel sizes (aspect ratios) are obtained from a video signal, for example, as described below. That is, in a system such as an electronic camera (SMC) that uses a solid recording medium such as a so-called card memory, when an NTSC-compliant video signal is recorded on the medium, the sampling clock of the luminance system is about 910 fh.
(Fh is a horizontal synchronizing frequency, which is about 15.734 kHz, and therefore 910 fh is about 14.318 MHz). When the above video signal is sampled at this frequency, the aspect ratio of each pixel is 1: 0.83 (however, this is the case of frame recording. In the case of field recording, it is twice as long as this). . This pixel vertically 48
This is because the aspect ratio of one screen composed of 0 and 768 horizontally arranged is 3: 4 (3/4).
80: 4/768 = 0.83). On the other hand, the pixels of a personal computer (many models) have an aspect ratio of 1: 1. This is because the personal computer is defined so that the aspect ratio of one screen composed of 480 pixels vertically and 640 pixels horizontally becomes 3: 4 (3/480: 4/640 = 1: 3).
1). When pixel data of different sizes (aspect ratios) are obtained from video signals as described above, it is usually possible to keep the sampling number (frequency) constant in the vertical direction of the screen and apply sampling clocks with different frequencies in the horizontal direction. Done. This is because the video signal is a discrete signal for each scanning line in the vertical direction, but is a continuous signal in the horizontal direction, and therefore it is much more realistic to change the sampling clock in the horizontal direction. As described above, multiple sampling clocks with different frequencies are prepared, and the SM
Corresponding to C, sampled and recorded at 910fh,
Different frequencies (14.31818)
By sampling and recording at (640/768 = 11.932 MHz), it is possible to match each predetermined pixel size.

[0025]

As described above, according to the time base collector device of the present invention, it is possible to adjust the delay amounts of the luminance system signal and the chrominance system signal without separately providing an analog delay line. Therefore, the circuit scale is reduced, and therefore the device can be downsized.
The cost can be reduced.

[Brief description of drawings]

1 a first time base collector device according to the invention, FIG.
It is a block diagram showing an example of.

FIG. 2 is a timing chart for explaining the operation of the phase modulation unit in the first embodiment.

FIG. 3 is a second time base collector device according to the present invention.
It is a block diagram showing an example of.

FIG. 4 is a third time base collector device according to the present invention.
It is a block diagram showing an example of.

FIG. 5 is a diagram for explaining an application example of the present invention.

FIG. 6 is a block diagram of a conventional time base collector device.

[Explanation of symbols]

1, 11, 31, 51 Synchronous separation unit 2, 12, 36, 37, 56 A / D converter 3, 58 Frame memory 4, 20, 46 Phase modulation unit 5, 6, 18, 43, 44, 57 Clock source 7 , 8, 19, 34, 35, 45, 47 switch 13 line memory 14, 52 phase comparator 15, 33 (1) to 33 (4), 53 low-pass filter 16, 54 voltage controlled oscillator 17, 55 1 / N minutes Frequency divider 32 Y / C separation section 38, 42, 1/2 frequency divider 39 C memory 40 Y memory 41 Read timing controller

Claims (1)

[Claims] 1. A time-base collector device adapted to reduce fluctuations of a time axis by reading out a signal written in a memory at a rate that faithfully follows a phase fluctuation of an input signal at a phase stable rate. The memory is provided separately corresponding to the system of the luminance system signal and the system of the color system signal, and the timing of reading the signal from the memory in the system of the luminance system signal (color system signal) is set to the system of the luminance system signal ( A time-base collector device comprising means for delaying and reading the color-based signals (luminance-based signals) corresponding to the transmission delay amount of the color-based signals.