JP3564714B2 - Video recording and playback device - Google Patents

Description

[0001]
[Industrial applications]
According to the present invention, a video signal is displayed on a monitor and, at the same time, the video signal is digitally compressed as a moving image in another sequence. The present invention relates to a video recording / reproducing apparatus that reproduces a moving image that has been digitally expanded and enlarged / reduced at an arbitrary position and an arbitrary size independently of the digitally compressed resolution.
[0002]
[Prior art]
A conventional example will be described with reference to FIG. The video signal 20 is sent to the video decoder unit 21 and separated into a color signal C, a luminance signal Y and a synchronization signal. The color signal and the luminance signal are digitized by the AD converter 22 (hereinafter abbreviated as ADC), and the video data that has been code-compressed by the video code compression circuit 27 are sent to the CPU 16 or the storage medium 15 by the CPU 16 and the bus line 29. Sent to The video data compressed from the CPU 16 or the storage medium 15 is sent to the video code expansion circuit section 28 through the CPU bus line 29, where the data is expanded. The decompressed data is written to a video memory 23, converted into an analog signal by a DA converter 24 (hereinafter abbreviated as DAC), sent to a video switch 25, and processed by a video switch 25 to output a signal from the DAC 24. The video signal 26 is switched. The video signal therefrom is sent to the monitor 31 and displayed. Therefore, when the video signal 20 is code-compressed on the CPU bus line 29 while being output to the monitor section 31 and is sent to the CPU 16 or the storage medium 15, the video signal 20 is converted from the video decoder 21 and the ADC 22 into a digital signal. The converted video data is code-compressed by a video code compression circuit section 27 and sent to a CPU or a storage medium via a CPU bus line 29. Upon receiving the signal from the video decoder 21, the compression / decompression control circuit 30 controls the video code compression circuit 27 and the video code expansion circuit 28. Next, the previously written video data is code-expanded from the CPU or storage medium through the CPU bus line 29 by the video code expansion circuit unit 28, the video memory 23 is updated, and displayed as a moving image on the monitor unit 31. You. Japanese Patent Application Laid-Open No. 5-41804 discloses a device similar to the conventional technology.
[0003]
[Problems to be solved by the invention]
However, in the conventional example, after the video signal 20 is written in the CPU or the storage medium in the frame unit or the field unit, the video memory 23 is updated, so that at least 1/2 or less of the frame unit or the field unit of the video signal. In this case, if both the frame unit and the field unit are collectively expressed as a "work unit", when the video signal is displayed on the monitor unit 31, it is less than 1/2 of the work unit. When the video data written in the CPU or the storage medium is reproduced by the video code decompression circuit unit 28, the work unit of the storage medium is 1/2 or less, so that the display is at least twice or more. The video data is in the fast-forwarded state. As described above, the video data obtained by the video code compression circuit unit 27 is code-expanded by the video code expansion circuit unit 28, and the video display size displayed on the monitor unit 31 is changed by the video code compression circuit unit. Since it is the resolution at the time of compression, the display size of the monitor unit 31 cannot be arbitrarily secured, and when enlarging data of the same image density as the display image when enlarging the displayed image, quality A bad image is simply obtained and cannot be enlarged to an arbitrary size, and it is impossible to cope with multimedia or the like that requires an arbitrary display size regardless of the size of the compressed data.
[0004]
An object of the present invention is to capture data independently of the display resolution of a moving image display monitor unit, realize smooth moving image display regardless of the moving image capture speed, and support multimedia.
[0005]
[Means for Solving the Problems]
The video recording / reproducing device of the present invention comprises:A processor for performing a logical operation;Controlled by the processorA writing control unit that operates in accordance with the first video signal, the first video signal being converted into a first video signal by a first analog-to-digital conversion unit.A write control unit that controls writing to the first storage medium, a read control unit that controls reading signals from the first storage medium for display,A moving image recording / reproducing unit which operates under the control of the processor, comprising a second analog / digital conversion unit for converting the input video signal into moving image data before compression,Compress and record on the second storage mediumWithA moving image recording / reproducing unit that expands a signal reproduced from the second storage medium and reproduces the signal as a second video signal, wherein the writing control unit switches between the first video signal and the second video signal. Further comprising a video switching unit for controlling the first analog-to-digital conversion unit and the first storage medium to reduce a video represented by the first video signal. And a video reduction function for writing to the first storage medium.
[0007]
[Action]
A video signal is displayed in a monitor while a video signal is converted into a digital signal, and the video signal is compressed and taken into a storage medium. An AD converter is provided which is independent of a sequence displayed on the monitor. Compress and store the data. As a result, the video data taken into the storage medium can be recorded at a resolution other than the displayed resolution without interruption in units of fields or frames, and video data of an undefined size is expanded from the storage medium into a video signal, and transmitted to the monitor unit. It is reproduced and displayed in any display size.
[0008]
【Example】
FIG. 1 is an operation diagram of the entire system according to the present invention. An analog video signal or a digital video signal 101 is input to a video signal separation unit 102, and is directly used as a first video signal by a write control unit 103 by a first video storage unit. The information is stored in the display unit 105 and displayed on the display unit 108 by the read control unit 106. Here, the input video signal further branched is taken in as a second video signal by the moving image recording / reproducing unit 109, switched by the switch unit 104 in the writing control unit 103, stored in the first video storage unit 105, and read out. The control unit 106 enlarges or reduces the size according to the display screen as needed, and the switch unit 107 superimposes the first video signal and the second video signal. The operation of the video signal is controlled via a CPU BUS 113 by, for example, a personal computer (PC main body) 111 having a built-in CPU and second video storage unit 112. Reference numeral 110 denotes a mouse for performing an input operation of the PC main body. The present invention is a further improvement of the technique of JP-A-4-307876 filed by the same applicant.
[0009]
2, the video signal input 140 is separated into a luminance signal Y and a chrominance signal C by a Y / C separation unit 141, and a color signal VVS1 ｛R / G / B or Y (luminance) is detected by a video decoder 142. ) U / V (hue) component｝, horizontal synchronizing signal HSTV and vertical synchronizing signal VSTV. The obtained color signal is sent to an AD converter unit 210 (hereinafter, referred to as “ADC 210”) and another AD converter unit 211 (hereinafter, referred to as “ADC 211”) to be converted into a digital signal. The signal from the ADC 210 is stored in the video memory unit 310 via the video switch 311. The stored signal is converted into an analog signal by a DA converter (hereinafter, referred to as “DAC”) 410 and displayed on the monitor unit 108 via the video switch unit 510. A signal from another ADC 211 is subjected to data compression by the video signal compression circuit unit 330, controlled by the CPU 620 and the compression / decompression control unit 320, and stored in the storage medium 720 via the common bus 610.
[0010]
When the video switch 311 of the interlocking switch is switched from the terminal 1 to the terminal 2 and the reproduction switch 312 is switched from the terminal 3 to the terminal 4, the compressed data in the storage medium 720 is expanded by the video signal expansion circuit 340 and stored in the video memory 310. Then, the image is controlled by the display enlargement / reduction control unit 420 to an arbitrary size or size, and is displayed on the monitor unit 108 via the video switch 510 from the DAC 410. Here, the video signal is divided into two streams by the ADCs 210 and 211 and is displayed at the display resolution or display size displayed on the monitor unit 108. However, the signals by the other ADCs 211 are irrelevant to the specifications of the display monitor. Can independently take in video data. The functions related to the compression / decompression control unit 320, the video signal compression circuit unit 330, and the video signal decompression circuit unit 340 are realized by an IC chip CL550 manufactured by C-Cube Microsystems of the United States using the International Standard Recommendation Draft JPEG (Joint Photographic Experts Group). ing. The related application technology is described in detail in "Interface" (published by CQ Publishing Co., Ltd., December 1991, pages 218 to 222).
[0011]
FIG. 3 shows a detailed block circuit diagram of the digitizing control unit 220 and its peripheral circuits, which will be described.
[0012]
In this embodiment, as the three-port video memory 310, for example, CXK 1206 manufactured by Sony Corporation or MB81C1501 manufactured by Fujitsu Limited is used. Here, description will be made using only the write port of the three-port video memory 310. Regarding the write port of the three-port video memory 310, a characteristic timing chart is described from page 21 to page 26 of the data sheet 72115-ST manufactured by Sony Corporation. The three-port video memory 310 has a configuration of 960 rows (COLUMN) × 306 columns (ROW) × 4 bits, which are provided for R, G, and B, respectively. Therefore, it is possible to store data obtained by quantizing one effective horizontal scanning period by 960 × 3.
[0013]
The access to the 3-port video memory 310 is performed in units of rows by blocks and columns by lines. In the 3-port video memory 310, DIN0 to DIN3 are data input terminals for inputting digital RGB signals, ADD0 to ADD3 are address input terminals, CKW0 is a port 0 shift signal terminal, INC0 is a port 0 line increment terminal, and HCLR0 is a port 0 horizontal. A clear terminal, VCLR0 is a port 0 vertical clear terminal, and WE (negative logic) is a port 0 write enable signal terminal. R, G, and B of the digital RGB signals are, for example, 4-bit signals.
[0014]
3, reference numeral 140 denotes an input video signal circuit for extracting and outputting a horizontal synchronizing signal HSTV, a vertical synchronizing signal VSTV, and an analog RGB signal from an analog video signal, and 221 denotes a horizontal writing dot clock signal HWDCK and a basic synchronizing signal. A horizontal write dot clock generating circuit for outputting BSYNC is shown, 222 is a horizontal write start counter for outputting a horizontal write start signal HWS and a HCLR0 signal, and 223 is a horizontal write for outputting a horizontal write count signal HWT. 3 shows a number counter. Reference numeral 224 denotes a vertical write line clock generation circuit that outputs a vertical write line clock signal VWLCK, 225 denotes a vertical write start counter that outputs a vertical write start signal VWS, and 226 denotes the number of vertical write operations. Reference numeral 227 denotes a vertical writing offset counter for outputting a signal VWT, and 227 denotes a vertical writing offset signal VWOFT for designating a vertical writing start position of the 3-port video memory 310 and a vertical writing offset for outputting a port 0 line increment INC0. Shows a counter. The OR circuit 228 outputs one of the vertical write line clock signal VWLCK and the vertical write offset signal VWOFT as the port 0 line increment signal INC0. The AND circuit 229 outputs the horizontal write dot clock signal HWDCK and the horizontal write dot clock signal HWDCK. A logical product of a write start signal HWS, an inverted output of the horizontal write count signal HWT, an inverted output of the vertical write start signal VWS and an inverted output of the vertical write count signal VWT, and outputs a write enable signal WENBL. , NOR circuit 230 performs an OR-NOT logical operation of the vertical synchronizing signal VSTV, HCLR0 signal, the output signal of the OR circuit 228 and the write enable signal WENBL output by the AND circuit 229, and outputs a port write enable signal WE. is there.
[0015]
The horizontal synchronizing signal HSTV extracted by the input video signal circuit 140 is supplied to a horizontal write dot clock generation circuit 221, a horizontal write start counter 222, a horizontal write number counter 223, and a vertical write start counter 225. The vertical synchronizing signal VSTV similarly extracted by the input video signal circuit 140 is used for a vertical write line clock generation circuit 224, a vertical write start counter 225, a vertical write number counter 226, a vertical write offset counter 227, and a 3-port video. It is provided to the port vertical clear terminal VCLR0 of the memory 310 and the NOR circuit 230.
[0016]
The ADC 210 digitally converts the horizontal write dot clock signal HWDCK provided as the clock signal CKAD into an analog RGB signal LSTV as a sampling timing, and outputs the digitally converted RGB signal LSTV to the three-port video memory 310. The horizontal writing dot clock generation circuit 221 generates a horizontal writing dot clock signal HWDCK synchronized with the horizontal synchronizing signal HSTV at a frequency designated by the CPU 620. The horizontal write dot clock signal HWDCK is supplied to the ADC 210 as a clock signal CKAD, and is also sent to the horizontal write start counter 222, horizontal write number counter 223, and AND circuit 229. The address preset is performed in the 3-port video memory 310 in an appropriate block unit. Here, when the block unit of the address preset of the 3-port video memory 310 is 60 dots, and one effective horizontal scanning period of the analog video signal is 64 (μs), the horizontal write dot clock generation circuit 221 generates the horizontal data. The frequency of the write dot clock signal HWDCK is
(Blanking period + effective image period / effective image period) ratio = 1.2
Then
1.2 × 60 (dot) / 64 · 10^-6(S) = 1.13 (MHZ)
become. For this reason, the horizontal writing dot clock signal HWDCK quantizes the analog RGB signal in one effective horizontal scanning period into 60 × 3 dots. Actually, the 3-port video memory 310 is configured to store data of one effective horizontal scanning period by 960 dots (16 blocks), so that 60 dots is one block for each of the digital R, G, and B signals. Up to 16 blocks can be used as
1.13 (MHZ) x 16 (block) = 18 (MHZ)
Horizontal writingIncludingThe digital RGB signal for one effective horizontal scanning period can be written in block units by the clock signal HWDCK.
[0017]
As described above, the horizontal writing dot clock generation circuit 221 has a horizontal writing dot clock having a frequency based on the value of the address preset block unit (60 dots) of the 3-port video memory 310 and the number of blocks to be used (1 to 16). The signal HWDCK is output. The value of the number of blocks to be used is set by the CPU 620 in the personal computer.
[0018]
The horizontal write dot clock generation circuit 221 is used as a clock for the port shift signal terminal CKW0 of the 3-port video memory 310 (a signal for enabling horizontal writing of the 3-port video memory 310 and incrementing the write address in dot units). Generate the basic synchronization signal BSYNC to be used. Here, considering the clock signal CKAD and the basic synchronization signal BSYNC, the cycle of the clock signal CKAD for converting an analog RGB signal into a digital signal is synchronized with the basic synchronization signal BSYNC, and the horizontal write enable control of the three-port video memory 310 is performed. And increment control is performed in dot units.
[0019]
The basic synchronization signal BSYNC generated by the horizontal write dot clock generation circuit 221 is used as a signal for basic synchronization with each control circuit, and is used as a horizontal write start counter 222, a horizontal write number counter 223, and a vertical write number counter 223. The write line clock generation circuit 224, the vertical write start counter 225, the vertical write number counter 226, the vertical write offset counter 227, and the 3-port video memory 310 are provided. Further, the vertical write line clock generation circuit 224 synchronizes with the vertical synchronization signal VSTV, generates a vertical write line clock signal VWLCK having a frequency N times the frequency of the vertical synchronization signal VSTV, and generates a vertical write number counter 226 and an OR. Send to circuit 228. The value of N times is set by the CPU 620 in the personal computer. The value of N is determined based on an aspect ratio suitable for the horizontal writing dot clock generation circuit 221.
[0020]
The horizontal writing start counter 222 is reset by the horizontal synchronizing signal HSTV, counts the number of clocks of the horizontal writing dot clock signal HWDCK specified by the CPU 620, and is specified by the CPU 620 during the effective horizontal scanning period of the analog video signal. The horizontal write start signal HWS for permitting the quantization is transmitted from the dot position. When horizontal writing start signal HWS is applied, horizontal writing start counter 222 sends port 0 horizontal clear signal HCLR0 to 3-port video memory 310 for one clock.
[0021]
Further, the horizontal writing counter 223 is reset by the horizontal synchronizing signal HSTV, and when a horizontal writing start signal HWS is supplied, counting of the clock of the horizontal writing dot clock signal HWDCK is started, and the effective horizontal scanning of the analog video signal is performed. The horizontal writing frequency signal HWT for permitting the quantization of the analog RGB signal is transmitted only during the clock designated by the CPU 620 during the period. Therefore, the horizontal writing counter 223 controls the effective horizontal scanning period, and it is possible to select up to which portion of the image in the horizontal direction the image is valid.
[0022]
The vertical writing start counter 225 is reset by the vertical synchronization signal VSTV, counts the number of clocks of the horizontal synchronization signal HSTV, and starts the effective horizontal scanning from the line position designated by the CPU 620 during the vertical effective scanning period of the video signal VSTV. Is output to the AND circuit 229 and the vertical writing number counter 226, which permits the quantization of the analog RGB signal of FIG. Therefore, the vertical writing counter 226 is reset by the vertical synchronizing signal VSTV, and when the vertical writing start signal VWS is applied, starts counting the clock of the vertical writing line clock signal VWLCK, and performs the vertical effective scanning of the analog video signal. The vertical writing frequency signal VWT for permitting the quantization of the analog RGB signal is transmitted only between the lines designated by the CPU 620 during the period. Therefore, the vertical effective scanning period is controlled by the vertical writing number counter 226, and it is determined to which line portion the image is valid in the vertical direction.
[0023]
The write position in the horizontal direction on the display screen of the 3-port video memory 310, that is, the write position in the COLUMN direction is determined by the CPU 620 in the address preset mode, using 60 × 3 bits of the quantized digital RGB signal as one block. Specify by block. At this time, the block is specified in 16 steps by the address input signals ADD0 to ADD3. That is, the address input signals ADD0 to ADD3 are set by the CPU 620. The vertical writing position on the display screen of the 3-port video memory 310 is set by a vertical writing offset counter 227. That is, the vertical write offset counter 227 is reset by the vertical synchronization signal VSTB, and the vertical write offset signal VWOFT and the line increment signal for offsetting the vertical write position of the 3-port video memory 310 while synchronizing with the basic synchronization signal BSYNC. INC0 transmits clocks of the number of lines specified by the CPU 620, and controls the vertical writing position of the 3-port video memory 310.
[0024]
Next, operations of the digitizing control units 221 to 230 and their peripheral circuits shown in FIG. 3 will be described with reference to the timing chart of FIG.
[0025]
(1) First, when the vertical synchronization signal VSTV becomes high level “H” (see FIG. 4A), the vertical write start counter 225, the vertical write number counter 226 and the vertical write offset counter 227 are reset, The vertical write start signal VWS and the vertical write count signal VWT become low level “L” (see FIGS. 4D and 4E). (2) The vertical write offset counter 227 creates a vertical write offset signal VWOFT from the basic synchronization signal BSYNC and outputs two clocks of the vertical write offset signal VWOFT (see FIG. 4 (h)). The vertical write offset signal VWOFT is applied to the port 0 line increment signal terminal INC0 of the 3-port video memory 310 via the OR circuit 228, and the vertical address of the 3-port video memory 310 is incremented twice. , And the horizontal line in the 3-port video memory 310 from which writing is started is offset.
[0026]
(3) On the other hand, when the clock number of the horizontal synchronizing signal HSTV reaches the number specified by the CPU 620, the vertical writing start counter 225 sets the vertical writing start signal VWS to the high level “H” and sets the quantum of the vertical effective scanning period. (See FIG. 4D). Thereby, it is possible to control which horizontal line of the screen based on the analog video signal is valid.
[0027]
(4) In the three-port video memory 310 that has obtained the clock of the vertical write offset signal VWOFT, the vertical write address is offset by the operation (2), and the horizontal synchronizing signal HSTV becomes high level “H” (FIG. 4 (j)), the horizontal write start counter 222 and the horizontal write number counter 223 are reset, and the horizontal write start signal HWS and the horizontal write number signal HWT are set to low level "L" (FIG. n) and (o)). The horizontal write dot clock generation circuit 221 outputs a horizontal write dot clock signal HWDCK (see FIG. 4 (m)). The ADC 210 that has received the horizontal write dot clock signal HWDCK operates with the horizontal write dot clock signal HWDCK as a sampling hold signal and a data latch signal, and samples analog RGB.
[0028]
The horizontal writing start counter 222 counts the number of clocks of the horizontal writing dot clock signal HWDCK, and when the counted value reaches the number specified by the CPU 620, sets the horizontal writing start signal HWS to a high level “H”. Then, quantization in the effective horizontal scanning period is permitted (see FIG. 4 (n)). At the same time, the horizontal write start counter 222 outputs one clock to the port 0 horizontal clear signal HCLR0 of the three-port video memory 310 to prepare for writing.
[0029]
At this time, the AND circuit 229 creates a logical product condition of the horizontal write start signal HWS at the high level “H” and the vertical write frequency signal VWT at the low level “L” which is inverted and input, and generates the horizontal write dot clock signal. HWDCK is sent to the NOR circuit 230 as the write enable signal WENBL. Further, the NOR circuit 230 outputs the port 0 horizontal clear signal HCLR0 of high level “H”, the vertical synchronization signal VSTV of high level “H”, the vertical write offset signal VWOFT or the vertical write line clock signal VWLCK of high level “H”. A logical operation of the NOT-OR condition of the write enable signal WENBL and the write enable signal WENBL are sent to the write 0 enable signal terminal of the 3-port video memory 310 as a write enable signal WE.
[0030]
The 3-port video memory 310 receives the write enable signal WE and becomes writable, and the digital RGB signal output from the ADC 210 is written. At the same time, the horizontal writing number counter 223 counts the number of clocks of the horizontal writing dot clock signal HWDCK, and permits writing of the luminance signal LSTV until the count value reaches the number specified by the CPU 620. Then, when the count value reaches the designated number, the horizontal writing number counter 223 sets the horizontal writing number signal HWT to the high level “H” to inhibit writing (see FIG. 4 (o)).
[0031]
Thus, while the digital RGB signal LSTV is being written, until the vertical write line clock generation circuit 224 outputs the vertical write line clock signal VWLCK, the same vertical line address is used in the horizontal direction. Is written. When the vertical write line clock generation circuit 224 sends the vertical write line clock signal VWLCK as the port 0 line increment INC0 signal of the three-port video memory 310, the vertical write line address of the three-port video memory 310 is changed. Go "1".
[0032]
As described above, when the writing in the vertical direction proceeds and the clock number of the vertical writing line clock signal VWLCK output from the vertical writing line clock generation circuit 224 reaches the number of lines specified by the CPU 620, the vertical writing number counter 226 sets the vertical write count signal VWT to a high level “H”, and stops writing to the 3-port video memory 310 during the vertical effective scanning period (see FIG. 4E). This stop of writing continues until the next vertical synchronizing signal VSTV becomes high level “H”.
[0033]
As described above, in the present embodiment, the vertical write line clock generation circuit 224 and the horizontal write dot clock generation circuit 221 are changed to arbitrary frequencies by the CPU 620 in response to a simple signal flow, and the ADC 210 and the 3-port video are used. By controlling the control signal output to the memory 310, the input video signal 140 can be written to the three-port video memory 310 at an arbitrary reduced size without using the CPU 620 at all times.
[0034]
In the above operation, the high level “H” is set to the active logic, but the same applies to the low level “L” set to the active logic.
[0035]
With the image processing apparatus of the present embodiment, the CPU 620 in the personal computer can easily operate any resolution, any aspect ratio, window display of any area, and a multi-strobe still image video technique of the analog video signal.
[0036]
Next, the operation when the CPU 620 in the personal computer writes video data directly to the three-port video memory 310 will be described with reference to FIG.
[0037]
Under the control of the CPU 620, the digital RGB video signal from the ADC 210 is stored in the video memory 310 via the video switch 311, and at the same time, the digital RGB video signal is output from the ADC 211 under the control of the video compression / decompression controller 320. The signal enters the signal compression circuit unit 330, is subjected to data compression, and is stored in the storage medium 720.
[0038]
At the time of video reproduction, the video switch 311 and the reproduction switch 312 are switched to 2 and 4, respectively, in conjunction with each other, video is expanded via the video signal expansion circuit unit 340 and stored in the video memory 310, and the display enlargement / reduction control unit The video signal VVS3 from the DAC 410 and the video signal VVS2 from the display signal generator 730 are superimposed by controlling the enlargement / reduction of the display by the control of 420, and the video signals to be video switch units 510 to 505 are displayed. Is sent to the monitor unit 101. That is, the display enlargement / reduction control unit 420 sends the clock signal HDCK and the horizontal read dot clock signal HDDA to the 3-port video memory 310 and the DAC 410 based on the conditions controlled by the CPU 620. The digital RGB signal LSMEM read from the three-port video memory 310 is converted into a video signal VVS3 and transmitted to the video switch 510. The video switch 510 is switching-controlled based on the output signal VSEL of the display enlargement / reduction control unit 420, superimposes the video signal VVS3 output from the DAC 410 on the video signal VVS2 coming from the color signal input terminal 506, and outputs the color signal. Output from terminal 505.
[0039]
Here, circuits relating to superimposition and mixing will be described in detail. FIG. 5 is a block circuit diagram of the display enlargement / reduction control unit 420 shown in FIG. 2 and its peripheral circuits. In the three-port video memory 310 shown here, a read port among the three input / output ports is used. On pages 27 to 31 of data sheet number 71125-ST of CXK 1206 manufactured by Sony Corporation, a timing chart related to the above-mentioned read port is described. The port used is read port 1 of the second page of the data sheet.
[0040]
In the 3-port video memory 310, the memory drive clock signal HDCK is applied to the port 1 shift signal terminal CKR1, the memory vertical / horizontal reset signal MRST is applied to the port 1 vertical clear terminal VCLR1, and the horizontal reset signal HRST is applied to the port 1 horizontal clear terminal HCLR1. , The vertical offset signal VROFT or the vertical line clock signal VRLCK is supplied to the port 1 line increment terminal INC1, and the port 1 output enable RE1 (negative logic) is supplied to the port 1 output enable terminal RE1 (negative logic). Further, the analog RGB signals LSMEM (one data in each of R, G, and B) is read from the port 1 data outputs DO10 to DO13.
[0041]
An analog RGB signal read-controlled by a port 1 shift signal CKR1, a port 1 vertical clear VCLR1, a port 1 horizontal clear signal HCLR1, a port 1 line increment signal INC1, and a port 1 output enable RE1 (negative logic) corresponding to each of the above terminals. The LSMEM is output from the port 1 data outputs DO10 to DO13, for example, with 4 bits for each of R, G, and B.
[0042]
The video switch 510 in FIG. 5 outputs the input of the A terminal or the B terminal from the common terminal C in response to the switching signal VSEL input to the switching signal input terminal CNT. Specifically, when the switching signal VSEL is at the high level “H”, the input to the B terminal is output, and when the switching signal VSEL is at the low level “L”, the input to the A terminal is output from the C terminal. The illustrated CPU 620 controls each unit via a CPU bus 610 in the personal computer. Reference numeral 421 denotes a horizontal reference read dot clock generator that outputs a horizontal reference read dot clock signal HBDCK, 422 denotes a horizontal read start counter that outputs a horizontal read start signal HRSA and a horizontal read direction reset signal HRST, and 423 denotes a horizontal read start counter. A horizontal 64 clock counter for outputting a horizontal reference start signal HRSB is shown, 424 is a horizontal read number counter for outputting a horizontal read number signal HRT, 425 is a horizontal read dot clock generator for outputting a horizontal read dot clock signal HDDA. Show. The memory vertical read offset counter 426 outputs a vertical read offset signal VROFT that determines an offset line of a vertical read line of the three-port video memory 310 with a count synchronized with the horizontal reference read dot clock generator 421. . The vertical blanking number counter 427 outputs a vertical blanking end signal VBE, the vertical reading start counter 428 outputs a vertical reading start signal VRS, the vertical reading number counter 429 outputs a vertical reading number signal VRT, and a vertical reading line. Clock generator 430 outputs vertical read line clock signal VRLCK. An AND circuit 431 outputs a signal VSEL for superimposing, an OR circuit 432 outputs a vertical read offset signal VROFT and a vertical read line increment signal VRLCK as a port 1 line increment signal INC1, and a NOR circuit 433 outputs a read enable RE1 signal. Is output. Reference numerals 434 and 435 denote tristate circuits, and reference numeral 436 denotes an inverter circuit.
[0043]
The video signal VVS2 coming from the color input terminal 506 is given to the A terminal of the video switch 510. The horizontal synchronizing signal HSPC coming from the synchronizing terminal 507 forming the horizontal synchronizing signal of the input terminal 506 includes a horizontal reference reading dot clock generator 421, a horizontal reading start counter 422, a horizontal 64 clock counter 423, a horizontal reading counter 424, and a vertical bus. The vertical synchronization signal VSPC is supplied to a ranking number counter 427, a vertical reading start counter 428, a vertical reading number counter 429, a vertical reading line clock generator 430, and a three-port video memory 310, a vertical reading offset counter 426, and a vertical blanking. The number is supplied to a number counter 427, a vertical read start counter 428, a vertical read number counter 429, and a vertical read line clock generator 430, and is sent to synchronization signal terminals 490 and 491, respectively.
[0044]
Here, input / output of the horizontal synchronization signal HSPC and the vertical synchronization signal VSPC will be described with reference to FIG.
[0045]
The horizontal synchronizing signal HSPC and the vertical synchronizing signal VSPC are supplied via buffers 62 and 61 to the synchronizing signal terminals 490 and 491 and the necessary circuits shown in FIG. These buffers 61 and 62 are impedanceySIt has functions such as conversion and waveform shaping, and contributes to accurate transmission of the synchronization signal even when image processing devices are cascaded. The horizontal synchronizing signal HSPC is applied to the PLL circuit 63 in the horizontal reference read dot clock generator 421, and a horizontal reference read dot clock HBDCK is generated as the frequency of the horizontal resolution of the entire horizontal screen designated by the CPU 620.
[0046]
The PLL circuit 63 is configured as shown in FIG. That is, the horizontal synchronizing signal HSPC is supplied from the signal line 70 to the phase comparator 71, and the output of the N frequency divider 74 is supplied to the phase comparator 71. The phase comparator 71 compares the phases of these signals. And outputs a signal having a pulse width corresponding to the phase difference. The output of the phase comparator 71 is applied to a low-pass filter LPF72, smoothed, and applied to a voltage controlled oscillator VCO73. The VCO 73 oscillates at a frequency corresponding to the applied voltage, and this is sent to each unit as a horizontal reference read dot clock HBDCK. The VCO 73 is also applied to the N frequency divider 74 to divide the frequency to the frequency of the horizontal synchronization signal HSPC. And returned to the phase comparator 71. As a result, a horizontal reference read dot clock HBDCK synchronized with the horizontal synchronization signal HSPC is generated.
[0047]
The horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read circuit counter 424 in the display enlargement / reduction control unit 420 in FIG. 5 have their count values reset by the horizontal synchronization signal HSPC. Further, the vertical synchronizing signal VSPC arriving from the synchronizing terminal 508 includes a port 1 vertical clear VCLR1 of the 3-port video memory 310, a NOR circuit 433, a vertical reading offset counter 426, a vertical blanking number counter 427, a vertical reading start counter 428, and a vertical reading start counter 428. It is sent to the read number counter 429, the vertical read line clock generator 430, and the synchronization terminal 491. The count values of the vertical read offset counter 426, the vertical blanking number counter 427, the vertical read start counter 428, and the vertical read number counter 429 are reset by the vertical synchronization signal VSPC.
[0048]
Further, the signal HBDCK generated by the horizontal reference read dot clock generator 421 is supplied to a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read number counter 424, and a vertical read offset counter 426, and a tristate circuit 435. Is transmitted to the port 1 shift signal terminal CKR1 of the three-port video memory 310 as the clock signal HDCK of the three-port video memory 310 via the.
[0049]
The horizontal read dot clock generator 425 is configured by a PLL circuit that outputs a signal having a frequency N1 times the frequency of the horizontal synchronizing signal HSPC based on the horizontal read start signal HRSB from the horizontal 64 clock counter 423. , And outputs a horizontal read dot clock signal HDDA. The horizontal read dot clock signal HDDA generated by the horizontal read dot clock generator 425 is used as a clock signal HDCK for the three-port video memory 310 via the tri-state circuit 434 as the port 1 shift signal terminal CKR1 and the port 1 shift signal terminal CKR1 of the three-port video memory 310. It is provided to the DAC 410 and used as a read clock signal for the digital RGB signal LSMEM and a conversion clock signal for the DAC 410.
[0050]
Further, the vertical read line clock generator 430 includes a PLL circuit which synchronizes with the vertical synchronization signal VSPC and outputs a signal having a frequency of N2 times the frequency of the vertical synchronization signal VSPC, and outputs the vertical read line clock signal VRLCK. I do. The vertical read line clock signal VRLCK generated by the vertical read line clock generator 430 is supplied to a port 1 line increment terminal INC1 which advances a line address which is a vertical address of the 3-port video memory 310 via an OR circuit 432. At the same time, it is applied to the port 1 output enable RE1 terminal (negative logic) via the OR circuit 432 and the NOR circuit 433.
[0051]
The display enlargement / reduction control unit 420 obtains basic timing by using the horizontal reference read dot clock signal HBDCK, the horizontal read dot clock signal HDDA, and the vertical read line clock signal VRLCK.
[0052]
The vertical read offset counter 426 is output from the horizontal reference read dot clock generator 421 after the count value is reset by the vertical synchronization signal VSPC in order to determine the start offset line position of the read line of the 3-port video memory 310. In synchronization with the horizontal reference read dot clock signal HBDCK, a vertical offset signal VROFT that advances the vertical line address of the 3-port video memory 310 is sent to the OR circuit 432.
[0053]
Further, the vertical blanking number counter 427 has a counter (not shown) for deleting the vertical back porch area of the video signal VVS2. This counter counts the number of clocks of the horizontal synchronizing signal HSPC, and outputs a vertical blanking end signal VBE to the vertical read start counter 428 after passing the vertical back porch area. The vertical read start counter 428 receives the permission signal (vertical blanking end signal VBE) sent from the vertical blanking number counter 427, counts the number of clocks of the horizontal synchronizing signal HSPC, and outputs the vertical direction from the 3-port video memory 310. Is output to the VRS vertical read number counter 429. The vertical reading counter 429 receives the permission signal (control signal VRS) sent from the vertical reading start counter 428, counts the number of clocks of the horizontal synchronizing signal HSPC, and sets the period of reading from the three-port video memory 310 in the vertical direction. The signal, that is, the vertical read count signal VRT, is output to the AND circuit 431.
[0054]
Then, the vertical reading offset counter 426, the vertical blanking number counter 427, the vertical reading start counter 428, the vertical reading number counter 429, and the vertical reading line clock generator 430 described above read the three-port video memory 310 in the vertical direction. Control is performed.
[0055]
The number of clocks of the horizontal reference read dot clock signal HBDCK counted by the vertical read offset counter 426, the number of clocks of the horizontal sync signal HSPC counted by the vertical blanking number counter 427, and the horizontal sync signal HSPC counted by the vertical read start counter 428 The number of clocks of the horizontal synchronization signal HSPC counted by the vertical reading number counter 429 and the value of the N divider in the PLL circuit in the vertical reading line clock generator 430 are required by the CPU 620 in the personal computer, respectively. Set the value.
[0056]
On the other hand, the horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421, and outputs a read start permission signal (horizontal read) for the 3-port video memory 310 in the horizontal direction. A start signal HRSA) is sent to the horizontal 64 clock counter 423. The horizontal 64 clock counter 423 receives the permission signal (horizontal read start signal HRSA) sent from the horizontal read start counter 422, and receives the clock number of the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421. Count. Then, when the count value reaches 64 clocks, which is a characteristic at the time of reading of the three-port video memory 310, the horizontal read start signal HRSB is output to the horizontal read dot clock generator 425, the horizontal read number counter 424, and the AND circuit 431. The horizontal read number counter 424 counts the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421, and outputs a read period enable signal (horizontal read number) of the 3-port video memory 310 in the horizontal direction. Signal HRT) to the AND circuit 431.
[0057]
Thus, the horizontal read control for the three-port video memory 310 is performed by the horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read number counter 424. The value of the frequency divider in the horizontal reference read dot clock generator and the frequency divider in the PLL circuit in the horizontal read dot clock generator, the number of clocks of the horizontal reference read dot clock signal HBDCK counted by the horizontal read start counter 422, and the horizontal read The number of clocks of the reference dot clock signal HBDCK counted by the number counter 424 is set to a required value by the CPU 620 in the personal computer.
[0058]
Next, the operation of the display enlargement / reduction control unit 420 will be described with reference to FIGS. 8, 9, 10, and 11. 8 is a timing chart of vertical read permission of the 3-port video memory 310, FIG. 9 is a timing chart of vertical offset of the 3-port video memory 310, and FIG. FIG. 11 is a timing chart of horizontal reading of the three-port video memory 310.
[0059]
First, the horizontal read permission of the three-port video memory 310 will be described with reference to FIG. When the vertical synchronizing signal VSPC becomes high level “H” (see FIG. 8A), the vertical blanking number counter 427, the vertical reading start counter 428, and the vertical reading number counter 429 are reset, and the vertical blanking end signal VBE, The vertical read start signal VRS and the vertical read count signal VRT each become low level “L” (see FIGS. 8D, 8E, and 8F), and the vertical blanking number counter 427 outputs the clock of the vertical synchronization signal HSPC. The number is counted, and after passing the vertical back porch area, the vertical blanking end signal VBE is set to the high level “H” (see FIG. 8D). When the vertical blanking end signal VBE becomes high level “H”, the vertical read start counter 428 starts counting the number of clocks of the horizontal synchronization signal HSPC. Then, when the vertical read start counter 428 counts the value set by the CPU 620, the vertical read start signal VRS is set to the high level “H” (see FIG. 8E). When the vertical read start signal VRS becomes ゛ high level “H”, the start of reading of the digital RGB signal LSMEM in the vertical direction of the 3-port video memory 310 is permitted. The counting of the number of clocks of the horizontal synchronization signal HSPC is started. When the vertical reading number counter 429 counts the value set by the CPU 620, the vertical reading number signal VRT is set to the high level “H” (see FIG. 8F).
[0060]
For this reason, when the horizontal read start signal HRSB is at the high level “H” and the horizontal read count signal HRT is at the low level “L”, the horizontal read start signal VRS is ゛ high level “H” and the vertical read count signal is Only during the period when VRT is at the low level “L”, the condition is satisfied in the vertical direction in which the high-level “H” superimposing signal VSEL is output from the AND circuit 431. Therefore, in the 3-port video memory 310, the digital RGB signal LSMEM is read based on the horizontal read permission during this time.
[0061]
Next, the vertical offset of the three-port video memory 310 will be described with reference to FIG. When the vertical synchronization signal VSPC becomes high level “H” (see FIG. 9A), the vertical read offset counter 426 is reset and starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK. While the vertical read offset counter 426 counts the value set by the CPU 620, it supplies the vertical read offset signal VROFT to the port 1 line increment INC1 of the 3-port video memory 310 via the OR circuit 432 (see FIG. 9C). Offset the read address value of the 3-port video memory 310 in the vertical direction.
[0062]
At this time, since the vertical synchronizing signal VSPC and the vertical read offset signal VROFT are supplied to the NOR circuit 433, the read enable signal RE1 (negative logic) is supplied to the read enable terminal RE1 (negative logic) of the 3-port video memory 310. When the value set by the CPU 620 is counted, a vertical offset is performed, so that the vertical read offset counter 426 stops outputting the vertical read offset signal VROFT until the next vertical synchronization signal VSPC arrives.
[0063]
Next, the horizontal read permission of the three-port video memory 310 will be described with reference to FIG. When the horizontal synchronizing signal HSPC is output, the horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read number counter 424 are reset, and the horizontal read start signal HRSA, the horizontal read start signal HRSB, and the horizontal read number signal HRT are low. The level becomes "L" (see FIGS. 10C, 10D, and 10E). Therefore, the horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421, and when the count value reaches the value set in the CPU 620, the horizontal read start signal HRSA To a high level "H" (see FIG. 10C). When the horizontal read start signal HRSA becomes high level “H”, the horizontal 64 clock counter 423 starts counting the number of clocks of the reference read dot clock signal HBDCK, and when the count value becomes 64, the horizontal read start signal HRSB becomes high. The level is set to “H” (see FIG. 10D). Then, the horizontal read dot clock generator 425 is phase-locked to the horizontal read start signal HRSB. Note that the horizontal 64 clock counter 423 generates a high level “H” of the horizontal read start signal HRSB at a count value of “64” due to the characteristics of the 3-port video memory 310, and is not limited to 64.
[0064]
When the horizontal read start signal HRSB becomes high level "H", it means that horizontal reading of the 3-port video memory 310 has been permitted, and the horizontal read counter 424 counts the number of clocks of the horizontal reference read dot clock signal HBDCK. The counting is started, and when the count value reaches the value set by the CPU 620, the horizontal reading frequency signal HRT is set to the high level “H” (see FIG. 10E).
[0065]
When the vertical read start signal VRS is at the high level “H” and the vertical read count signal VRT is at the low level “L”, the horizontal read start signal HRSB is at the high level “H” and the horizontal read count signal HRT is at the low level. Only during the period of the level “L”, the AND circuit 431 receiving the horizontal read count signal HRT outputs a high-level “H” superimpose enable signal VSEL. Therefore, in the 3-port video memory 310, the digital RGB signal LSMEM is read based on the vertical read permission during this time.
[0066]
Next, the horizontal reading of the three-port video memory 310 will be described with reference to FIG. 11. The superimposing signal VSEL becomes high level "H" (see FIG. 11C), and the horizontal reading dot clock is generated. The digital signal LSMEM from the three-port video memory 310 and the analog conversion of the DAC 410 are performed based on the clock of the horizontal read dot clock signal HDDA output from the device 425 (see FIG. 11B). The read enable signal RE1 at this time is also shown (see FIG. 11D).
[0067]
On the other hand, as described above, the video signal VVS2 is input to the point A of the video switch 510, and the video signal VVS3 read out from the three-port video memory 310 and converted into an analog signal by the DAC 410 is input to the point B of the video switch 510. Have been. Therefore, when the video switch 510 is switched by the signal VSEL to be superimposed, the video signal VVS4 output from the video switch 510 becomes the video signal VVS3 whose phase has been corrected to the video signal VVS2 in the image corresponding to the video signal VVS2. Is output as a video signal VVS4 corresponding to the superimposed image. In addition to the output of the video signal VVS4, the horizontal synchronizing signal HSPC and the vertical synchronizing signal VSPC are also output to the output terminals 505, 490, and 491.
[0068]
Note that the above-described timing chart is an example, and the above-described operation can be performed even when each signal is positive logic or negative logic.
[0069]
In FIG. 5, when a signal VSEL for superimposing a high level “H” is output to the tri-state circuit 434 via the NOT circuit 436, the tri-state circuit 434 operates to output the horizontal read dot. Clock signal HDDA is transmitted as drive clock signal HDCK. Conversely, when the signal VSEL to be superimposed is at the low level “L”, the tristate circuit 435 operates, and the horizontal reference read dot clock signal HBDCK is supplied to the three-port video memory 310 as the drive clock signal HDCK. I have.
[0070]
That is, when superimposing is performed with the signal VSEL to be superimposed being at the high level “H”, the 3-port video memory 310 is accessed by the horizontal read dot clock HDDA output from the horizontal read dot clock generator 425, Reading of the digital RGB signal LSMEM is performed at a speed sufficient for superimposing. On the other hand, when the superimpose signal VSEL is low level “L” and superimpose is not performed, the 3-port video memory 310 is accessed by the horizontal reference read dot clock HBDCK output from the horizontal reference read dot clock generator 421. Then, the address is advanced to the horizontal read offset point, and the digital RGB signals in the horizontal / vertical area where superimposition is not performed are skipped, so to speak, and the next superimposed signal VSEL becomes high. This is to prepare for the timing when the level becomes “H”.
[0071]
As described above, the position at which the video signal VVS is superimposed in the video signal VVS2 is the vertical read start signal VRS from the vertical read start counter 428 in the vertical direction, and the horizontal read start from the horizontal read start counter 422 in the horizontal direction. It is determined by the signal HRSA. The display size to be superimposed is determined by the vertical reading frequency signal VRT from the vertical reading frequency counter 429 in the vertical direction and by the horizontal reading frequency signal HRT from the horizontal reading frequency counter 424 in the horizontal direction.
[0072]
In order to cause the video signal VVS3 to be displayed in an enlarged or reduced scale, the vertical read line clock signal VRLCK of the vertical read line clock generator 430 in the vertical direction, and the horizontal read dot clock signal HDDA of the horizontal read dot clock generator 425 in the horizontal direction, respectively. When the frequency is lowered, the display can be enlarged, and when the frequency is increased, the display can be reduced.
[0073]
FIG. 12 shows an example in which a color signal is extracted as an RGB signal (VRGBY) from the video decoder unit 142 and the ADC 210, and a color signal is extracted as a YUV signal (VYUVY) from the video decoder unit 143 and the ADC 211. Even in such a case, it is realized by the IC chip MC44011 manufactured by Motorola, USA. In addition, since this IC chip has the video decoder unit and the ADC unit integrated, the environment is easy to use.
[0074]
FIG. 13 shows an embodiment in which digital data such as a liquid crystal display is used as an input signal of the display. A block corresponding to the DAC 410 is omitted, a signal LSMEM from the video memory 310 and a signal from the display signal generator 730. The video switching unit 510 superimposes the signal VVS2 and drives the display panel by a display control unit 810 such as an LCD panel.
[0075]
【The invention's effect】
According to the present invention, video data can be simultaneously compressed and written to a storage medium while the video data is displayed on the monitor unit 108.
[0076]
Claims 2 and 3 show special examples for specifically realizing the effect of claim 1.
[0077]
The fourth aspect has an effect that an operation of selectively displaying video signals of a plurality of streams or combining and displaying them on the same display body by superimposing becomes possible.
[0078]
According to a fifth aspect of the present invention, the data read from the CPU or the storage medium is used to monitor the recorded video data of the specified resolution by the display enlargement / reduction control unit 420 at any display size and display position regardless of the specified size. The present invention is an invention which is displayed on the display unit 101, and in which the present invention can provide an indispensable effect in the field of video processing compatible with multimedia.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram of the present invention.
FIG. 2 is a schematic block diagram of the present invention.
FIG. 3 is a configuration diagram showing a part of FIG. 2 of the present invention.
FIG. 4 is a timing chart of FIG. 3 of the present invention.
FIG. 5 is a block diagram showing another part of FIG. 2 of the present invention.
FIG. 6 is an explanatory diagram of a main part of a PLL oscillation circuit.
FIG. 7 is an explanatory diagram of a main part of a PLL oscillation circuit.
FIG. 8 is a time chart showing the operation of the main part.
FIG. 9 is a time chart showing the operation of the main part.
FIG. 10 is a time chart showing the operation of the main part.
FIG. 11 is a time chart showing the operation of the main part.
FIG. 12 is a time chart showing the operation of the main part.
FIG. 13 is a time chart showing the operation of the main part.
FIG. 14 is a configuration diagram of a conventional system.
[Explanation of symbols]
101: Monitor section
140: video signal input unit
141: Y / C separation unit
142: Video decoder unit
210, 211: AD converter section
220: digitizing control unit
310: Video memory unit
311: Video switch
312: Reproduction switch
320: compression / decompression control unit
330: Video code compression circuit section
340: Video code expansion circuit section
410: DA converter section
420: display enlargement / reduction control unit
510: Video switch section
610: CPUBUS
620: CPU
710: I / O control unit
720: Storage medium
730: display signal generator

Claims (1)

A processor for performing a logical operation;
A writing control unit that operates under the control of the processor, including a first analog-to-digital conversion unit that converts an input video signal into a first video signal; A write control unit that controls writing to a storage medium;
A read control unit that controls reading of a signal from the first storage medium to display the read signal;
A moving image recording / reproducing unit which operates under the control of the processor, comprising a second analog / digital conversion unit for converting the input video signal into uncompressed moving image data; a second and records in the storage medium, moving image recording and reproducing unit for reproducing the second video signal and decompresses the signal reproduced from said second storage medium Te,
With
The writing control unit further includes a video switching unit for switching between the first video signal and the second video signal,
The writing control unit controls the first analog-to-digital conversion unit and the first storage medium to reduce an image represented by the first video signal and write the reduced image to the first storage medium. A video recording / reproducing device having a function.

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