JPH01317081A - Scanning frequency converter - Google Patents

Abstract

PURPOSE:To display a video signal with a different scanning frequency for both horizontal and vertical directions on the screen by inhibiting the readout only when an address selector receives a synchronizing signal of the 2nd video signal. CONSTITUTION:When a synchronizing signal is inputted from a synchronizing separator circuit 4 to an address selector 7, the address selector 7 outputs a vertical line readout address to a memory 6 with priority and withdraws an output while storing the data from an A/D converter 1 to an FIFO memory 8. Then the memory 6 receiving the readout address reads out a data written in a corresponding address according to a horizontal picture element readout clock and a video signal is generated via a D/A converter 9. Thus, the video signal is displayed within the period of the horizontal synchronizing signal of the 2nd video signal and within the horizontal/vertical period designated in the period of the vertical synchronizing signal. Thus, the 1st video signal is displayed on the pattern of the 2nd video signal with a different scanning frequency.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a scanning frequency conversion device that converts video signals with different scanning frequencies into displayable screen data, and is capable of converting both horizontal and vertical scanning frequencies. The purpose is to incorporate an A/D converter that converts a first video signal into a digital signal, a circuit that separates horizontal and vertical synchronization signals of the first video signal, and a write pixel clock, and to convert the synchronization signal into a digital signal. a write address generation circuit that synchronizes the phase of the clock with the clock and generates horizontal and vertical write addresses respectively corresponding to designated horizontal and vertical write periods; and a second video signal having a scanning frequency different from that of the first video signal. A circuit for separating the synchronization signal of the second video signal and a readout pixel clock, which synchronizes the phase of the clock with the synchronization signal of the second video signal, and reads horizontal pixels corresponding to a specified horizontal/vertical display period. A read address generation circuit that generates a clock and a vertical line read address and provides the read clock to the two-bottom screen memory (6), and a read address generation circuit that generates a clock and a vertical line read address and provides the read clock to the two-bottom screen memory (6), and a synchronization signal of the first or second video signal to An address selector that selects one of the read addresses with priority and specifies the address of the memory, and an address selector that normally reads the data from the A/D converter to the memory as it is and selects one of the read addresses with priority, and the address selector selects one of the read addresses with priority and specifies the address of the memory. FIFO memory that prohibits reading only when a synchronization signal is received, and D/A that converts the screen memory signal into an analog signal.
It consists of a converter.

[Industrial application field]

The present invention relates to a scanning frequency conversion device, and more particularly to a scanning frequency conversion device that converts video signals having different scanning frequencies into displayable screen data.

With the recent diversification of visual devices, it has become necessary to display screen (image) data for one visual device in a manner compatible with various other visual devices.

[Conventional technology]

As a conventional device for converting display screens, there is one shown in Figure 10, which converts standard television signals (NTSC signals) into
A /D converter 101 converts it into a digital signal, and a switching switch 102 writes the digital signal alternately into one-line memories 103 and 104. In this write operation, the horizontal and vertical synchronization signals of the television signal are separated by the synchronization separation circuit 105, and the horizontal synchronization signal is directly used as the write clock (15,
75 KHz) to the memories 103 and 104. Also, the horizontal synchronization signal is the phase synchronization circuit 1
06, a read clock (31.5 KHz) twice the write frequency is generated and the memory 103.1
04 performs a read operation, and by alternately switching the selector switch 107, a high-resolution video signal having a scanning frequency different from that of the television signal is output from the D/A converter 108.

The display screen at this time is shown in Figure 11, and the horizontal scanning frequency of the television signal before scanning frequency conversion is 15.75.
KHz, and the horizontal scanning frequency of the video signal after conversion is 2
It is shown that the frequency is doubled to 31.5KHz.

Therefore, as shown in the time chart of FIG. 12, on the display screen after conversion, each horizontal line is displayed overlappingly twice.

[Problem to be solved by the invention]

The above conventional example has an image memory for one line, and by reading at twice the writing speed, only the horizontal scanning frequency is doubled.
The vertical scanning frequency was not converted.

As a result, the number of scanning lines is doubled, which has the advantage of being able to display fine grain on standard televisions.
There was a problem in that it could not handle high-resolution images such as those produced by personal computers, which have different vertical scanning frequencies as well as horizontal scanning frequencies.

Therefore, an object of the present invention is to realize a scanning frequency conversion device capable of converting both horizontal and vertical scanning frequencies.

[Means to solve the problem]

In order to achieve the above object, the scanning frequency conversion device according to the present invention includes an A/D converter 1 that converts a first video signal into a digital signal, as shown in principle in FIG.
It incorporates a circuit 2 for separating horizontal and vertical synchronization signals of the first video signal and a write pixel clock, synchronizes the phase of the clock with the synchronization signal, and corresponds to specified horizontal and vertical write periods, respectively. A write address generation circuit 3 that generates horizontal and vertical write addresses, a circuit 4 that separates a synchronization signal of a second video signal having a different scanning frequency from the first video signal, and a read pixel clock are built in. , phase synchronizes the clock with the synchronization signal of the second video signal, generates a horizontal pixel readout clock and a vertical line readout address corresponding to the specified horizontal and vertical display period, and outputs the readout clock to the 2-port screen memory 6. a read address generation circuit 5 for providing
an address selector 7 which selects one of the read addresses of both address generating circuits 3.5 with priority based on a synchronization signal of the first or second video signal and specifies the address of the memory 6; Normally, the data from the D converter 1 to the memory 6 is read out as is, and the address selector selects the second memory 6.
FI that prohibits reading only when it receives the synchronization signal of the video signal.
It includes an FO memory 8 and a D/A converter 9 that converts the signal of the screen memory into an analog signal.

[For production]

In the scanning frequency conversion device of the present invention, the horizontal and vertical synchronization signals of the first video signal are separated by the synchronization separation circuit 2 and then provided to the address selector 7 and the write address generation circuit 3.

The write address generation circuit 3 synchronizes the phase of the built-in write pixel clock with the horizontal and vertical synchronization signals and generates horizontal and vertical write addresses corresponding to the horizontal and vertical write periods specified from the outside, for example. do. When this write address is generated, the horizontal and vertical synchronizing signals of the first video signal are applied to the address selector 7, so that the address selector 7 provides the write address to the two-port screen memory 6. The first video signal is converted into a digital signal by the A/D converter 1 and then sent to the FIFO memory 8.
Normally, it is stored once and sent to the memory 6 after a certain period of time.
Written to the write address above.

As a result, the input screen is as shown in Figure 2(a).
within the period of the horizontal synchronizing signal (e.g., 640 dots) and the period U of the vertical synchronizing signal (e.g., 480 lines) of the video signal.
written within the specified horizontal and vertical period.

On the other hand, horizontal and vertical synchronizing signals of a second video signal having a scanning frequency different from that of the first video signal are separated by a synchronization separation circuit 4 and sent to an address selector 7 and a read address generation circuit 5. The read address generation circuit 5 synchronizes the phase of the built-in read pixel clock with the horizontal and vertical synchronization signals of the second video signal, and also generates horizontal pixel read clocks corresponding to the horizontal and vertical read periods specified from the outside, for example. and a vertical read address, and the horizontal pixel read clock is sent directly to the memory 6. When a read address is generated, the horizontal and vertical synchronizing signals of the second video signal are applied to the address selector 7, and thereby the address selector 7 provides the read address to the two-vote screen memory 6.

That is, when a synchronization signal is input from the synchronization separation circuit 4 to the address selector 7, the address selector 7 preferentially outputs the vertical line read address to the memory 6, and also outputs the vertical line read address from the A/D converter 1 to the FIFO memory 8. Prevent data from being output while it is being accumulated. After outputting the line address, the address selector 7 performs the above operation.

Upon receiving this read address, the memory 6 reads out the data written in the corresponding address in accordance with the horizontal pixel read clock, and generates a video signal via the D/A converter 9.

As a result, the display screen changes to the second
The video signal is displayed within a horizontal and vertical period specified within the period of the horizontal synchronizing signal (for example, 1024 dots) and within the period of the vertical synchronizing signal (for example, 768 lines).

In this way, as shown in FIG. 3, writing or reading is performed every time a synchronization signal is applied to the address selector 7, and the first video signal is converted into a second video signal having a different scanning frequency. can be displayed on the screen. In this example,
Two read horizontal synchronization signals are inserted between the write horizontal synchronization signals, so when data is written in one period of the write horizontal synchronization signal, two image data are left over, but the address selector 7 preferentially selects the read data, it is sufficient to store these two pieces of data in the FIFO memory 8.

〔Example〕

FIG. 4 shows an embodiment of the scanning frequency conversion device of the present invention shown in FIG. 1, and in this embodiment, one screen memory 6 is divided into four parts.

This is done in consideration of the slow writing speed of the memory 6, and in response to this, latch circuits 10 and 11 are provided.
Furthermore, the write/read timings of the launch circuits 10 and 11 are adjusted by a 4-frequency divider circuit 12.

However, if the memory 6 is very fast, one screen memory is sufficient, and a launch circuit and a divide-by-four circuit are not necessary. The write address generation circuit 3 also includes a write synchronization circuit 31 that inputs horizontal and vertical synchronization signals from the synchronization separation circuit 2, and horizontal and vertical synchronization signals that are phase-synchronized in this write synchronization circuit 31. , and a write counter 32 which receives a signal giving a specified period from the outside and generates a write horizontal/vertical address. Furthermore, the read address generation circuit 5 includes a read synchronization circuit 51 that inputs horizontal and vertical synchronization signals from the synchronization separation circuit 2, and a read synchronization circuit 51 that inputs horizontal and vertical synchronization signals that are phase-synchronized in this read synchronization circuit 51 and external signals. The reading counter 52 generates a horizontal pixel read clock and a vertical read line address in response to a signal giving a designated period.

These address generation circuits 3 and 5 are further connected to fifth address generation circuits 3 and 5, respectively.
This is shown in detail in FIG.

In FIG. 5, the write synchronization circuit 31 of the write address generation circuit 3 has a write pixel clock generation section 31a and a write pixel clock (which has a center frequency equal to the frequency of the pixel to be written and whose frequency is variable). It is composed of a counter 31b as a frequency dividing circuit (possibly locked), and a comparison circuit 31c that performs a phase comparison between the frequency divided output and the horizontal synchronizing signal of the synchronization separation circuit 2. Note that the vertical synchronization signal from the synchronization separation circuit 2 is passed through as is. The write counter 32 also receives a write dot clock from the write pixel clock generator 31a and a horizontal write period (
1 to 640 don't) AND gate 32a with specified signal
A horizontal address counter 32b counts the output clock of the AND gate 32a to generate a horizontal write address and is reset by a horizontal synchronization signal from the frequency divider circuit 31b, and a horizontal address counter 32b generates a horizontal write address by counting the output clock of the AND gate 32a. A vertical write line address is generated by counting the AND gate 32C with the write period (1 to 480 lines) designation signal and the output clock of this AND gate 32c, and is reset by the vertical synchronization signal from the synchronization separation circuit 2. It is composed of a counter 32d.

The readout synchronization circuit 51 of the readout address generation circuit 5 shown in FIG. 6 has the same configuration as that in FIG.
1a, a counter 51b, and a comparison circuit 51c, and the read counter 52 includes an AND gate 52a, an AND gate 52C, and a vertical address counter 52d.
It is made up of. The readout pixel clock has a center frequency equal to the frequency of the pixel to be readout, and is locked so that the frequency can be varied.The reason why the readout counter 52 is not provided with a counter corresponding to the horizontal address counter 32b is because of the memory 6. This is because only a vertical line address is sufficient for addressing during reading. However, since a clock is required to read out pixel data in each addressed line, a horizontal pixel readout clock is generated from the AND gate 52a. Further, it is assumed that the horizontal display period is specified as 201 to 840 lines), and the vertical display period is specified as 101 to 580 lines.

Next, the operation of the embodiment shown in FIG. 4 will be explained with reference to FIGS. 5 and 6. It is assumed here that a television signal (NTSC signal) is used as the first video signal, and a high-resolution personal computer video signal is used as the second video signal.

A television signal is converted into a digital signal by an A/D converter 1, temporarily stored in a FIFO memory 8, output, and latched by a latch circuit 10 for four pixels at a time.

On the other hand, the television signal is separated into horizontal and vertical synchronizing signals H and V by the synchronization separation circuit 2 and sent to the address selector 7 and the write synchronization circuit 31. As a result, the address selector 7 selects the horizontal and vertical addresses from the write address generation circuit 3 and applies them to the memory 6 unless a synchronization signal of the personal computer video signal is input as will be described later.

In this case, the horizontal and vertical addresses are generated by the write synchronization circuit 31 and the write counter 32 from the synchronization signal of the synchronously separated television signal.

That is, as shown in FIG.
A clock is generated at point a, and when the frequency dividing circuit 31b counts 640 clocks, a write horizontal synchronizing signal is generated and applied to the comparator circuit 31c. The comparator circuit 31c compares the phase of the written horizontal synchronizing signal with the horizontal synchronizing signal of the synchronously separated television signal, and uses the clock generator 31a, the frequency dividing circuit 31b, and the comparator circuit 31c to make the two match. It is controlled by a PLL circuit configured. This situation is shown in FIGS. 7(a) and 7(b).

In the write counter 32, the write pixel counter and the horizontal write period are connected to the AND gate 32a and the horizontal address counter 3.
2b, a horizontal screen of 640 dots, which is the same as the maximum television screen, is obtained, and the write synchronization signal and the vertical write period are antegrated by 32c and the vertical address counter 32.
By passing through d, a vertical screen of 480 lines, which is the same as the maximum television screen, can be obtained.

As a result, a screen like the one shown in FIG. 2(a) appears in the memory 6.
will be written to. If the writing period is shortened, Figure 2 (a
) screen is partially scraped off and remains in the upper left part.

The horizontal and vertical write addresses generated by the write counter 32 in this manner are applied to the clock terminal CK of the launch circuit 10 to enable latching, and the frequency is divided by 4 by the divide-by-4 circuit 12 to the latch circuit 10. 4 given to load terminal LO
To make it possible to load pixels into a memo IJ6 all at once.

As mentioned above, since the address selector 7 is currently selecting the address on the write side, the data from the launch circuit 10 is sent to each segment of the memory 6 according to the horizontal and vertical write addresses output from the frequency divider circuit 12. written.

In the read operation, a read address is generated by the read address generation circuit 6 shown in FIG. 6 in the same manner as the write address generation circuit 3.

However, as mentioned above, it is sufficient to specify only the vertical line address as the read address of the memory 6, so the vertical line read address is input from the read counter 52 to the address selector 7 without passing through the divide-by-4 circuit 12. At this time, since the address selector 7 has been switched to the read side by the synchronization signal of the PC signal, this vertical line address is given to the memory 6 to specify the address.

Since a clock is required to launch the pixels of each line to the launch circuit 11, the horizontal pixel read clock generated by the read counter 52 is divided by 4 by the 4 frequency divider circuit 12 and applied to the memory 6. Read each pixel of the line corresponding to the specified line address of the memory segment;
The data is read out from the launch circuit 11 using an undivided read clock, and the D/A converter 9 generates a personal computer video signal.

The screen read out in this way becomes as shown in FIG. 2(b), but in the example of FIG. 2(b), the maximum width of the television signal both horizontally and vertically is
This is specified as the display period for c, but is not limited to this.
Can be displayed on a small screen. However, in that case, some parts may be scraped off. Furthermore, if the display period is always set to 1'', the screen shown in FIG. 2(b) will stick exactly to the upper left corner.

Here, if there is no more data to be read from the memory 6 due to the write operation to the memory 6, the display screen will disappear. That is, since the synchronization signal of the television signal and the synchronization signal of the PC signal are generated non-simultaneously, in this case, the address selector 7 must preferentially select the read example address and provide it to the memory 6. Sometimes it is necessary to inhibit input to the latch circuit 10. Therefore, when the address selector 7 receives the read-side synchronization signal, it notifies the FIFO memory 8 of this fact, and upon receiving this, the FIFO
In the FO memory 8, reading of data that has been sequentially stored and read out is prohibited.

During this time, the address selector 7 is set to 1 as shown in FIG.
The addresses for the line are output to the memory 6, and when this is completed, the address selector 7 releases the read inhibited state of the FIFO memory 8 and performs the write operation again.

That is, as can be seen from FIG. 3, the address selector 7 processes reading as an interrupt operation.

FIG. 8 shows a mixed state of old and new on the screen memory due to such asynchronous write and read operations. Since the read speed exceeds the write speed, when time t2 has elapsed on the read side, the write The side shows that new data has been rewritten only up to A.

However, in the case of moving images, there is a very strong correlation between continuously sent screens, so this does not pose a visual problem.

FIG. 9 shows an application example of the present invention. By using the scanning frequency conversion circuit SC of the present invention, it is possible to easily display a television signal by converting it to the video frequency of a personal computer PC, and the OR gate By providing a synthesis circuit RC such as
It becomes possible to display the

In the above embodiments, television signals and personal computer signals have been taken as examples, but the present invention is not limited to this, and signal conversion of various different scanning frequencies can be performed.

〔Effect of the invention〕

As described above, according to the scanning frequency conversion device of the present invention, synchronizing signals are extracted from two video signals having different scanning frequencies, and the writing clock and the reading clock are phase-synchronized with these synchronizing signals and written respectively. The structure generates addresses and read addresses, writes and reads in response to the generation of each synchronization signal, and does not write to memory during read operations, so images with different horizontal and vertical scanning frequencies can be used. Even signals can be displayed on the screen at all times.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the scanning frequency conversion device according to the present invention, FIG. 2 is a diagram for explaining the input screen and display screen in the scanning frequency conversion device according to the present invention, and FIG. FIG. 4 is a block diagram showing an embodiment of the scanning frequency converting device of the present invention; FIG. 5 is a write address generation circuit used in the scanning frequency converting device of the present invention. FIG. 6 is a diagram showing an embodiment of the read address generation circuit used in the scanning frequency conversion device of the present invention. FIG. 7 is a time chart diagram for explaining phase synchronization of synchronization signals. , Fig. 8 is a diagram showing the writing state of old and new data on the screen memory, Fig. 9 is a diagram showing an application example of the present invention, and Fig. 10 is a block diagram showing a conventional scanning frequency conversion device. , FIG. 11 is a diagram showing a screen display example of the conventional example, and FIG. 12 is a time chart diagram of the conventional example. In Fig. 1, 1...A/D converter, 2.4...Synchronization separation circuit, 3...Write address generation circuit, 5...Read address generation circuit, 6...2 port screen Memory, 7... Address selector, 8... FIFO memory, 9... D/A converter. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] An A/D converter (1) that converts a first video signal into a digital signal, a circuit (2) that separates horizontal and vertical synchronization signals of the first video signal, and writing. a write address generation circuit (3) that includes a pixel clock, synchronizes the phase of the clock with the synchronization signal, and generates horizontal and vertical write addresses respectively corresponding to specified horizontal and vertical write periods; A circuit that separates the synchronization signal of the first video signal and the second video signal having a different scanning frequency (
4) It has a built-in readout pixel clock, synchronizes the phase of the clock with the synchronization signal of the second video signal, and generates the horizontal pixel readout clock and vertical line readout address corresponding to the specified horizontal and vertical display periods. and set the read clock to 2
The read address generation circuit (5) given to the port screen memory (6) and the synchronization signal of the first or second video signal give priority to the read address of both address generation circuits (3) and (5). an address selector (7) that selects one of the memory (6) and specifies the address of the memory (6); and an address selector (7) that normally reads data from the A/D converter (1) to the memory (6) as is FIF that prohibits reading only when it receives the synchronization signal of the video signal of 2.
1. A scanning frequency conversion device comprising: an O memory (8); and a D/A converter (9) that converts a signal in the screen memory into an analog signal.