JP2738286B2 - Image processing apparatus and method, and computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method used for a personal computer and the like , and
A computer system including the image processing device .

[0002]

2. Description of the Related Art Conventionally, there has been an image processing apparatus capable of operating a personal computer while watching a television by superimposing a television image at a predetermined size and a predetermined position on a monitor screen of the personal computer.

FIG. 21 is a block diagram of a conventional video processing apparatus. In FIG. 21, reference numeral 100 denotes a first video signal VS1 as a first synchronization signal SS1 and a first luminance signal LS1.
The video decoder 200 separates the first luminance signal L
An analog-to-digital converter (hereinafter referred to as ADC) for converting S1 into a digital signal, a video memory 300 for storing a first luminance signal LS1 obtained by digital conversion, and a reference numeral 340 for controlling the writing of the first luminance signal LS1 to the video memory 300. The writing control unit 350 is a read control unit that controls reading of the first luminance signal LS1 from the video memory 300, and the reference numeral 400 is a digital-to-analog converter (hereinafter, referred to as a digital-to-analog converter) that converts the first luminance signal LS1 that is read from the video memory 300 , DAC), 600 is a CPU control unit, 630 is a multiplexer, 640 is a third video signal VS3 which is a third synchronizing signal SS3 and a third luminance signal LS3.
And a mixing control unit 500 for mixing the first luminance signal LS1 and the third luminance signal LS3 and outputting a fourth luminance signal LS4.

This conventional video processing circuit is a video decoder 1
00 represents the video signal VS1 as the synchronization signal SS1 and the luminance signal LS.
The ADC 200 converts the luminance signal LS1 into a digital signal and writes the digital signal into the video memory 300. At this time,
The write control unit 340 sets the ADC based on the synchronization signal SS1.
A timing clock for controlling the operation of the video memory 200 and the video memory 300 is output. Note that the second luminance signal LS2 output by the CPU control unit 600 can also be written to the video memory 300.

[0005] The read control unit 350 is connected to the video memory 300.
The first luminance signal LS1 (or the second luminance signal LS2) written into the first luminance signal LS1 is read through the multiplexer 630, the DAC 400 converts the first luminance signal LS1 read from the video memory 300 into an analog signal, and 500 is the first luminance signal LS1 and the third luminance signal L
By mixing with S3, a fourth luminance signal LS4 in which an image corresponding to the first luminance signal LS1 is superimposed in an image corresponding to the third luminance signal LS3 is output.

When the image is frozen, the CPU 620 monitors the operation of the video decoder unit 100,
When the decoder unit 100 outputs a vertical synchronization signal, the CPU 620
During the vertical blanking period in the video signal.
To stop digitizing control. Note that, when the image is still, the first image is also included in the image corresponding to the third luminance signal LS3.
LS4 obtained by superimposing an image corresponding to the luminance signal LS1 is obtained. Further, when superimposing a character and a special shape on an image corresponding to the first luminance signal LS <b> 1, the CPU control unit 600 writes the character and the special shape data in the video memory 300.

[0007]

By the way, the conventional video processing apparatus shown in FIG. 21 is capable of displaying an image at an arbitrary resolution, converting an arbitrary aspect ratio, and converting to an arbitrary position in accordance with the development of a smart image which will be developed in the future. There has been a problem that it is not possible to cope with multi-purpose specifications such as display control and superimposition.

[0008] Further, in order to achieve the multi-purpose specification, the equipment becomes equivalent to several hundreds to tens of millions of yen, such as a television broadcasting equipment currently used by a commercial broadcasting station or the like. For this reason, there has been a problem that fundamental technological reform is necessary in order to make the equipment of a consumer equipment level.

Further, since the video memory 300 is generally constituted by a dynamic memory, a refresh is required. Therefore, a clock signal for refreshing the video memory 300 is added to the serial port of the video memory 300. This clock signal is, for example, 10
(MHZ) or higher. Therefore, the number of clocks of the serial output of the multiplexer 630 is 100 (KH
From z) to several (MHz), 10 (MHZ) or more must be supplied from the serial output other than the DAC 400 side. To the serial output other than the side of the DAC 400, a mere refresh clock not for the purpose of output must be sent.

When the CPU controller 600 wants to read the video data from the video memory 300, the multiplexer 630 is switched to switch the video data to the CPU controller 600.
Is read, and no video data is sent to the DAC 400 during that time.
Even if the video from 00 is superimposed, there is a problem that the fourth luminance signal LS4 becomes blanked.

Further, there is a problem that it is impossible for the CPU to read the CPU control section 600 with an operation of constantly 10 (MHZ) or more from the serial output other than the DAC 400 side.

When the image is frozen, the CPU controller 6
00 needs to monitor the vertical synchronization signal VS1,
In the worst case, there is a problem that the CPU control unit 600 requires a waiting time of several tens of milliseconds.

Even if the CPU control unit 600 has a high-speed IC such as a digital signal processor (DSP), it takes several tens of hours to rewrite characters and special shapes.
(Us) or more.

When the third luminance signal LS3 is a signal corresponding to a moving image, the number of frames of the third luminance signal LS3 is reduced, and the CPU 620 needs time to rewrite the storage contents of the video memory 300. .

Further, scrolling of characters, special shapes, and the like in the vertical and horizontal directions cannot be performed on the third luminance signal LS3.

SUMMARY OF THE INVENTION The present invention has been made to solve at least a part of the above problems, and a plurality of images including a moving image can be displayed.
The purpose is to display while compositing .

[0017]

In order to solve the above-mentioned problems, the invention described in claim 1 provides a display device.
A method of displaying a combined image a plurality of images on the chair, the steps of receiving a first image signal representing the first image, in synchronization with the first synchronizing signal, the first image signal and storing the image memory, provided to said display device
Second in synchronization with the synchronization signal is, and expand the first image signal from said image memory in an arbitrary ratio, including nonintegral
Reading while reducing the size of the first image read from the video memory in synchronization with the second synchronization signal
By selecting while switching one of the plurality of image signals and a second image signal supplied from the signal and the display control unit, represented by the first and second image signals
By supplying a step of generating a third image signal representing a composite image of the image, the third image signal and a second synchronization signal to said display device, displaying the composite image on the display device comprising a step of, the said first
The step of reading out the first image signal includes the step of:
The frequency of the included horizontal synchronizing signal and the
The relative relationship between the read line address and the update frequency
Adjusting the first image signal in the vertical direction.
A step of enlarging / reducing at an arbitrary magnification is provided .

After the first image signal is temporarily stored in the video memory, the first image signal is read from the video memory in synchronization with the second synchronization signal supplied to the display device.
The first image signal and the second image signal can be selected while switching in synchronization with the second synchronization signal. As a result, the third image signal representing an image obtained by synthesizing the image represented by the first and second image signals can be easily obtained, also by using the third image signal, displays the composite image Can be displayed on the device. Further, according to the above method, when reading the first image signals from the video memory, so read while scaling with an arbitrary magnification including non-integer, in the composite image, tables in the first image signal The displayed image can be displayed at an arbitrary magnification . Especially,
The magnification in the vertical direction is determined by the horizontal synchronization included in the second synchronization signal.
Signal frequency and readout line address given to video memory
Easily set to any value depending on the relative relationship with the update frequency
Can be adjusted. Note that "any integer including non-integer
The term “magnification” refers to non-integer multiples as well as integral multiples.
It means that you can expand at a large rate, and
Reduction ratios other than a fraction (for example, M / N times (M and N are 1 or less)
Outside integer)) means that it can be reduced. In addition, "Read
`` Update frequency of output line address ''
This is the frequency when it is considered that the address is updated one by one. An example
For example, the read line address is incremented by 1 as 0, 1, 2,.
The reciprocal of the increase period corresponds to the update frequency
, And the read line address increases by 2, such as 0, 2, 4,.
When the renewal frequency is twice the reciprocal of the
Equivalent to.

According to the image processing method of the present invention,
Storing the first image signal in the video memory comprises scaling the first image .

If [0020] This, while scaling the first image, it is possible to write the first image signal to the video memory.

According to a third aspect of the present invention, there is provided a display device.
An apparatus for displaying a combined image a plurality of images to scan, means for receiving a first image signal representing the first image and the first synchronizing signal, for storing the first image signal In synchronization with the first synchronization signal,
A first controller for controlling the writing of the first image signal into the image memory, et applied to the display device
A second controller that controls an operation of reading out the first image signal from the video memory while enlarging / reducing at an arbitrary magnification including a non-integer in synchronization with a second synchronization signal to be read out; In synchronization with a synchronization signal, one of a plurality of image signals including the first image signal read from the video memory and the second image signal provided from the display control unit is switched and selected. By doing so, the first
When the third image signal generated by the representative of the composite image of the image represented by the second image signal, and a video switch for supplying the third image signal to the display device, wherein
A second controller included in the second synchronization signal
The frequency of the horizontal synchronizing signal and the reading given to the video memory
Adjust the relative relationship between the output line address and the update frequency
Thereby, the first image signal can be vertically multiplied by an arbitrary factor.
It has a means to enlarge / reduce at a rate .

After the first controller temporarily stores the first image signal in the video memory, the second controller synchronizes the first image signal with the second synchronization signal supplied to the display device.
Reading out the image signal from the video memory. The video switch can select the first image signal and the second image signal while switching them in synchronization with the second synchronization signal, and as a result, are represented by the first and second image signals. A third image signal representing an image obtained by synthesizing the images can be created. Then, if the third image signal and the second synchronization signal are supplied to the display device, the composite image can be displayed on the display device.

Further, while enlarging or reducing the first image at an arbitrary magnification including a non-integer, the first image signal can be read out from the video memory and displayed in the composite image . In particular, the vertical scaling factor is included in the second synchronization signal.
Horizontal sync signal frequency and readout given to video memory
Arbitrary depending on the relative relationship with the line address update frequency
Can be easily adjusted.

In the image processing apparatus according to the fourth aspect,
The first controller comprises means for scaling the first image .

According to a fifth aspect of the present invention, a display device is provided.
A method of displaying a combined image a plurality of images in the scan, the first analog image signal representing the first image and the first
Receiving the first synchronizing signal, generating the first digital image signal by A / D converting the first analog image signal in synchronization with the first synchronizing signal, and generating the first digital image signal. in synchronization with the synchronizing signal, and storing the first digital image signal to the video memory, the display de
Reading the first digital image signal from the video memory while enlarging / reducing at an arbitrary magnification including a non-integer in synchronization with a second synchronization signal given to the device; Synchronizing and digitally converting the first digital image signal read from the video memory to generate a second analog image signal;
The second analog image is synchronized with the second synchronization signal.
One of a plurality of analog image signals including an image signal and a third analog image signal provided from the display control unit is cut off.
By selecting while Rikae, the second and generating a fourth analog image signal representing a composite image of the image represented by the third analog image signal, said fourth analog image signal and the second of by a synchronization signal supplied to the display device, and a step of displaying the composite image on the display device, the first digital
The step of reading out the total image signal includes the step of:
The frequency of the included horizontal synchronizing signal and the
The relative relationship between the read line address and the update frequency
Adjusting the first digital image signal.
A step of enlarging / reducing at an arbitrary magnification in the vertical direction .

According to the image processing method of the present invention,
Storing the first digital image signal in the video memory comprises scaling the first image .

According to a seventh aspect of the present invention, there is provided a display device.
An apparatus for displaying a combined image a plurality of images in the scan, the first analog image signal representing the first image and the first
Means for receiving the first analog image and the synchronizing signal.
The first digital image is obtained by A / D converting the image signal.
An A / D converter for generating an image signal;
A video memory for storing the image signals, in synchronization with the first synchronizing signal, a first controller for controlling the writing of said first digital image signal to the image memory, provided to said display device A second controller which controls an operation of reading out the first digital image signal from the video memory while enlarging / reducing the image data at an arbitrary magnification including a non-integer in synchronization with a second synchronizing signal. And the first digital image signal read from the video memory
A D / A converter that generates a second analog image signal by performing A-conversion, and in synchronization with the second synchronization signal,
By switching and selecting one of a plurality of analog image signals including the second analog image signal and the third analog image signal provided from the display control unit, image represented by the third analog image signal
Generates a fourth analog image signal representing a composite image of the image, and a video switch for supplying said fourth analog image signal to the display device, the second controller
A roller for outputting a horizontal synchronizing signal included in the second synchronizing signal;
Frequency and read line address given to the video memory
By adjusting the relative relationship between the
The first digital image signal is vertically scaled at an arbitrary magnification.
A means for enlarging / reducing is provided .

In the image processing method according to the present invention,
The first controller comprises means for scaling the first image .

According to a ninth aspect of the present invention, a computer
Data system, Display control for controlling display devices
Department andNo.OneimageThe first representingimageSignal and first synchronization
Means for receiving a signalimageStore signal
And a video memory for synchronizing with the first synchronizing signal.
The first memory to the video memoryimageSignal writing
A first controller for controlling;Giving the display device
availableIn synchronization with the second synchronization signal, the video memory
Said the firstimageRead operation while scaling the signal
A second controller for controlling the operation of the second synchronization signal;
In synchronization with the video signal,
OneimageSignal and a second signal provided from the display control unit.Picture
imageIncluding multiple signalsimageOne of the signalsswitching
WhileBy selecting the first and secondimagesignal
Represented byimageSynthesis ofimageA third representingimageSignal
Generate the thirdimageSupply signal to the display device
Video switch, The second controller
Is the frequency of the horizontal synchronizing signal included in the second synchronizing signal.
Wave number and read line address given to the video memory
By adjusting the relative relationship with the update frequency of the
Enlarging / reducing the first image signal at an arbitrary magnification in the vertical direction
Have means to.

The invention according to claim 10 is a computer
Data system, Display system for controlling display devices
Obe andNo.OneimageA first analog representingimageSignal and
Means for receiving a first synchronization signal and the first analog signal;
TheimageA first digital signal is obtained by A / D converting the signal.
LeimageAn A / D converter for generating a signal;
TallimageA video memory for storing a signal;
In synchronization with the synchronization signal of
DigitalimageFirst control for controlling signal writing
La andGiven to the display deviceFor the second synchronization signal
In synchronization with the first digitalimage
Read signals while scaling at any magnification, including non-integers
A second controller for controlling the output operation;
The first digital read from the memoryimageD signal
The second analog by A-conversionimageLive signal
And a D / A converter to be synchronized with the second synchronization signal.
And the second analogimageFrom the signal and the display control unit
3rd analog givenimageMultiple analyzers including signals
logimageOne of the signalsWhile switchingTo choose
The second and third analogsimageSignaled
BeimageSynthesis ofimageA fourth analog representingimageSignal
Generate the fourth analogimageSignal to the display device
A video switch for supplying the, Said second co
The controller controls a horizontal synchronization signal included in the second synchronization signal.
Signal frequency and readout line applied to the video memory
By adjusting the relative relationship with the address update frequency
The first digital image signal is vertically multiplied by an arbitrary factor.
Providing means to scale at a rate.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a schematic block diagram of an image processing apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 100 denotes an external device (not shown) such as a composite video signal VSTV or VTR from a tuner (not shown).
Composite video signal VSEX (hereinafter simply referred to as composite
A positive video signal (VSTV) is converted to a luminance signal (con
Component video signal) Video decoder for separating LSTV and synchronization signal SSTV, ADC controller 200 for converting luminance signal LSTV into a digital signal, 300 3-port video memory controller for storing luminance signal LSAD which is a digital signal, 400 Is a DAC control unit that reads out the luminance signal LSMEM stored in the 3-port video memory control unit 300 and converts it into an analog signal, and 500 is a digital computer that reads the luminance signal LSMEM read from the 3-port video memory control unit 300 and converts it into an analog signal. , Workstations, terminals and game consoles (hereinafter referred to as personal computers)
(Not shown) The output luminance signal LSPC is mixed with the output luminance signal LSPC, and the luminance signal L is included in an image corresponding to the luminance signal LSPC.
A video mixing control unit 600 for outputting a luminance signal LSMON obtained by superimposing an image corresponding to the STV, 600
The video decoder 100, ADC controller 200,3 port video memory 300, DAC control unit 400 and the video mixing control unit 500, CPU controller der outputs control data via the data bus 610 is, also, the luminance signal L
The SPC is under the control of the CPU control unit 600. CPU
The control data output by the control unit 600 is data for obtaining a luminance signal LSMON according to the purpose, and is managed by the CPU control unit 600.

FIG. 2 is an external view of the image processing apparatus shown in FIG. In FIG. 2, 700 is a personal computer main body,
701 is a personal computer monitor, 702 is a keyboard, 703
Denotes a mouse, 704 denotes an expansion slot card which realizes a main part of the image processing apparatus as an embodiment of the present invention , 705 denotes a video cable between the main units for connecting the personal computer main unit 700 and the expansion slot card 704, and 706 denotes a personal computer monitor 70.
1 is an inter-monitor video cable connecting the first slot card 704 to the expansion slot card 704; 710, a tuner;

This image processing apparatus comprises an expansion slot card 70 between a personal computer main body 700 and a personal computer monitor 701.
4 is provided. Expansion slot card 70
4 connects a tuner 710 and inserts it into an expansion slot (not shown) of the personal computer 700 as shown in FIG.

Luminance signal LST output from tuner 710
The image corresponding to V is displayed on the keyboard 702 or the mouse 70.
By the operation of 3, the image corresponding to the luminance signal LSPC is displayed at an arbitrary position in an arbitrary position of the image corresponding to the luminance signal LSPC displayed on the personal computer monitor 701 at an arbitrary timing together with the image corresponding to the luminance signal LSPC.

FIG. 4 is a detailed block circuit diagram of a main part of the video processing circuit shown in FIG. In FIG.
Reference numeral 101 denotes an audio signal terminal for inputting an audio signal ASEX output from a VTR or the like, and reference numeral 110 denotes an audio signal selection circuit for selectively outputting the audio signal ASEX input from the audio signal terminal 101 and the audio signal ASTV input from the tuner 710.
(In the following description, the audio signal ASTV is selected.
To), volume control circuit which controls the volume of the audio signal ASTV 120, 102 audio signal terminal for outputting the audio signal ASTV selected as an audio signal ASMON computer monitor 701, 103 VTR or the like and outputs compositing
The video signal terminal for inputting a Tsu door video signal VSEX, 130
Compositor is inputted from the composite video signal VSEX a tuner 710 that is input from the video signal terminal 103
In Tsu picked up image signal selection circuit for selectively outputting a video signal VSTV (later described, the composite video signal VSTV is
And it has been selected), 140 were selected output con
The positive video signal VSTV is converted to a luminance signal (component
Video signal) This is a video signal decoder that separates the signal into an LSTV and a synchronization signal SSTV.

Reference numeral 210 denotes an ADC for digitally converting the luminance signal LSTV, and reference numeral 220 denotes a digitizing control unit for controlling the ADC 210 and the video memory 310 based on the synchronization signal SSTV.

Reference numeral 310 denotes a three-port video memory having one write port and two read ports, and 320 denotes an ADC.
The luminance signal LSTV output from the video memory 210 or the luminance signal W output from the personal computer (not shown) to the video memory 310
A video data selection circuit 330 for selectively outputting the LSPC is provided with a video memory control signal WETV or a write control unit 34 output from the digitizing control unit 220 to the video memory 310.
Video memory control signal selecting circuit for selecting and outputting the video memory control signal WEPC 0 is outputted, 340 3-port video memory 310 of the luminance signal W LSPC outputting PC
A write control unit 350 for controlling writing to the memory, 350 is a read control unit, 360 is a FIFO memory of a first-in first-out method for storing one horizontal line in the luminance signal LSMEM stored in the 3-port video memory 310, and 370 is A FIFO read control unit that controls reading of the luminance signal LSMEM from the 3-port video memory 310.

Reference numeral 410 denotes a DAC, and 420 denotes a horizontal synchronizing signal HSPC and a vertical synchronizing signal VSP output from a personal computer.
C, a 3-port video memory 310, a DAC 41
0, a superimpose control unit for controlling the AND circuit 530, and 510 a luminance signal LSPC or 3 from a personal computer.
A video switch that outputs one of the luminance signals LSMEM from the port video memory 310 as a luminance signal LSMON of the personal computer monitor, 520 is a mixing control unit, 540 is a reference voltage Vr and a luminance signal L from the personal computer.
A voltage comparator 620 for comparing with the SPC is a CPU in the main body of the personal computer.

Next, FIG. 5 is a connection diagram of the tuner 710 and the expansion slot card 704. In FIG. 5, 71
2 outputs a power signal of the tuner 710, a control signal such as a tuning signal to the tuner 710, and outputs the audio signal A from the tuner 710.
STV, tuner control connector for inputting a video signal VSTV, 713 is input an audio signal ASEX external device such as a VTR (not shown) is output to the expansion slot card 704
Forces input connector, 714 external device (figure VTR etc.
(Not shown) is an input connector for inputting the video signal VSEX output to the expansion slot card 704.

The audio signal ASMON is supplied to the headphones 7 via a plug 716 connected to the output connector 715.
17 or a speaker (not shown).

The tuner 710 converts the audio signal ASTV and the video signal VSTV of a specific channel out of the signals received from the antenna 711 and the antenna terminal (not shown) through the output connector 712 into the audio signal selection circuit 110 and the video signal selection circuit. Output to the circuit 130 respectively. In this case, channel selection is performed under the control of CPU 620.

The audio signal ASEX and the video signal VSEX are also output from the video equipment (not shown) such as a video deck and a laser disk to the audio signal selection circuit 110 and the video signal selection circuit 130, respectively.

The audio signal selection circuit 110 selects an audio signal ASTV or ASEX under the control of the CPU 620 and outputs it to the volume control circuit 120. Voice control circuit 12
0 is controlled by the CPU 620, and the audio signal selection circuit 1
The audio signal ASTV output from the amplifier 10 is amplified and output to the audio signal terminal 102 as an audio signal ASMON between the personal computer monitor cables. The audio signal ASMON is also output to the output connector 715 . The video signal selection circuit 130 controls the video signal VSTV under the control of the CPU 620.
Alternatively, VSEX is selected and output to the video signal decoder 140. Reference numeral 705 denotes a luminance signal LSP output from the personal computer.
C, horizontal sync signal HSPC and vertical sync signal VSPC
Input connector. 706 is a personal computer monitor
701, a luminance signal LSMON, a horizontal synchronization signal HSPC,
This is an output connector for outputting the vertical synchronization signal VSPC.

FIG. 6 is a diagram for explaining the operation of the image processing apparatus. The image corresponding to the video signal obtained from the tuner 710 displayed on the display screen of the personal computer monitor 701 is reduced and moved to the upper right. Show where you are. Mouse 703
, The tuner 710 indicated by the mouse cursor 301 and the video image area are determined, and the mouse switch is performed.

Next, FIG. 7 shows the application software of the present invention.
MS-D, the OS of a personal computer, using software
It is a memory map in a state where it is incorporated as a device driver (front processor) in an OS using an OS (registered trademark). No matter what application software is running on the OS by this built-in, by simply key <br/> board operation and mouse operation, running the application software <br/> Towea, from the television or video deck You can easily see the picture at your favorite position and size.

Next, the video signal decoder 140 separates the video signal VSTV output from the video signal selection circuit 130 into a luminance signal LSTV and a synchronizing signal SSTV.
0 and output to the digitizing control unit 220. The synchronization signal SSTV includes a vertical synchronization signal VSSTV and a horizontal synchronization signal HSSTV .

The ADC 210 converts the luminance signal LSTV output from the video signal decoder 140 into a digital signal according to the clock signal CKAD output from the digitizing control unit 220, and outputs the digital signal to the 3-port video memory 310 via the video data selection unit 320. I do.

Also, the digitizing control unit 220 is provided with the ADC 21
A clock signal CKAD is output to 0, and a write control signal WETV is output to the 3-port video memory 310 via the video memory control signal selection unit 330. Therefore, 3
The port video memory 310 stores the updated luminance signal LSTV under the conditions controlled by the CPU 620.

Next, FIG. 8 is a block circuit diagram of the digitizing control unit 220 and its peripheral circuits shown in FIG. Note that the video memory control signal selection unit 330 is omitted. In the present embodiment, as the 3-port video memory 310, for example, CXK1206 manufactured by Sony Corporation or MB81C1 manufactured by Fujitsu Limited
501 is used. The 3-port video memory 310
The description will be made using only the read port. A characteristic timing chart is described on pages 21 to 26 of the data sheet 71125-ST manufactured by Sony Corporation.

The 3-port video memory 310 has 960 rows (C
(OLUMN) × 306 columns (ROW) * 4 bits. Therefore, one effective horizontal scanning period can be quantized by 960. Access to the three-port video memory 310 is performed in units of blocks for rows and units for columns.

In the 3-port video memory 310, DI
N0 to DIN3 are data inputs for inputting the luminance signal LSAD , ADD0 to ADD3 are horizontal address inputs, C
KW0 horizontal write clock signal for port 0, INC0 the line increment port 0, HCLR0 horizontal clearing port 0, VCLR0 vertical clearing port 0,
WE (negative logic) of the write enable port 0 (Shokomimoto
OK) . These signals CKW0, VCLR
0, HCLR0, INC0, WE (negative logic), ADD
0, luminance signal LS controlled by DIN0 to DIN3
AD is a 4-bit, that is, a 16- gradation gray image signal.

It is needless to say that a luminance signal of 4 bits or more and a color signal can be handled similarly by connecting a plurality of 3-port video memories 310 in parallel.

In FIG. 8, reference numeral 140 denotes a video signal VSTV.
The horizontal synchronizing signal HSSTV, a video signal decoder and outputting the separated vertical synchronizing signal VSSTV and luminance signal LSTV, 221 horizontal dot clock generator for outputting a horizontal write dot clock signal HWDCK and basic synchronization signals BSYNC, 222 horizontal Write start signals HWS and HCL
A horizontal writing start counter 223 for outputting the R0 signal, a horizontal writing counter 223 for outputting the horizontal writing number signal HWT, a vertical writing line clock generator 224 for outputting the vertical writing line clock signal VWLCK, and a reference numeral 225 A vertical write start counter that outputs a vertical write start signal VWS,
Reference numeral 226 denotes a vertical write number counter that outputs a vertical write number signal VWT, and 227 denotes a vertical write offset signal VW that specifies the vertical write position of the 3-port video memory 310.
The vertical write offset counter 228 outputs the OFT and the port 0 line increment INC0, and outputs the vertical write line clock signal VWLCK and the vertical write offset signal VWOFT to the port 0 line increment signal IN.
An OR circuit 229 outputting as C0 has a horizontal write dot clock signal HWDCK, a horizontal write start signal HWS, an inverted output of the horizontal write count signal HWT, and a vertical write start signal V.
An AND circuit that takes the logical product of WS and the inverted output of the vertical write count signal VWT and outputs a write enable signal WENBL;
230 is a vertical synchronization signal VSSTV , HCLR0 signal, O
This is a NOR circuit that takes an OR-NOT of an output signal of the R circuit 228 and a write enable signal WENBL output by the AND circuit 229, and outputs a port 0 write enable signal WE.

In the case of color, the luminance signal LSTV
Are R, G and B luminance signals RLSTV, GLSTV,
BLSTV.

The video signal decoder 140 converts the video signal VSTV output from the video signal selection circuit 130 into a horizontal synchronization signal H.
SSTV , vertical synchronizing signal VSSTV and luminance signal LST
V. The horizontal synchronizing signal HSSTV includes a dot clock generator 221, a horizontal write start counter 222, a horizontal write number counter 223, and a vertical write start counter 225.
Is output to The vertical synchronizing signal VSSTV is AND times.
Via line 810, the vertical write line clock generator 22
4, vertical writing start counter 225, vertical writing number counter 226, vertical writing offset counter 227, port 0 vertical clear terminal VCLR of 3-port video memory 310
0 and output to NOR circuit 230 . Further, the luminance signal LSTV is output to the ADC 210.

The ADC 210 converts the luminance signal LSTV into a digital signal according to the horizontal write dot clock signal HWDCK input as the clock signal CKAD, and converts the digitally converted luminance signal LSAD into the 3-port video memory 310.
Output to

[0057] dot clock generator 221 is synchronized with the horizontal synchronizing signal HSSTV, i.e. horizontal synchronization signals HSSTV
, A horizontal write dot clock signal HWDCK having a period of 1 / N (N is a positive integer) is generated. This horizontal write dot clock signal HWDCK is AD
C210, the horizontal write start counter 222, the horizontal write number counter 223, and the AND circuit 229.

When the address preset block unit of the 3-port video memory 310 is 60 dots and one effective horizontal scanning period of the video signal VSTV is 50 (μs), the frequency of the horizontal write dot clock signal HWDCK is 60 (dots). / 50 · 10 ⁻⁶ (S) = 1.2 (MHz).

This horizontal write dot clock signal HWDC
By K, one effective horizontal scanning period can be quantized by 60 dots. Therefore, the 3-port video memory 310 has 6
Since one dot is defined as 16 blocks (960 dots), the luminance signal LSTV in one effective horizontal scanning period is blocked by 1.2 (MHz) × 16 (block) = 19.2 (MHz). Can be written in units. As described above, the horizontal write dot clock generator 221 outputs the horizontal write dot clock signal HWDCK having a frequency based on the value of the block B. The value of the block B can be set by the CPU 620.

The horizontal writing dot clock generator 221
Generates a basic synchronizing signal BSYNC used as a clock for a port 0 shift signal terminal CKW0 of the 3-port video memory 310 (a signal for incrementing the horizontal write address of the 3-port video memory 310 in dot units).

Accordingly, the cycle of the clock signal CKAD for digitally converting the luminance signal LSTV is が, and the cycle of the basic synchronization signal BSYNC for incrementing the horizontal write address of the 3-port video memory 310 in dot units is ２. >, The video corresponding to the luminance signal LSTV has a standard resolution . Further , when the cycle of the clock signal CKAD is smaller than the cycle of the basic synchronization signal BSYNC, the luminance signal L
An image corresponding to the STV has a reduced resolution . The basic synchronization signal BSYNC is a signal for performing basic synchronization with each control circuit.
2, horizontal writing number counter 223, vertical writing line clock generator 224, vertical writing start counter 225, vertical writing number counter 226, vertical offset counter 22
Port 0 shift signal of 7 and 3 port video memory 310
Output to terminal CKW0 .

The vertical write line clock generator 224 is synchronized with the vertical synchronizing signal VSSTV and outputs the vertical synchronizing signal VSST.
A vertical write line clock signal VWLCK having a frequency M times the frequency of V is output to the vertical write number counter 226 and the OR circuit 230. The value of M can be set by the CPU 620. The value of M is determined based on the aspect ratio suitable for the dot clock generator 221.

The horizontal writing start counter 222 is reset by the horizontal synchronizing signal HSSTV , counts the number of clocks of the horizontal writing dot clock signal HWDCK, and starts counting from the S1 clock during the effective horizontal scanning period of the video signal VSTV.
A horizontal write start signal HWS that permits quantization of the luminance signal LSTV is output.

With the output of the horizontal write start signal HWS,
The horizontal write start counter 222 is a 3-port video memory 31
0 is output as the port 0 horizontal clear signal HCLR0 for one clock. The horizontal write counter 223 outputs the horizontal synchronization signal H.
The horizontal write start signal HWS is reset by the SSTV.
Is output, the horizontal write dot clock signal HWDC
The counting of the K clock is started, and the effective horizontal scanning period of the video signal VSTV is set to the luminance signal LS for only the E1 clock.
A horizontal writing frequency signal HWT for permitting the quantization of the TV is output. Therefore, the horizontal writing number counter 223 controls the effective horizontal scanning period.

The vertical write start counter 225 is reset by the vertical synchronizing signal VSSTV , and the horizontal synchronizing signal HSST is reset.
The number of V clocks is counted, and a vertical write start signal VWS that permits quantization of the luminance signal LSTV for effective horizontal scanning is output from the S2 clock during the vertical effective scanning period of the video signal VSTV.

The vertical write counter 226 is reset by the vertical synchronizing signal VSSTV , and the vertical write start signal V
When WS is output, the vertical write line clock signal VW
LCK clock counting is started, and the video signal VST
During the vertical effective scanning period of V, the luminance signal L
A vertical write count signal VWT for permitting STV quantization is output. Therefore, the vertical writing counter 226 controls the vertical effective scanning period.

The horizontal writing position on the display screen of the 3-port video memory 310, that is, the writing position in the COLUMN direction is determined by the address preset mode, with 60 bits of the quantized luminance signal LSAD as one block.
Perform by specifying a block. Block designation is performed in 16 stages by address input signals ADD0 to ADD3. The address input signals ADD0 to ADD3 are
0 can be set. The vertical writing position on the display screen of the 3-port video memory 310 is set by a vertical writing offset counter 227.

The vertical write offset counter 227 is reset by the vertical synchronizing signal VSSTV, and the vertical write offset signal VWOFT for offsetting the vertical write position of the 3-port video memory 310 while synchronizing with the basic synchronizing signal BSYNC, and the line increment. Signal INC
0 is output as an S3 clock to control the vertical writing position of the 3-port video memory 310.

The value of S1, the value of E1, the value of S2,
The value of 2 and the value of S3 are set by the CPU 620.

Next, the digitizing control unit 22 shown in FIG.
The operation of 0 and its peripheral circuits will be described with reference to the timing chart of FIG.

(1) When the vertical synchronizing signal VSSTV becomes high level "H" (see FIG. 9A), the vertical writing start counter 225, the vertical writing number counter 226 and the vertical writing offset counter 227 are reset. , The vertical write start signal VWS and the vertical write number signal VWT become low level “L” (see FIGS. 9D and 9E).

(2) Vertical write offset counter 227
Is the basic synchronization signal BSYNC and the vertical write offset signal V
9 is output as WOFT for S3 clocks.
(H)). When the vertical write offset signal VWOFT is O
By the output via the R circuit 228, the port 0 line increment signal terminal IN of the 3-port video memory 310
The address is output to C0, and the vertical address of the 3-port video memory 310 is incremented S3 times.

(3) On the other hand, the vertical writing start counter 225
When the number of clocks of the horizontal synchronizing signal VSSTV becomes S2, the vertical writing start signal VWS is set to the high level “H”, and quantization is permitted over the vertical effective scanning period (FIG. 9).
(D)).

(4) Vertical write offset signal VWOFT
When the horizontal writing signal HSSTV becomes high level "H" (see FIG. 9 (j)), the horizontal writing start counter 222 and the horizontal writing frequency The counter 223 is reset, and the horizontal write start signal HWS and the horizontal write count signal HWT are set to low level "L" (see FIGS. 9 (n) and 9 (o)). The dot clock generator 221 outputs a horizontal write dot clock signal HWDCK (FIG. 9).
(M)). Horizontal write dot clock signal HWDCK
, The ADC 210 operates using the horizontal write dot clock signal HWDCK as a sampling hold signal and a data latch signal, and samples the luminance signal LSTV.

The horizontal write start counter 222 counts the number of clocks of the horizontal write dot clock signal HWDCK, and when the count value reaches S1, sets the horizontal write start signal HWS to a high level "H" to enable effective horizontal scanning. Period quantization is permitted (see FIG. 9 (n)). At the same time,
The horizontal write start counter 222 is a 3-port video memory 31
The port 0 horizontal clear signal HCLR0 of 0 is output for one clock to prepare for writing. At this time, the AND circuit 2
Reference numeral 29 denotes a high level "H" horizontal write start signal HWS, and a low level "L" horizontal write number signal HW which is inverted and input.
T, a high level "H" vertical write start signal VWS and a low level "L" vertical write number signal VW which is inverted and input
The AND condition of T is taken, and the horizontal write dot clock signal H
WDCK is output to the NOR circuit 230 as the write enable signal WENBL.

Further, the NOR circuit 230 outputs a high level "H" port 0 horizontal clear signal HCLR0, a high level "H" vertical synchronizing signal VSSTV , and a high level "H".
Vertical write offset signal VWOFT or vertical write line clock signal VWLCK and write enable signal WENBL
Of the three-port video memory 310
As a write enable signal WE to the write enable signal terminal WE. The 3-port video memory 310 writes the luminance signal LSAD output from the ADC 210 in response to the output of the write enable signal WE.

At the same time, the horizontal writing number counter 223 counts the number of clocks of the horizontal writing dot clock signal HWDCK, and keeps the luminance signal until the count value reaches E1.
Allow writing of LSAD . When the count value reaches E1, the horizontal write number counter 223 sets the horizontal write number signal HWT to a high level "H" to inhibit writing (FIG. 9).
(O)).

While writing the luminance signal LSAD ,
Until the vertical write line clock generator 224 outputs the vertical write line clock signal VWLCK, horizontal write is performed for the same vertical write address.

The vertical write line clock generator 224 outputs the vertical write line clock signal VWLCK to the port 0 line increment INC0 of the 3-port video memory 310.
When output as a signal, the write line address in the vertical direction of the 3-port video memory 310 advances by one.

When the clock number of the vertical write line clock signal VWLCK output from the vertical write line clock generator 224 reaches the vertical write number counter 226, the vertical write number counter 226 outputs the vertical write number signal V
WT is set to the high level “H”, and writing to the 3-port video memory 310 is stopped during the vertical effective scanning period (FIG. 9).
(E)). The stop of the writing is performed by the next vertical synchronization signal VS.
Continue until the STV reaches the high level "H".

As described above, in the present embodiment, the control signal output to the ADC 210 and the 3-port video memory 310 is controlled with respect to the simple flow of the signal, thereby realizing a smart video which has been conventionally difficult. it can.

In the above operation, the high level "H" is set to the active logic, but the same applies when the low level "L" is set to the active logic. Digitizing control unit shown in FIG.
The set value of each element 221 to 227 in the
To summarize the relationship with the processing contents in the
become that way. Horizontal writing dot clock generator 221
The set value corresponds to the dot clock given to the A / D converter 210.
The frequency of the clock signal CKAD is adjusted so that the dot
Clock signal CKAD and horizontal signal in video memory 310
The address update frequency (ie, the basic synchronization signal BSYN)
C frequency) to adjust the relative relationship
Determines the horizontal scale of the image represented by the image signal.
Set. Set value of vertical write line clock generator 224
Is also the vertical of the image represented by the image signal to be written.
Determine the reduction ratio in the vertical direction. Horizontal write start counter 2
The setting value of 22 is set on each line of the input image signal.
Start writing to the video memory 310 from the position
The set value of the horizontal write number counter 223 is
Image signals for several dots after the start of
310 is specified. Similarly, start vertical writing
The set value of the counter 225 is the vertical value of the input image signal.
Start writing to video memory 310 from any position in the direction
The vertical writing frequency counter 226
Shows how many lines of image signals have been
It specifies whether to write to the image memory 310. Vertical write off
The set counter 227 is a
Specifies the vertical start position of the embedded address range. What
Note that the vertical end position of the write address range is
Set value of direct write offset counter 227 and vertical write
It is defined by the set value of the number counter 226. Video memo
Start position of write address range in memory 310 in horizontal direction
Is the address input A provided by CPU 620.
It is defined by DD0 to ADD3. Write address range
The horizontal end position of the box is determined by the address input ADD0.
To ADD3 and setting of horizontal writing counter 223
It is specified by the value. In addition, each of these elements 221 to 22
7 is connected to the CPU 620 via the bus 610.
And the set value and address input AD in each of these elements
The value of D0 to ADD3 is the value within the processing in the digitizing control unit.
Der can be arbitrarily set by the CPU620 in accordance with the contents
You.

According to the present embodiment, the CPU 620 can easily operate any resolution, any aspect ratio, any area window display, and any multi-strobe still image, etc. of the video signal VSTV, and can be used for consumer equipment. Because it is easy to achieve low prices, PC TVs, intelligence terminals, video phones,
Other than video equipment such as a smart TV, an area designation monitoring system for a surveillance camera using a video or the like is also used.

CPU 620 to 3-port video memory 310
Performs the following operation when the device writes video data.
First, the CPU 620 controls the switching control signal CC of the writing control unit 340 to switch between the video data selection unit 320 and the video memory control signal selection unit 330. By this switching, the three-port video memory 310 stores the digitizing control unit 2
The write control signal WEPC output by the write control unit 340 is input instead of the write control signal WETV output by the control unit 20.

Luminance signal WLSP output from CPU 620
C is input to the 3-port video memory 310 via the write control unit 340 and the video data selection unit 320. 3-port video memory 310 by the write control signal WEP C output by the write control unit 340, the luminance signal WLSPC is written.

Next, the video data is read from the video memory 310.
Is read by the CPU 620, the luminance signal is transferred to the CPU 620 by DMA transfer in the 3-port video memory 310. FIG. 10 is a block circuit diagram of the 3-port video memory 310, the FIFO memory 360, the FIFO read control unit 370, and its peripheral circuits related to the DMA transfer. Incidentally, FIFO memory 360 may be have the same or more storage capacity and one line in the horizontal direction of the three-port video memory 310.

Next, an operation when the CPU 620 reads the luminance signal LSMEM stored in the three-port video memory 310 by DMA transfer will be described. First, C
The read control unit 350 controlled by the PU 620 outputs to the three-port video memory 310 scanning line information that is an offset value of the scanning line read from the three-port video memory 310.

The FIFO read control unit 370 stores the luminance data LSMEM of the designated scanning line in the 3-port video memory 31.
0 is a direct memory access (hereinafter referred to as DMA), and the luminance signal LSMEM is transferred to F which is an asynchronous I / O.
The data is transferred to the input port of the IFO memory 360. CPU6
20 is the luminance signal L transferred to the FIFO memory 360
The SMEM is read from the output port of the FIFO memory 360 via the read control unit 350 and the CPU bus 610.

In this embodiment, the personal computer and the personal computer monitor have been described as being separated from each other. However, the personal computer and the personal computer monitor can be implemented integrally.

Next, the operation of the DMA circuit shown in FIG. 10 will be described with reference to the timing chart of FIG.

(1) The FIFO read controller 370 outputs a horizontal clear signal HCLR2 for resetting the horizontal address of the 3-port video memory 310 to the 3-port video memory 31.
When output to 0 (see FIG. 11B), the 3-port video memory 310 is set to address 0 in the horizontal direction . At the same time as the output of the horizontal clear signal HCLR2, the FIFO read control unit 370 sets the reset signal FWR of the address of the input unit of the FIFO memory 360 (the horizontal clear signal HCLR2 to N).
The signal inverted by the OT circuit 372) is stored in the FIFO memory 36.
When it is output to 0 (see FIG. 11D), the write address of the FIFO memory 360 is set to address 0.

(2) Each time the clock signal CLK output from the FIFO read control unit 370 rises after the setting of the 3-port video memory 310 (see FIG. 11A), the 3-port video memory 310 outputs the luminance signal LSMEM. To data bus 3
71 via the output (see FIG. 11 (c)), FIFO memories 360 Komu read.

(3) Every time the clock signal CLK falls (see FIG. 11A), the three-port video memory 310
And the address of the FIFO memory 360 are incremented by one, and the luminance signal LSMEM is read from the 3-port video memory 310 and the FIFO memory 3 is read.
The writing of the luminance signal LSMEM to 60 is repeatedly executed.

(4) When DMA transfer by reading and writing of the luminance signal LSMEM is performed for one horizontal line , the FIFO read control unit 370 sets the horizontal clear signal HCL.
R2 and FRR signals are output and the 3-port video memory 31
0 and the address of the FIFO memory 360 are set to address 0, and the above-described operation is repeated. In this case, the clock signal CLK output from the FIFO read control unit 370 is 10 M
Hz or higher, so that the 3-port video memory 31
0 is used as the refresh timing.

Next, FIG. 12 shows a three-port video memory 310.
FIG. 10 is a circuit diagram of an offset circuit that sets an address of a FIFO memory 360 storing a luminance signal of the same to a predetermined address and reads a luminance signal LSFIFO from the FIFO memory 360. The operation of this offset circuit will be described with reference to the timing chart of FIG.

(1) The CPU 620 sets the read offset value N of the FIFO memory 360 in the read control unit 350 via the CPU bus 610.

(2) When the CPU 620 outputs a high-level “H” FIFO read memory reset signal PR (see FIG. 13B), the counter in the FIFO read control unit 350 and the read address in the FIFO memory 360 become 0. Address is set. The FIFO read memory reset signal RR outputs the FIFO read offset enable signal CST for starting the clock in the read control unit 350.
And the FIFO read offset end signal CEND for stopping the clock becomes low level “L” and the CPU 620
Is the FIFO memory 360 and the FIFO read control unit 350
And outputs a clock signal CLK for N clocks.

(3) The FIFO read controller 350 outputs the clock signal CLK for N clocks (see FIG. 13).
(See (a)), FIFO read offset end signal CEN
D is set to high level “H” (see FIG. 13D), and FI
The output of the clock signal CLK to the F0 memory 360 and the FIFO read control unit 350 is stopped. At this time,
The FIFO memory 360 outputs the luminance signal LSFIFO at address N to its output section as a DATA signal. Also FI
The FO read offset end signal CEND is also output to the CPU 620, and the CPU 620 outputs DATA by the high level “H” of the chip select / read signal RD / CS.
Read the signal.

(4) Chip select / read signal RD / C
When S becomes low level “L”, the FIFO memory 360
Is incremented by one. Since the clock signal CLK has a very high frequency of 10 MHz or more ,
The CPU 620 can read the luminance signal LSFIFO in an arbitrary area of the FIFO memory 360 very efficiently.

As described above, the three-port video memory 310
Output unit can be operated at 10 (MHz) or higher.
Therefore, the clock signal CLK is supplied to the 3-port video memory 31.
0PeculiarDynamic memory refresh timing
Can be used as Therefore, these are the expected
PC TV, intelligence end that can be an imaging device
Finally, it can be applied to devices such as TV phones.

The logic of the timing chart shown in FIG. 13 is an example for explanation, and the present invention is not limited to this.

In this embodiment, the transfer of the luminance data is described in a state where the personal computer main body and the personal computer monitor are separated from each other. However, the present invention can be applied to an apparatus in which the personal computer and the personal computer monitor are integrated.

Next, the superimpose control section 420 controls the 3-port video memory 310 and the DAC 410 to control the read control signal, the clock signal CKDA, and the video switch 510 based on the conditions controlled by the CPU 620.
Output a signal . The 3-port video memory 310 uses the read control signal RETV to update the updated luminance signal LSME.
M is read. The DAC 410 converts the luminance signal LSMEM read from the three-port video memory 310 into an analog signal LSDA and outputs the analog signal LSDA to the video switch 510.

The AND circuit 530 receives the superimpose permission signal output from the superimpose control section 420 and C
Mixing control unit 52 controlled by PU 620
AND of multiple superimpose permission signals output by 0
Take the conditions.

The video switch 510 is connected to an AND circuit 530
Switching is controlled based on the output signal of
The superimposed luminance signal LSDA output from the PC 10 and the personal computer body side luminance signal LSPC are output as a personal computer monitor luminance signal LSMON.

FIG. 14 is a block circuit diagram of the superimpose control 420 shown in FIG. 4 and its peripheral circuits. Note that the AND circuit 530 is omitted. or,
The 3-port video memory 310 is CXK manufactured by Sony Corporation as described above.
1206 or MB81C1501 manufactured by Fujitsu Limited.
Use the read port among the I / O ports. Data sheet number 71215 of Sony CXK1206
The timing chart is described on pages 27 to 31 of ST. The used port is read port 1 of two pages.

The 3-port video memory 310 uses the memory drive clock signal HDCK as the port 1 shift signal CKR1,
The memory vertical / horizontal reset signal MRST is applied to the port 1 vertical clear VCLR1, the horizontal reset signal HRST is applied to the port 1 horizontal clear HCLR1, and the vertical offset signal is applied.
VROFT or the vertical line clock signal VRLCK is input to the port 1 line increment INC1, and the port 1 output enable RE1 (negative logic) is input to the port 1 output enable RE1 (negative logic).

The luminance signal LSMEM is read from the port 1 data outputs DO10 to DO13. These port 1 shift signal CKR1, port 1 vertical clear VCL
R1, port 1 horizontal clear signal HCLR1, port 1 line increment signal INCL, port 1 output enable RE1 (negative logic), port 1 data output DO10
The luminance signal LSMEM to be read-controlled by D013
Is a 4-bit, that is, a 16-gradation monochrome luminance signal. It goes without saying that the luminance signal of 4 bits or more or a color signal is similarly replaced.

In FIG. 14, reference numeral 310 denotes a luminance signal LSM.
A 3-port video memory storing EM, 410 is a DAC for converting the luminance signal LSMEM into an analog signal and outputting a luminance signal LSDA, and 510 is a point A or a point B according to the switching signal CNT input to the switching signal input terminal. A video switch that outputs an input from a common point C, and 620 is a luminance signal LSPC, a horizontal synchronization signal HSPC, and a vertical synchronization signal V
CPU of a personal computer that outputs SPC; 610, CPU bus; 421, horizontal reference read dot clock signal HBDC
Horizontal reference read dot clock generator for outputting K, 42
Reference numeral 2 denotes a horizontal read start counter that outputs a horizontal read start A signal HRSA and a horizontal read direction reset signal HRST.
23 is a horizontal 64 for outputting a horizontal read start B signal HRSB
A clock counter 424, a horizontal read number counter for outputting a horizontal read number signal HRT, 425, a horizontal read dot clock generator for outputting a horizontal read dot clock signal HDDA, and 426, a count number of the horizontal reference read dot clock generator 421. It has a function that can be set arbitrarily by the CPU 620,
A memory vertical read offset counter that outputs an OFT,
427 vertical blanking number counter for outputting a vertical blanking end signal VBE, 428 start counter output vertical read outputs a start signal VRS out vertical read, 429 vertical read counter outputs a count signal VRT out vertical read,
430 is a vertical read line clock generator that outputs a vertical read line clock signal VRLCK, 431 is an AND circuit that outputs a superimpose enable signal SENBL,
432 is a vertical read offset signal VROFT and vertical read
Line increment signal VRLCK at port 1 line
OR circuit 43 for outputting as increment INC1 43
Reference numeral 3 denotes a NOR circuit that outputs the read enable signal RE1, 434 and 435 denote tristate circuits, and 436 denotes an inverter circuit.

The luminance signal LSPC output from the personal computer is
The signal is input to the point A of the video switch 510. The horizontal synchronizing signal HSPC is output from the horizontal reference read dot clock generator 4.
21, horizontal read start counter 422, horizontal 64 clock counter 423, horizontal read number counter 424, horizontal read dot clock generator 425, vertical blanking number counter 427, vertical read start count 428, vertical read number counter 429, vertical read line Clock generator 43
0 and a personal computer monitor (not shown).

A horizontal read start counter 422, a horizontal 64 clock counter 423, and a horizontal read number counter 424
Are reset by the horizontal synchronizing signal HSPC.

Further, the vertical synchronizing signal VSPC is the port 1 vertical clear VCLR1, N of the 3-port video memory 310.
OR circuit 433, vertical read offset counter 426,
The signals are input to a vertical blanking number counter 427, a vertical read start counter 428, a vertical read number counter 429, a vertical read line clock generator 430, and a personal computer monitor.

The vertical reading offset counter 426, the vertical blanking number counter 427, the vertical reading start counter 428, and the vertical reading number counter 429 are used for the vertical synchronization signal V.
The count value is reset by the SPC.

Horizontal reference read dot clock generator 421
Is synchronized with the horizontal synchronizing signal HSPC and the vertical synchronizing signal HS
It is composed of a PLL circuit that outputs a signal having a frequency several hundred times that of a PC, and outputs a horizontal reference read dot clock signal HBDCK corresponding to a horizontal dot clock signal of a personal computer monitor.

Horizontal reference read dot clock signal HBDC
K is a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read number counter 424, a vertical read offset counter 426, and a tristate circuit 43.
5, the clock signal H of the 3-port video memory 310
It is output to the port 1 shift signal terminal CKR1 of the 3-port video memory 310 as DCK.

The horizontal read dot clock generator 425 is composed of a PLL circuit which synchronizes with the horizontal synchronizing signal HSPC and outputs a signal having a frequency N1 times the frequency of the horizontal synchronizing signal HSPC.
Output DA.

The horizontal read dot clock signal HDDA is supplied to the 3-port video memory 3 via the tri-state circuit 434.
The port 1 shift signal terminals CKR1 and DAC4 of the three-port video memory 310 are used as ten clock signals HDCK.
10 and used as a read clock signal for the luminance signal LSMEM and a conversion clock signal for the DAC 410.

[0118] vertical read line clock generator 430 is synchronized with the vertical synchronizing signal VSPC, it is constituted by a P LL circuit for outputting a signal of N2 times the frequency of the vertical synchronizing signal VSPC, vertical read line clock signal VR
Output LCK.

The vertical read line clock signal VRLCK is synchronized with the clock signal HDCK of the three-port video memory 310, and the port 1 line which advances the line address which is the vertical address of the three-port video memory 310 via the OR circuit 432. Increment 1 NC1 and OR
The signal is output to the port 1 output enable RE1 (negative logic) via the circuit 432 and the NOR circuit 433.

The vertical read line clock signal VRLCK is synchronized with the clock signal HDCK of the three-port video memory 310, and the port 1 line which advances the line address which is the vertical address of the three-port video memory 310 via the OR circuit 432. Increment 1 NC1 and OR
The signal is output to the port 1 output enable RE1 (negative logic) via the circuit 432 and the NOR circuit 433.

The horizontal reference read dot clock signal H
The basic timing of the superimpose circuit 420 is obtained by the BDCK, the horizontal read dot clock signal HDDA, and the vertical read line clock signal VRLCK.

The vertical read offset counter 426 determines the read start offset point of the 3-port video memory 310, and after the count value is reset by the vertical synchronization signal VSPC, the horizontal reference read dot clock generator 42.
1 output horizontal reference read dot clock signal HBDC
A vertical offset signal VR for adding a vertical line address of the 3-port video memory 310 while synchronizing with K
Output OFT .

[0123] vertical blanking number counter 427 counts the number of clocks counter of the horizontal synchronizing signal HSPC for deleted vertical back porch region of the luminance signal LSPC, past the vertical back porch area vertical blanking
And it outputs the ring end signal VBE.

The vertical read start counter 428 has a vertical blank
The vertical signal which is a permission signal output from the king number counter 427.
In response to the output of the blanking end signal VBE, the number of clocks of the horizontal synchronization signal HSPC is counted, and a vertical read start signal VRS, which is a read start permission signal from the 3-port video memory 310 in the vertical direction, is output.

The vertical reading counter 429 is a luminance signal V which is a permission signal output from the vertical reading start counter 428.
The number of clocks of the horizontal synchronizing signal HSPC is counted by the output of the RS, and a vertical reading frequency signal VRT which is a reading period in the vertical direction from the 3-port video memory 310 is output.

A vertical read offset counter 426, a vertical blanking number counter 427, a vertical read start counter 428, and a vertical read number counter 429 form a three-point counter.
The vertical control of the video memory 310 is performed.

The vertical reading offset counter 426
Horizontal read dot clock signal HBD counted by
CK clock number, vertical blanking number counter 427
, The number of clocks of the horizontal synchronization signal HSPC counted by the vertical read start counter 428, and the number of clocks of the horizontal synchronization signal HSPC counted by the vertical read start counter 428
The clock number of the horizontal synchronization signal HSPC counted by
The PU 620 can be set to each arbitrary value.

The horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421, and outputs a read start permission signal for the horizontal direction of the 3-port video memory 310 in the horizontal direction. A horizontal read start A signal HRSA is output.

The horizontal 64 clock counter 423 outputs the horizontal read start A signal HRSA, which is a permission signal output from the horizontal read start counter 422, and outputs the reference dot clock signal HBDCK clock number output from the horizontal reference read dot clock generator 421. When the count value reaches 64 clocks, which is the characteristic when reading out from the 3-port video memory 310, a horizontal read start B signal HRSB is output.

The horizontal reading counter 424 counts the number of clocks of the reference dot clock signal HBDCK output from the horizontal reference reading dot clock generator 421, and is a horizontal reading signal which is a permission signal of a reading period in the horizontal direction of the 3-port video memory 310. The frequency signal HRT is output.

Horizontal read start counter 422, horizontal 64 clock counter 423, and horizontal read number counter 424
Thus, the horizontal control of the three-port video memory 310 is performed.

The horizontal reference read dot clock signal HBDCK counted by the horizontal read start counter 422
The CPU 620 can set the number of clocks and the number of clocks of the reference dot clock signal HBDCK counted by the horizontal read number counter 424 to arbitrary values. 14th
Elements 421 to 421 in the superimpose control unit shown in the figure
430 and the superimpose controller
The following summarizes the relationship with the processing contents in
You. The set value of the horizontal read dot clock generator 425 is
Dot clock signal H applied to D / A converter 410
Adjust the frequency of the DDA, and as a result,
Of the horizontal address in the HDDA and the video memory 310
Update frequency (ie, horizontal reference dot clock signal HB
DCK frequency) and read out
Horizontal scaling factor of the image represented by the image signal
To determine. The setting of the vertical read line clock generator 430
The constant value is also the image represented by the read image signal.
Determine the vertical scaling factor for. Start horizontal reading
The set value of the counter 422 is read and the image signal is displayed.
Defines where to display on each line of the device
The set value of the horizontal read number counter 424 is
Image signals for how many dots have passed since the start of
Specifies whether to read from 0 and display. Similarly, vertical
The set value of the read start counter 428 is the value of the image to be read.
Where the signal is displayed in the vertical direction of the display device
And the set value of the vertical read counter 429 is
The video signal for several lines after starting
Stipulates whether to read from the file 310 and display it. Vertical reading
The output offset counter 426 is stored in the video memory 310.
The vertical start position of the read address range
You. Note that the vertical end position of the read address range is
The set value of the vertical read offset counter 426 and the vertical
It is defined by the set value of the direct reading number counter 429. Movie
The read address range of the image memory 310 in the horizontal direction
The starting position is an address given by the CPU 620.
It is defined by the inputs ADD0 to ADD3. Read address
The horizontal end position of the address range is determined by the address input A
DD0-ADD3 and horizontal reading counter 424
And set value. Each of these elements 42
2,424～426,428 to 430 is, the bus 610
These components are connected to the CPU 620 via
Set value and the value of address input ADD0-ADD3
Depends on the processing in the superimpose control unit.
It can be arbitrarily set by the CPU 620.

Next, the operation of the superimpose control section 420 will be described with reference to FIGS. 15, 16, 17 and 18. FIG. 15 shows a 3-port video memory 3
FIG. 16 is a timing chart of vertical offset of the three-port video memory 310, FIG. 17 is a timing chart of horizontal read permission of the three-port video memory 310, and FIG. FIG. 18 is a timing chart of horizontal reading of the 3-port video memory 310.

First, the vertical read permission of the three-port video memory 310 will be described with reference to FIG. When the vertical synchronizing signal VSPC becomes high level “H” (FIG. 1)
5 (a)), a vertical blacking number counter 427,
The vertical read start counter 428 and the vertical read number counter 429 are reset, and the vertical blanking end signal VB
E, vertical read start signal VRS and vertical read number signal VR
T becomes low level "L", respectively (FIG. 15)
(D), (e), (f), reference), counts the number of clocks of the vertical blanking number counter 427 is a horizontal synchronizing signal HSPC, past the vertical back porch area perpendicular Bra
The locking end signal VBE is set to the high level “H” (see FIG. 15D).

When the vertical blanking end signal VBE becomes high level "H", the vertical read start counter 428 starts counting the number of clocks of the horizontal synchronizing signal HSPC. When the vertical read start counter 428 counts the value set by the CPU 620, it sets the vertical read start signal VRS to a high level “H” (see FIG. 15E).

When the vertical read start signal VRS becomes high level "H", it means that the start of reading of the luminance signal LSMEM in the vertical direction of the three-port video memory 310 has been permitted. 429
Starts counting the number of clocks of the horizontal synchronization signal HSPC. When the vertical reading number counter 429 counts the value set by the CPU 620, the vertical reading number signal VRT is set to the high level “H” (see FIG. 15F).

The AND circuit 431 outputs the horizontal read start B signal H
When the RSB is at the high level “H” and the horizontal read count signal HRT is at the low level “L”, the vertical read start signal VR
S is at the high level “H”, and the vertical read number signal VRT
High level “H” only during the period when is low level “L”
Output the superimpose permission signal SENBL.
Therefore, the luminance signal LSMEM is read from the three-port video memory 310 based on the read permission in the horizontal direction.

Next, the vertical offset of the 3-port video memory 310 will be described with reference to FIG. When the vertical synchronizing signal VSPC becomes high level “H” (FIG. 16)
(See (a)), the vertical read offset counter 426 is reset, and starts counting the number of clocks of the reference dot clock signal HBDCK.

The vertical read offset counter 426 sets the CP
While counting the value set in U620, the vertical read offset signal VROFT is output to the port 1 line increment INC1 of the 3-port video memory 310 via the OR circuit 432 (see FIG. 16 (c)). The vertical line of the memory 310 is offset.

At this time, since the vertical synchronizing signal VSPC and the vertical reading offset signal VROFT have been input to the NOR circuit 433, the read enable signal RE1 (negative logic) is also set to the read enable R of the three-port video memory 310.
It is output to E1 (negative logic).

Next, a description will be given of the horizontal read permission of the three-port video memory 310 with reference to FIG.
When the horizontal synchronization signal HSPC is output, the horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read number counter 424 are reset, and the horizontal read start A signal HRSA, the horizontal read start B signal HRSB, and the horizontal read number signal HRT are reset. Becomes low level "L" (Fig. 1
7 (d), (e), (f), see).

The horizontal read start counter 422 counts the number of clocks of the reference dot clock signal HBDCK output from the horizontal reference read dot clock generator 421 (FIG. 17).
When the count value reaches the value set by the CPU 620, the horizontal read start A signal HRSA is set to the high level “H” (see FIG. 17D).

When the horizontal read start A signal HRSA goes high, the horizontal 64 clock counter 423 starts counting the number of clocks of the reference dot clock signal HBDCK. The signal HRSB is set to the high level “H” (FIG. 17)
(E)). The horizontal 64 clock counter 423
Is caused by the characteristics of the 3-port video memory 310, and 6
It is not limited to four.

When the horizontal read start B signal HRSB becomes high level "H", horizontal read of the 3-port video memory 310 is permitted, and the horizontal read counter 424 counts the number of clocks of the reference dot clock signal HBDCK. Is started, and the count value is
, The horizontal read count signal HRT is set to the high level “H” (see FIG. 17F).

The AND circuit 431 operates as a vertical read start signal VR.
S is at the high level “H”, and the vertical read number signal VRT
Is at the low level "L", the horizontal read start B signal HRSB is at the high level "H", and only during the period when the horizontal read count signal HRT is at the low level "L", the super-level signal of the high level "H" is output. The pause enable signal SENBL is output. Therefore, the luminance signal LSMEM is read from the three-port video memory 310 based on the vertical read permission.

Next, reading of the three-port video memory 310 in the horizontal direction will be described with reference to FIG. The superimpose permission signal SENBL becomes high level “H” (see FIG. 18C), and based on the clock of the horizontal read dot clock signal HDDA output from the horizontal read dot clock generator 425 (see FIG. 18B). ) Luminance signal LSM from 3-port video memory 310
This also shows the read enable signal RE1 when the reading of the EM and the analog conversion of the DAC 410 are performed.

The luminance signal LSPC of the personal computer is input to the point A of the video switch 510. The luminance signal LSDA read from the three-port video memory 310 and converted by the DAC 410 into an analog signal is input to a point B of the video switch 510. By switching the video switch 510,
Luminance signal LSMON output from video switch 510
Is output as a luminance signal LSMOM corresponding to a superimposed image of an image corresponding to the analog-converted luminance signal LSDA in an image corresponding to the luminance signal LSPC output from the personal computer. Note that the luminance signal LSM
Along with the output of ON, the horizontal synchronizing signal HSPC and the vertical synchronizing signal VSPC are also output to the personal computer monitor.

Note that the above-described timing chart is an example, and the above-described operation can be performed even when each signal is positive logic or negative logic.

In FIG. 14, the high level "H"
Is output to the trislate circuit 434 via the NOT circuit 436, the tristate circuit 434 operates to output the horizontal read dot clock signal HDDA as the drive clock signal HDCK, Superimpose permission signal S
When ENBL is at the low level “L”, the tri-state circuit 435 operates to generate the reference dot clock signal HBD.
CK is output as the drive clock signal HDCK.
As described above, the luminance signal read from the video memory 310 is
The image of the signal LSMEM is represented by the luminance signal LSPC.
Super import at any position in the video at any size
Can be

According to the present invention, the superimposition control unit 420 is provided in the intelligent terminal and the consumer television.
Can easily superimpose video from videophones, interphones, etc., so that videophones and interphones without a monitor can be realized. Naturally, as a personal computer television, a baseball broadcast on the same monitor while operating a word processor To enjoy the video, education with real images by CAI, stress prevention measures for VDT workers,
It also conveys a step toward realization of a new software-type computer by controlling video freely in the computer, such as a video monitoring system on the computer.

Next, FIG. 19 is a block diagram of a circuit for multiplex superimposing a luminance signal. The luminance signal LSPC output from the personal computer is output to the video switch 510 and the voltage comparator 540. The voltage comparator 540 outputs a high level “H” when the luminance signal LSPC is higher than the reference voltage Vr, and a low level “L” when the luminance signal LSPC is lower than the reference voltage Vr.
MP is output to the NAND circuit 450. Further, the superimpose control section 420 outputs a permission signal CENBL for enabling the comparison signal COMP to the NAND circuit 450.

The NAND circuit 450 outputs the low-level "L" permission signal NE only when the comparison signal COMP is at the high level "H" and the permission signal CENBL is at the high level "H".
Output NBL.

The AND circuit 451 is a 3-port video memory 3
10, a permission signal SENBL for permitting the superimposition of the luminance signal LSDA with the luminance signal LSPC by the DAC 410 and a permission signal SSENBL for permitting the luminance signal LSPC to superimpose the luminance signal LSDA. And a permission signal NENBL output from the NAND circuit 450.

The video switch 510 has a luminance signal LSPC
The video signal LSDA is superimposed by the switching signal CNT output from the AND circuit 451. When the level of the luminance signal LSPC occurs while the luminance signal LSDA is superimposed in the luminance signal LSPC, the output signal COMP of the voltage comparator 450 becomes high level “H”. Ha this time, the superimpose control unit 420 permission signal CENBL the NAND circuit 450
Output “H” , the NAND circuit 450
Outputs a low-level “L” permission signal NENBL, and A
The switching signal CNT output from the ND circuit 451 is the luminance signal L
It becomes low level "L" only during the level period of SPC. Therefore, the luminance signal LSPC is superimposed on the luminance signal LSMON of the personal computer monitor in the luminance signal LSDA.

FIG. 20 is a timing chart showing the operation of FIG. The permission signal SENBL and the permission signal C
ENBL is at a high level “H”. The luminance signal LSMON of the personal computer monitor obtained by these (FIG. 20)
(See (i)) is obtained by superimposing the luminance signal (see FIG. 20 (b)) LSDA on the luminance signal LSPC (see FIG. 20 (a)) and generating the luminance signal LSPC during the scanning of the luminance signal LSDA. Character signal, special shape video signal LS
In addition it will be allowed to superimpose into the DA.

It goes without saying that the above-described operation is established irrespective of positive logic or negative logic. The AND circuit 451 and the NAND circuit 450 are an OR circuit and an AND circuit.
It is a simple circuit that can be easily realized and applied to all circuits having a switch function such as a path, a multiplexer, and an analog switch. For example, the NAND circuit 450 is AND times
If the output signal COMP is at the high level "H"
Only during the period, the luminance signal LSDA can be superimposed.

It is general that the luminance signal LSPC is superimposed with the luminance signal LSDA. However, superimposing the luminance signal LSPC within the luminance signal LSPC takes a very long time. This is not possible when LSDA is a moving image. But,
Characters and special shapes to be displayed in the luminance signal LSDA as in the present invention are output to the luminance signal LSPC at the same position of the luminance signal LSDA, and only the level portion of the luminance signal LSPC is released from the superimposition of the luminance signal LSDA. By simply doing so, conventionally, there is no problem even with the moving image of the luminance signal LSDA, and it can be realized with a very simple circuit,
It is indispensable for future video processing circuits.

[0158]

As described above, according to the present invention, dynamic
There is an effect that a plurality of images including an image can be displayed while being synthesized .

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is an external view of the image processing apparatus shown in FIG.

FIG. 3 is an external view of a main body of the personal computer in which the expansion slot card shown in FIG. 2 is incorporated.

FIG. 4 is a detailed block circuit diagram of a main part of the image processing apparatus shown in FIG. 1;

FIG. 5 is a connection diagram between the expansion slot card and the tuner shown in FIG. 2;

FIG. 6 is an operation explanatory view of the image processing apparatus shown in FIG. 1;

FIG. 7 is a memory map.

FIG. 8 is a circuit diagram of a digitizing control unit and its peripheral circuits shown in FIG. 4;

FIG. 9 is a timing chart showing operations of the digitizing control unit and its peripheral circuits shown in FIG. 4;

FIG. 10 is a circuit diagram of the DMA circuit shown in FIG. 4;

11 is a timing chart showing the operation of the DMA circuit shown in FIG.

FIG. 12 is a circuit diagram of an offset circuit.

13 is a timing chart showing the operation of the offset circuit shown in FIG.

FIG. 14 is a circuit diagram of a superimpose control unit and its peripheral circuits shown in FIG. 4;

FIG. 15 is a timing chart showing the operation of the superimpose control unit and its peripheral circuits.

FIG. 16 is a timing chart showing the operation of the superimpose control unit and its peripheral circuits.

FIG. 17 is a timing chart showing the operation of the superimpose control unit and its peripheral circuits.

FIG. 18 is a timing chart showing the operation of the superimpose control unit and its peripheral circuits.

FIG. 19 is a circuit diagram of a multiplex superimpose control unit.

FIG. 20 is a timing chart showing the operation of the multiplex superimpose control unit shown in FIG. 19;

FIG. 21 is a block diagram of a conventional image processing apparatus.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 video decoder 101 audio signal terminal 102 audio signal terminal 103 video signal terminal 110 audio signal selection circuit 120 volume control circuit 130 video signal selection circuit 140 ... video signal decoder 200 ... ADC control unit 210 ... ADC 220 ... digitizing control unit 221 ... horizontal writing dot clock generator 222 ... horizontal writing start counter 223 ... Horizontal writing number counter 224 ... Vertical writing line clock generator 225 ... Vertical writing start counter 226 ... Vertical writing start counter 227 ... Vertical writing offset counter 228 ... NOA circuit 229 ··· AND circuit 230 ··· OR circuit 300 ··· 3 port video memory controller 310 ··· 3 port video memory 20 ... video data control circuit, 330 ... video memory control signal selecting circuit 340 ... write control unit 360 ... FIFO memory 370 ... FIFO read control unit 350 ... read control unit 400, .. DAC control unit 410 DAC 420 superimpose control unit 421 horizontal reference read dot clock generator 422 horizontal read start counter 423 horizontal 64 clock counter 424 Horizontal reading number counter 425: Horizontal reading dot clock generator 426 ... Vertical reading offset counter 427 ... Vertical blacking number counter 428 ... Vertical reading start counter 429 ... Vertical reading number counter 430 ... -Vertical read line clock generator 431 ... AND circuit 432 ... OR circuit 4 33 NOR circuit 434, 435 Tristate circuit 436 Inverter circuit 450 NAND circuit 451 AND circuit 500 Image mixing control unit 510 Video switch 520 ... mixing control unit 530 ... AND circuit 540 ... voltage comparator 600 ... CPU control unit 610 ... data bus (CPU bus) 620 ... CPU 700 ... personal computer body 701 ...・ PC monitor 702 ・ ・ ・ Keyboard 703 ・ ・ ・ Mouse 704 ・ ・ ・ Expansion slot card 705 ・ ・ ・ Video cable between main units 706 ・ ・ ・ Video cable between monitors 710 ・ ・ ・ Tuner 711 ・ ・ ・ Antenna 712 ・ ・ ・Tuner control connector 713, 714, 715 ... output connector 716 ... plug 717: Headphone, VSTV: Video signal of tuner LSTV: Luminance signal of tuner SSTV: Synchronization signal of tuner HSTV: Horizontal synchronization signal of tuner VSTV: Horizontal synchronization signal of tuner ASTV: Tuner .. VTR video signal ASEX... VTR sound signal DIN0, DIN1, DIN2, DIN3... Port 0 data input ADD0, ADD1, ADD2... Address input INC0. ··· Port 0 horizontal clear VCLR0 ··· Port 0 vertical clear WE (negative logic) ··· Port 0 write enable LSMEM ··· Memory luminance signal CKR1 ··· Port 1 shift signal VCLR1 ··· Port 1 Vertical clear HCLR1 port Horizontal clear INC1 ... port 1 line increment RE1 (negative logic) ... port 1 output enable D010, D011, D012, D013 ·· port 1
Data output LSPC ··· PC brightness signal HSPC ··· PC horizontal synchronization signal VSPC ··· PC vertical synchronization signal ASMON ··· Monitor audio signal VSMON ·· Monitor video signal LSMON ·· Monitor brightness signal WETV, WEPC: Video memory control signal Vr: Reference voltage HDCK: Horizontal write dot clock signal HWS: Horizontal write start signal HWT: Horizontal write count signal VWS: Vertical write start Signal VWT: Vertical write count signal WENBL: Write enable signal VWLCK: Vertical write line clock signal VWOFT: Vertical write offset signal WE: Write enable signal BSYNC: Basic synchronization signal CC: switch control signal of write control circuit HBDCK: horizontal reference read dot clock signal HR A: Horizontal read start A signal HRST: Memory horizontal reset signal HRSB: Horizontal read start B signal HRT: Horizontal read count signal HDDA: Horizontal read dot clock signal VROFT: Vertical read offset signal VBE ··· Vertical blanking end signal VRS ··· Vertical read start signal VRT ··· Vertical read count signal VRLCK ··· Vertical read line clock signal SENBL ··· Superimpose enable signal LSDA ··· Luminance signal HDCK ··· Memory drive Clock signal MRST Memory vertical / horizontal reset signal HRSP Horizontal sync signal VSPC Vertical sync signal SENBL Permit signal SSENBL Permit signal CENBL Permit signal COMP Permit signal NENBL・ ・ ・ Enable signal CNT ・ ・ ・Signal

 ──────────────────────────────────────────────────続 き Continuation of the front page (31) Priority claim number Japanese Patent Application No. 63-331876 (32) Priority date December 28, 1988 (33) Priority claim country Japan (JP) (31) Priority Claim number Japanese Patent Application 63-331878 (32) Priority date December 28, 1988 (33) Priority country Japan (JP) (31) Priority claim number Japanese Patent Application No. 1-28430 (32) Priority Japan 1 (1989) February 7, 1989 (33) Countries claiming priority

Claims (10)

(57) [Claims] 1. A fraction obtained by combining a plurality of images on a display device
A method of displaying an image, and storing the steps of receiving a first image signal representing the first image, in synchronization with the first synchronizing signal, said first image signal to the video memory, Reading the first image signal from the video memory while enlarging / reducing at an arbitrary magnification including a non-integer in synchronization with a second synchronization signal given to the display device; and Out of a plurality of image signals including the first image signal read from the video memory and the second image signal given from the display control unit in synchronization with
By switching and selecting one of them, a third one representing a composite image of the images represented by the first and second image signals is obtained.
Comprising a step of generating an image signal, by supplying said third image signal and the second synchronization signal to said display device, a step of displaying the composite image on the display device, wherein the The step of reading out the first image signal includes the step of reading the second image signal.
Frequency of horizontal synchronization signal included in signal and video memory
Relative to the update frequency of the read line address given to
By adjusting the relationship, the first image signal is
An image processing method comprising a step of enlarging / reducing at an arbitrary magnification in a direction . 2. The image processing method according to claim 1, wherein the step of storing the first image signal in the video memory includes the step of scaling the first image . 3. A picture that combining a plurality of images on a display device
An apparatus for displaying an image, means for receiving a first image signal representing the first image and the first synchronizing signal, a video memory for storing the first image signal, the first A first controller that controls writing of the first image signal to the video memory in synchronization with a synchronization signal of the video memory, and a first controller that controls writing of the first image signal to the video memory in synchronization with a second synchronization signal provided to the display device. A second controller for controlling an operation of reading the first image signal while enlarging / reducing at an arbitrary magnification including a non-integer, and reading the first image signal from the video memory in synchronization with the second synchronization signal 1 from a plurality of image signals and a second image signal supplied from said first image signal and the display control unit
By switching and selecting one of them, a third one representing a composite image of the images represented by the first and second image signals is obtained.
And a video switch for generating the image signal of the second image signal and supplying the third image signal to the display device , wherein the second controller is included in the second synchronization signal.
And the frequency of the horizontal synchronization signal given to the video memory.
The relative relationship between the read line address and the update frequency
The first image signal in the vertical direction.
An image processing apparatus comprising means for enlarging / reducing at a magnification of . 4. The image processing apparatus according to claim 3, wherein the first controller includes means for scaling the first image . 5. A picture obtained by combining a plurality of images on a display device
A method of displaying an image, comprising the steps of receiving a first analog image signal representing the first image and the first synchronization signal, in synchronization with the first synchronizing signal, the first analog picture
The first digital image is obtained by A / D converting the image signal.
And generating an image signal, in synchronization with the first synchronizing signal, the first digital image
Storing the image signal in a video memory; and enlarging or reducing the first digital image signal from the image memory at an arbitrary magnification including a non-integer in synchronization with a second synchronization signal provided to the display device. Reading the first digital image signal read from the video memory in synchronism with the second synchronization signal, and generating a second analog image signal by DA conversion. And the second analog image in synchronization with the second synchronization signal.
One of a plurality of analog image signals including an image signal and a third analog image signal provided from the display control unit is cut off.
By selecting while Rikae, the second and generating a fourth analog image signal representing a composite image of the image represented by the third analog image signal, said fourth analog image signal and the second by the the synchronizing signal supplied to said display device, said synthetic image
Comprising a step of displaying an image on the display device, the step of reading the first digital image signal, said first
2 and the frequency of the horizontal sync signal included in the sync signal.
Update frequency of readout line address given to image memory
Adjusting the relative relationship with the first digital
Enlarge / reduce the image signal vertically at any magnification
An image processing method comprising: 6. The image processing method according to claim 5, wherein the step of storing the first digital image signal in the video memory includes the step of scaling the first image . 7. A picture obtained by combining a plurality of images on a display device
An apparatus for displaying an image, means for receiving a first analog image signal representing the first image and the first synchronous signal, first by the first analog image signal to convert A-D 1 of the a-D converter to generate a digital image signal, a video memory for storing the first digital image signal, in synchronization with the first synchronizing signal, the first to the video memory A first controller for controlling writing of a digital image signal, and synchronizing with a second synchronization signal provided to the display device, synchronizing the first digital image signal from the video memory with an arbitrary magnification including a non-integer. A second controller that controls a read operation while enlarging / reducing, the first digital image read from the video memory;
The second analog image is obtained by DA conversion of the image signal.
A DA converter that generates an image signal; and the second analog image in synchronization with the second synchronization signal.
One of a plurality of analog image signals including an image signal and a third analog image signal provided from the display control unit is cut off.
By selecting while Rikae, the second and the third to generate a fourth analog image signal representing a composite image of the image expressed by the analog video signal, said fourth analog picture
A video switch for supplying an image signal to the display device , wherein the second controller is included in the second synchronization signal.
And the frequency of the horizontal synchronization signal given to the video memory.
The relative relationship between the read line address and the update frequency
The first digital image signal in the vertical direction.
An image processing apparatus comprising means for enlarging / reducing at an arbitrary magnification in the direction . 8. The image processing method according to claim 7, wherein the first controller includes a unit that scales the first image . 9. A computer system, comprising:  A display control unit for controlling a display device;No. OneimageThe first representingimageSignal and the first synchronization signal
Means for receiving, the firstimageA video memory for storing a signal; and synchronizing with the first synchronization signal,
FirstimageFirst control for controlling signal writing
La andGiven to the display device Synchronized with the second synchronization signal
From the video memoryimageScale the signal
Controller for controlling reading while reading
Reading from the video memory in synchronization with the second synchronization signal.
The firstimageFrom the signal and the display control unit.
The second obtainedimageIncluding multiple signalsimageIn the signal
OneWhile switchingBy selecting, the first
And the secondimageRepresented by a signalimageSynthesis ofimageRepresents
ThirdimageGenerating a signal, the thirdimageThe signal is
And a video switch for supplying to the display device., The second controller is included in the second synchronization signal.
And the frequency of the horizontal synchronization signal given to the video memory.
The relative relationship between the read line address and the update frequency
The first image signal in the vertical direction.
Equipped with means for enlarging / reducing at a magnification of Computer system. 10. A computer system, comprising:  A display control unit for controlling a display device;No. OneimageA first analog representingimageSignal and the first
Means for receiving the first analog signal and the first analog signal.imageA / D conversion of the signal
What is the first digitalimageA / D converter for generating a signal
And the first digitalimageVideo memo for storing signals
In synchronization with the first synchronization signal,
The first digitalimageThe first command for controlling the writing of signals
Controller andGiven to the display device Synchronized with the second synchronization signal
From the video memory to the first digitalimageSignal
Read operation while scaling at any magnification including non-integer
A second controller for controlling the operation, and the first digital read from the video memoryPicture
imageThe second analog signal is obtained by DA conversion of the signal.Picture
imageA D / A converter for generating a signal; and the second analog signal in synchronization with the second synchronization signal.Picture
imageSignal and a third analog provided from the display control unit
imageMultiple analog signals andimageOne of the signals
ToWhile switchingBy selecting the second and third
AnalogimageRepresented by a signalimageSynthesis ofimageRepresents
The fourth analogimageGenerating a signal;
TheimageA video switch for supplying a signal to the display device.
And, The second controller is included in the second synchronization signal.
And the frequency of the horizontal synchronization signal given to the video memory.
The relative relationship between the read line address and the update frequency
The first digital image signal in the vertical direction.
Equipped with means for enlarging / reducing at any magnification in the Computer system.