JP2591262B2 - Video processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing device that superimposes another video screen on a part of one video screen.

[Conventional technology]

In the field of so-called personal computers (personal computers), image processing called picture-in-picture in which television images and the like are superimposed and displayed on personal computer images has come to be performed. That is, an image processing apparatus that is interposed between a personal computer and a personal computer monitor and displays a part or all of an external image signal on a personal computer image screen is being developed.

Generally, a 2: 1 interlaced video signal is used as an external video signal. This is performed by scanning every other scanning line from the top to the bottom of the screen, returning to the top again, and then skipping first. This is a signal based on a method of scanning a scanning line. In this case, a screen composed of every other scanning line is called a field, and a completely scanned screen composed of two consecutive fields (a first field and a second field) is called a frame.

FIG. 5 is a conceptual diagram showing the relationship between the framed fields. FIGS. 5 (a) and 5 (b) show the first field and the second field, respectively, and FIG. 5 (c) shows the first field. 2 and a frame composed of the second field.

[Problems to be solved by the invention]

By the way, in performing picture-in-picture video processing, in order to obtain a high-quality video, the video may be superimposed on a frame basis. However, in order to extract the video signal in frame units from the 2: 1 interlace signal, this signal is stored in a separate storage device for each field, and then the field signal is extracted from each storage device and mixed as a frame. There must be. Image processing for arbitrarily enlarging or reducing a video signal in the vertical direction is performed on a video signal for each field stored in a storage device before mixing, but management of the video signal in this process is complicated and difficult. Was.

Also, the video signal input to the storage device is transferred to an external CPU.
For example, in order to read in frame units, it is difficult to read the video signals of the first field and the second field alternately for each line.

An object of the present invention is to solve such a problem.

[Means for solving the problem]

In order to solve the above problems, an image processing apparatus according to the present invention includes an A / D conversion unit that quantizes a luminance signal of a first video signal and converts the quantized signal into a digital luminance signal; A video storage means for storing a signal; a mixing means for partially replacing a screen based on the luminance signal of the second video signal with a screen based on a digital luminance signal from the video storage means; And a control means for controlling each means based on a command indicating how to enlarge or reduce the screen by the luminance signal of the first video signal. One screen (field) is a 2: 1 interlace signal in which one complete screen (frame) is formed. The control means stores each line of the first field video signal in the video storage means. Is intended to be stored in between the lines of each line of the second field image signal is the first field video signal are stored together is stored in jumps in-intervals.

[Action]

If it is a video memory signal written in this way,
It is possible to read out without being aware of the video signal of the first field or the video signal of the second field, that is, in frame units. Therefore, arbitrary enlargement / reduction of the video signal can be easily performed at the time of reading.

〔Example〕

FIG. 1 is a block diagram of a video processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a connection relationship between the video processing device and a personal computer and a personal computer monitor.

The video processing device 1 is a personal computer 2 that receives a personal computer video signal 3 (RGB luminance signal and vertical
(Horizontal synchronization signal) and an NTSC composite video signal 5 coming from a video input terminal 4. Then, the video processing device 1 combines these two video signals, and outputs a video signal 8 in which the screen 7 of the NTSC composite video signal 5 is inserted into the screen 6 of the personal computer video signal 3 to the personal computer monitor 9. How to insert the screen 7 into the screen 6 is performed based on a command 10 from the personal computer 2 by extracting a desired portion from the screen of the video signal or enlarging the extracted screen. . The NTSC composite video signal 5 is supplied to a video input terminal 4 from a TV tuner, a VCR, or the like (not shown).

Next, the internal configuration of the video processing device 1 will be described. The video signal decoder 21 receives the NTSC composite video signal 5 from the video input terminal 4 and extracts an RGB luminance signal 23, a horizontal synchronizing signal, a vertical synchronizing signal, and an odd / even discrimination signal from the NTSC composite video signal 5. The odd / even discrimination signal is a signal synchronized with the first field signal and the second field signal. For example, if the odd / even discrimination signal is at the high level “H” while the NTSC composite video signal 5 is applying the first field signal, the NTSC composite video signal 5 changes from the first field signal to the second field signal. At the timing, the odd / even discrimination signal is inverted from the high level “H” to the low level “L”.

The A / D converter (ADC) 22 quantizes the RGB luminance signal 23 coming from the video signal decoder 21 at the timing of the clock signal CKAD from the memory write control unit 24, and converts it into a digital RGB luminance signal 25. Image memory 26 has 960 rows x 360 columns x 4
It has a bit configuration, which is provided for each of R, G, and B colors.

The memory write control unit 24 outputs the clock signal CKAD to the ADC 22 and outputs the write control signal WETV to the video memory 26. The clock signal CKAD is a signal synchronized with the horizontal synchronization signal from the video signal decoder 21, and has a period of 1 / N (a positive integer of N) of the period (for example, 63.5 μs) of the horizontal synchronization signal. The write control signal WETV is a signal for permitting the writing of the digital RGB luminance signal 25 coming from the ADC 22, and is a set of a plurality of control signals. The internal configuration of the memory write control unit and a specific example of the write control signal WETV will be described later with reference to FIG.

The memory read control unit 27 controls reading of the video stored in the video memory 26. This memory read control unit 27 is configured to
A read control signal is sent to the video memory 26, and the D / A converter (DA
C) Send the clock signal CKDA to 28. The read control signal is a signal for controlling reading of a digital RGB luminance signal from the video memory 26. Although a specific form of the read control signal is omitted here, it is usually a set of a plurality of control signals. For example, a signal for designating or incrementing a pixel address for reading on the storage screen of the video memory 26, a control signal for permitting reading in pixel units, and reading of only a desired area in the horizontal direction (line) of the storage screen. The control signal includes an enable control signal, a control signal for allowing only a desired area to be read in the vertical direction, and the like. All of these control signals are generated based on whether or not the read basic synchronization signal generated inside the memory read control unit 27 is counted and the count value has reached a set value set for each control signal. Things. These setting values can be adjusted based on a command from the personal computer 2.

DAC 28 is a digital RGB read from video memory 26
The luminance signal 29 is sampled at the timing of the clock signal CKDA and converted into an analog RGB luminance signal 30. A video signal input terminal 31 is supplied with a personal computer video signal 3 coming from the personal computer 2 and is input as an RGB luminance signal 35, a horizontal synchronization signal and a vertical synchronization signal for a processed video signal. The horizontal synchronization signal and the vertical synchronization signal are independent of the horizontal synchronization signal and the vertical synchronization signal of the NTSC composite video signal 5. The video signal output terminal 32 is connected to the RGB luminance signal 34 from the video switch 33 and the video signal input terminal 3
1 is a terminal for outputting a horizontal synchronization signal and a vertical synchronization signal from the video signal output terminal 1. The video signal 8 (RG
B luminance signal and synchronization signal) are supplied to the personal computer monitor 9.

Next, the internal configuration of the memory write control unit 24 including its peripheral elements will be described with reference to FIG.

In this embodiment, as the video memory 26, for example, CXK1206 manufactured by Sony Corporation or MB81C1501 manufactured by Fujitsu Limited is used. The video memory 26 has a configuration of 960 rows (COLUMN) × 306 columns (ROW) × 4 bits, which are provided for R, G, and B, respectively. Access to the video memory 26 is performed in units of rows by blocks and columns by lines. In the video memory 26, DIN0 to DIN3 are data input terminals for inputting a digital RGB signal 25, ADD0 to ADD3 are address input terminals, CKW0 is a port 0 shift signal terminal, INC0 is a port 0 line increment terminal, and HCLR0 is a port 0 horizontal clear. The terminal VCLR0 is a port 0 vertical clear terminal, and WE (negative logic) is a port 0 write enable signal terminal.

R, G, and B of the digital RGB signal 25 are 4-bit signals.

In FIG. 3, reference numeral 221 denotes a horizontal write dot clock generation circuit that outputs a horizontal write dot clock signal HWDCK and a basic synchronization signal BSYNC, and 222 denotes a horizontal write start signal H.
A horizontal write start counter that outputs the WS and HCLR0 signals is shown, and 223 is a horizontal write number counter that outputs the horizontal write number signal HWT. Reference numeral 224 denotes a vertical write line clock generation circuit that outputs a vertical write line clock signal VWLCK, 225 denotes a vertical write start counter that outputs a vertical write start signal VWS, and 226 denotes the number of vertical write operations. 5 shows a vertical write counter for outputting a signal VWT. Further, reference numeral 227 denotes a vertical write offset counter for outputting a vertical write offset signal VWOFT for designating a vertical write reference position of the video memory 26, and reference numeral 228 denotes a video signal of the second field from a video signal of the first field. A vertical offset circuit for outputting a vertical write field clock signal VWFCK synchronized with the switching timing to the vertical write line clock signal VWFCK, and 229 generates a vertical write two line clock signal VWTCK having a frequency twice as high as the vertical write line clock signal VWLCK. The line addition circuit 229 is shown. The OR circuit 230 outputs one of the vertical write two-line clock signal VWTCK, the vertical write offset signal VWOFT, and the vertical write field clock signal VWFCK to the port 0.
The AND circuit 231 outputs the horizontal write dot clock signal HWDCK,
The logical AND of the horizontal write start signal HWS, the inverted output of the horizontal write count signal HWT, the vertical write start signal VWS and the inverted output of the vertical write count signal VWT is created, and the write enable signal WENBL is output. Yes, NOR circuit 232 has vertical sync signal VSTV, HCLR
It performs an OR-NOT logical operation of the signal, the output signal of the OR circuit 230, and the write enable signal WENBL output by the AND circuit 231 and outputs the port write enable signal WE.

The horizontal synchronizing signal HSTV extracted by the video signal decoder 21 is supplied to a dot clock generation circuit 221 and a horizontal writing start counter 22.
2, horizontal write counter 223 and vertical write start counter
Given to 225. Similarly, the vertical synchronizing signal VSTV extracted by the video signal decoder 21 is supplied to the vertical writing line clock generation circuit 224, the vertical writing start counter 225, the vertical writing number counter 226, the vertical writing offset counter 227, and the video memory 26. The port vertical clear terminal VCLR and the NOR circuit 232 are provided. Similarly, the odd / even discrimination signal EOS extracted by the video signal decoder 21 is supplied to the vertical offset circuit 228.

The ADC 22 converts the analog RGB signal LSTV into a digital signal using the horizontal write dot clock signal HWDCK provided as the clock signal CKAD as a sampling timing, and outputs the digitally converted RGB signal LSTV25 to the video memory 26. The dot clock generation circuit 221 is a horizontal synchronization signal HSTV.
(Ie, the horizontal synchronization signal HSTV period 63.5 μs)
, A horizontal write dot clock signal HWDCK having a period of 1 / N (N is a positive integer) is generated. The horizontal write dot clock signal HWDCK is supplied to the ADC 22 as a clock signal CKAD, and is also sent to the horizontal write start counter 222, horizontal write number counter 223, and AND circuit 231. Video memory 2
In step 6, address preset is performed in appropriate block units. Here, if the block unit of the address preset of the video memory 26 is 60 dots and one effective horizontal scanning period of the NTSC composite signal is 50 (μs), the horizontal writing generated by the horizontal writing dot clock generation circuit 221 is performed. The frequency of the dot clock signal HWDCK is 60 (dot) / 50 · 10 ⁻⁶ (S) = 1.2 (MHz).
Therefore, the horizontal write dot clock signal HWDCK quantizes the analog RGB signal in one effective horizontal scanning period into 60 × 3 dots. Actually, video memory 26 is 960
Since the data of one effective horizontal scanning period is stored by dots (16 blocks), digital R,
Up to 16 blocks can be used with 60 dots as one block for each of the G and B signals. In this case, it is effective with a horizontal writing dot clock HWDCK of 1.2 (MHz) x 16 (block) = 19.2 (MHz) Digital RGB signals during the horizontal scanning period can be written in block units.

As described above, the dot clock generation circuit 221 uses the address preset block unit (60 dots) of the video memory 26.
And outputs a horizontal write dot clock signal HWDCK having a frequency based on the value of the number of blocks to be used (1 to 16). The value of the number of blocks to be used is set by an instruction from the personal computer 2.

The dot clock generation circuit 221 is a port shift signal terminal CKW0 of the video memory 26 (a signal for incrementing the horizontal write address of the video memory 26 in dot units).
Generates a basic synchronization signal BSYNC to be used as a clock signal.

The basic synchronization signal BSYNC generated by the horizontal write dot clock generation circuit 221 is used as a signal for basically synchronizing each control circuit as a horizontal write start counter 222, a horizontal write number counter 223, and a vertical write line. The clock generation circuit 224, the vertical writing start counter 225, the vertical writing circuit counter 226, the vertical offset counter 227, and the video memory 26 are provided.

The horizontal write start counter 222 is reset by the horizontal synchronizing signal HSTV, counts the number of clocks of the horizontal write dot clock signal HWDCK, and outputs the analog RGB signal from the _first S clock during the effective horizontal scan period of the NTSC composite signal. A horizontal write start signal HWS for permitting writing to the video memory 26 is transmitted. At the same time, the horizontal write start counter 222 outputs the port horizontal clear signal HCLR0 to the video memory 26 by one.
Transmit only the clock.

The horizontal writing counter 223 is reset by the horizontal synchronization signal HSTV, and when the horizontal writing start signal HWS is given,
The clock count of the horizontal write dot clock signal HWDCK is started, and the effective horizontal scanning period of the NTSC composite video signal 5 is started.
E Digital RGB luminance signal video memory 2 only during _one clock
A horizontal write count signal HWT that permits writing to 6 is transmitted. Therefore, by controlling the effective horizontal scanning period, the horizontal writing number counter 223 can select to what extent the image is valid in the horizontal direction.

The vertical write line clock generation circuit 224 synchronizes with the vertical synchronizing signal VSTV and outputs the frequency N of the vertical synchronizing signal VSTV.
A vertical writing line clock signal VWLCK having a double frequency is generated and sent to the line addition circuit 229. Line addition circuit 2
At 29, a vertical write two-line clock signal VWTCK having a frequency twice the frequency of the vertical write line clock signal VWLCK is generated and sent to the vertical write number counter 226 and the OR circuit 230. Note that the value of N times is set by a command from the personal computer 2. The value of N is determined based on an aspect ratio suitable for the dot clock generation circuit 221.

Vertical write start counter 225 is reset by the vertical synchronizing signal VSTV, horizontal counts the clock number of the synchronization signals HSTV, from the S ₂ clock cycle during the vertical effective scanning period of the video signal VSTV, analog RGB signals from the effective horizontal scanning Is output to the AND circuit 231 and the vertical writing number counter 226 to permit the quantization of. Then, the vertical writing circuit counter 226 is reset by the vertical synchronization signal VSTV,
When the vertical write start signal VWS is supplied, the clock count of the vertical write two-line clock signal VWTCK starts, and N
The TSC composite in vertical effective scanning period of the video signal E only _two clock, and sends the vertical write count signal VWT which enables writing into the image memory 26 of the digital RGB luminance signals. Accordingly, the vertical effective scanning period is controlled by the vertical writing circuit counter 226, and it is determined to what extent the image is valid in the vertical direction.

The write reference position in the horizontal direction with respect to the display screen of the video memory 26, that is, the write position in the COLUMN direction is determined by the personal computer 2 by the address preset mode.
This is performed by designating the block as 60 × 3 bits of the quantized digital RGB signal as one block. The block designation at this time is performed in 16 steps by the address input signals ADD0 to ADD3. That is, the address input signals ADD0 to ADD3 are set by the personal computer 2. The vertical writing reference position for the display screen of the video memory 26 is set by the vertical writing offset counter 227. That is, the vertical write offset counter 227 is reset by the vertical synchronization signal VSTV, and outputs a vertical write offset signal VWOFT, that is, a line increment signal INC that offsets the vertical write position of the video memory 26 in synchronization with the basic synchronization signal BSYNC. S ₃ clock transmission, video memory 2
6 controls the vertical writing reference position.

Further, the odd / even discrimination signal EOS and the vertical write offset signal VWOFT extracted from the video signal decoder 21 are supplied to the vertical offset circuit 228. When the odd / even discrimination signal EOS indicates the state of the second field and the vertical write offset signal VWOFT has finished sending the line increment signal INC, the vertical write field clock signal VWFCK is The signal is supplied to the port 0 line increment signal terminal INC0 of the video memory 26 via the OR circuit 230.

That is, writing to the image memory 26 of the first field of the video signal, row every other line from the head position which is S ₃ line increment than the reset position by the vertical synchronizing signal VSTV by the vertical writing 2 line clock signal VWTCK However, the writing of the video signal of the second field to the video memory 26 is performed at the above-described head position.
After the vertical writing reference position is shifted, the writing is performed every other line from the position incremented by one line by the vertical writing field clock signal VWFCK. Therefore, the video signal of the second field is written between the lines where the video signal of the first field is written.

FIG. 6 is a conceptual diagram showing the situation in the video memory 26 of one plane in RGB. In the video memory 26, it can be seen that the first field 261 and the second field 262 are mutually written.

The above S ₁ value, the value of E _1, the value of S _2, the value of E _2, the value of S ₃ is set based on a command from the personal computer 2.

Next, the operation of the memory write control unit 24 and its peripheral circuits will be described with reference to the timing chart of FIG.

(1) First, when the vertical synchronizing signal VSTV becomes high level “H” (see FIG. 4A), the vertical write start counter 22
5. The vertical writing number counter 226 and the vertical writing offset counter 227 are reset, and the vertical writing start signal VWS and the vertical writing number signal VWT become low level "L" (FIGS. 4 (e) and (f)). )reference).

The signal of the odd / even discrimination signal EOS changes in synchronization with the vertical synchronizing signal VSTV, and keeps the low level “L” while the video of the first field is being written. The high level "H" is maintained while writing is being performed (see FIG. 4 (s)).

(2) The vertical write offset counter 227 outputs the basic synchronization signal B
Create a vertical write offset signal VWOFT from SYNC, and outputs a clock of the vertical write offset signal VWOFT only S ₃ clocks (see FIG. 4 (i)). This vertical write offset signal VWOFT is supplied to the video memory 26 via the OR circuit 230.
Given to port 0 line increment signal terminal INC0, video memory 26 will be the address in the vertical direction is incremented _three times S, to start the writing from the horizontal line of the video memory 26 throat is offset.

(3) On the other hand, the vertical write start counter 225 outputs the horizontal synchronization signal H
When STV number of clocks is S _2, and the vertical write start signal VWS to the high level "H", to allow a quantization of the vertical effective scanning period (see FIG. 4 (e)). With this, it is possible to control which horizontal line of the screen is valid according to the NTSC composite selection signal.

(4) When the horizontal synchronizing signal HSTV becomes high level “H” after the vertical write address of the video memory 26 is offset (see FIG. 4 (k)), the horizontal write start counter 222 and the horizontal write The number counter 223 is reset, and the horizontal write start signal HWS and the horizontal write number signal HWT are set to low level "L" (see FIGS. 4 (o) and (p)). Also,
The horizontal write dot clock generation circuit 221 outputs a horizontal write dot clock signal HWDCK (see FIG. 4 (n)).
ADC22 receiving this horizontal write dot clock signal HWDCK
Operates the horizontal write dot clock signal HWDCK as a sampling hold signal and a data latch signal, and samples analog RGB.

The horizontal write start counter 222 counts the clock number of the horizontal writing dot clock signal HWDCK, when its count value becomes S _1, and a horizontal write start signal HWS to the high level "H", the effective horizontal scanning Writing to the video memory 26 during the period is permitted (see FIG. 4 (o)). At the same time, the horizontal write start counter 222 outputs one clock of the port horizontal clear signal HCLR0 of the video memory 26 to prepare for writing.

At this time, the AND circuit 231 creates a logical product condition of the horizontal write start signal HWS of high level “H” and the vertical write count signal VWT of low level “L” which is inverted and input, and generates the horizontal write dot clock signal. HWDCK as write enable signal WENBL, NOR
It will be sent to the circuit 232. Further, the NOR circuit 232 outputs a high level "H" port 0 horizontal clear signal HCLR0, a high level "H" vertical synchronization signal VSTV, a high level "H" vertical write offset signal VWOFT or a vertical write line clock signal VWLCK, The logical operation of the NOT-OR condition of the write enable signal WENBL is performed, and the result is sent to the write enable signal terminal WE of the video memory 26 as the write enable signal WE.

The video memory 26 becomes writable in response to the write enable signal WE, and becomes a digital RGB signal output from the ADC 22.
25 is written. At the same time, the horizontal write counter 223
Is to count the number of clocks of the horizontal writing dot clock signal HWDCK, until the count value becomes E _1, to permit the writing of digital RGB luminance signal 25. When the count value becomes E _1, (see FIG. 4 (p)) horizontal write circuit counter 223 to the horizontal write count signal HWT the high level "H" to prohibit writing.

Thus, while the digital RGB luminance signal LSTV25 is being written, until the vertical write line clock generation circuit 224 outputs the vertical write line clock signal VWLCK,
Horizontal writing is performed on the same line address. Then, the vertical write line clock generation circuit 22
The vertical write line clock signal VWLCK generated in step 4 is converted by the line adder circuit 229 into a double frequency vertical write two line clock signal VWTCK, which is transmitted as a port line increment INC signal of the video memory 26. Then, the vertical write line address of the video memory 26 advances by "2". Therefore, writing in the vertical direction is performed every other line (see FIG. 4 (d)).

In this way, the writing in the vertical direction proceeds, and when the writing of the video of the first field is completed, the vertical synchronization signal VSTV
Is given to the port vertical clear terminal VCLR of the video memory 26, the writing position on the display screen of the video memory 26 is reset, and the odd / even discrimination signal EOS becomes high level “H”. Then, the vertical write offset counter 227 is incremented S ₃ lines. The signal of the end of the count of the vertical write offset counter 227 is given to the vertical offset circuit, and the odd / even discrimination signal EOS
Is at the high level “H”, the vertical write field clock signal VWFCK is applied to the port 0 line increment signal terminal INC0 of the video memory 26,
Is incremented by one line (see FIG. 4 (u)).

Further writing in the vertical direction proceeds, and the line addition circuit 22
When the clock number of the vertical write two-line clock signal VWTCK output from 9 becomes E ₂ , the vertical write number counter 226 sets the vertical write number signal VWT to a high level “H”, and The writing to the video memory 26 is stopped (see FIG. 4 (f)). This writing stop is performed by the next vertical synchronization signal.
It continues until VSTV becomes high level "H".

In the above operation, the high level “H” is set to the active logic, but the same applies when the low level “L” is set to the active logic.

As described above, by controlling the control signals output to the ADC 22 and the video memory 26, the digital RGB luminance signals of the first and second fields of the NTSC composite video signal are alternately displayed on the video memory 26 in line units. You can write on the screen.

The video signal input terminal is controlled by the memory read control unit 27.
By scanning on the screen of the video memory 26 in synchronization with the horizontal / vertical synchronization signal from 31, the RGB luminance signal can be read out without being aware of the first and second fields of the screen. The read digital RGB luminance signal 29 is converted into an analog RGB luminance signal by the DAC 28 as shown in FIG.
It is converted to 30 and given to a video output terminal 32. If the clock signal read from the video memory 26 by the memory read control unit 27 is read at, for example, twice the frequency of the horizontal synchronizing signal H, video data is read from the video memory in every other line in the vertical direction. As a result, a video signal thinned out one line at a time in the vertical direction is obtained.
A video screen signal reduced to 2 is obtained. Conversely, if the clock signal at the time of reading is 1/2 of the horizontal synchronizing signal H, the data of that line will be repeatedly read twice for each line in the vertical direction. The output is obtained. The analog RGB luminance signal 30 is output from the video output terminal 32 to the corresponding display device 9 together with the synchronization signal 36 from the video signal input terminal 31.

〔The invention's effect〕

As described above, according to the video processing device of the present invention,
All or part of the sub-picture based on the 2: 1 interlaced picture signal can be arbitrarily enlarged or reduced and displayed superimposed on the main picture. This sub-picture screen can be displayed as a still image in frame units. Therefore, an image of an arbitrary size corresponding to a high-definition image signal such as a next-generation high-definition image can be easily constructed on a personal computer. Also, video editing for business use can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing an application example of this embodiment, FIG. 3 is a block diagram showing a memory write control unit constituting the embodiment, FIG. FIG. 4 is a waveform diagram showing the operation of the memory write control unit constituting the embodiment, FIG. 5 is a conceptual diagram showing the relationship between a frame and a field, and FIG. It is the conceptual diagram shown. 1 ... video processing device, 2 ... personal computer,
3 PC video signal 5 NTSC composite video signal 9
…… PC monitor, 21 …… Video signal decoder, 22 ……
ADC, 24: Memory write control unit, 25: Digital RGB luminance signal, 26: Video memory, 27: Memory read control unit, 28
… DAC, 29… Digital RGB luminance signal, 30… Analog
RGB luminance signal, 31: Video signal input terminal, 32: Video signal output terminal, 33: Video switch, 34: Analog RG
B luminance signal, 35: RGB luminance signal, 36: Synchronous signal.

Claims (2)

(57) [Claims] 1. A / D conversion means for quantizing a luminance signal of a first video signal and converting the same into a digital luminance signal; video storage means for storing a digital luminance signal from the A / D conversion means; Mixing means for partially replacing a screen based on the luminance signal of the video signal with a screen based on the digital luminance signal from the video storage means; and how the screen based on the luminance signal from the video storage means is displayed during the screen based on the second video signal. And a control means for controlling each of the means based on a command indicating whether to insert the image by enlarging or reducing the image signal. A 2: 1 interlace signal that constitutes one complete screen (frame), wherein the control means includes:
The video storage means stores each line of the first field video signal by skipping every other line and stores each line of the second field video signal between the lines where the first field video signal is stored. A video processing device characterized by the above-mentioned. 2. The line adding circuit section, wherein the control means generates a pulse for advancing a write line on a storage area of the video storage means twice for each write processing of one line on the first video signal. And a second field write position setting circuit section which shifts a write start line on the storage area of the video storage means by one line only at the time of write processing of one of the first and second fields. The video processing device according to claim 1, wherein: