JPH0456891A - Image processor - Google Patents

Abstract

PURPOSE:To easily execute the optional expansion/contraction of a video signal at the time of reading out it by storing a 1st field video signal so that respective lines of the signal are jumped every other line and storing a 2nd field video signal so that respective lines of the signal are stored between respective stored lines of the 1st field video signal. CONSTITUTION:The writing of the 1st field video signal in an image memory 26 is executed by a vertical writing 2-line clock signal VWTCK every other line from a leading position increased by S3 lines from a position reset by a vertically synchronizing signal VSTV. The writing of the 2nd field video signal in the video memory 26 is executed by moving the vertical writing reference position of the memory 26 to the leading position and then writing respective lines every other line by a vertical writing field clock signal VWFCK from a position increased by one line. Consequently, all or a part of a subimage based upon a 2:1 interlacing video signal can be superposed to a main image.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video processing device that superimposes another video screen on a part of one video screen.

[Conventional technology]

In the field of so-called personal computers (PCs), image processing called picture-in-picture, which displays television images overlaid on computer images, has begun to be used. That is, a video processing device is being developed that is interposed between a personal computer and a personal computer monitor and displays part or all of an external video signal superimposed on the personal computer video screen.

The external video signal is generally a 2:1 interlaced video signal, which scans every other scanning line from the top to the bottom of the screen, returns to the top, and is then skipped first. This is a signal based on a method of scanning scan lines. In this case, a screen consisting of every other scanning line is called a field, and a completely scanned screen consisting of two consecutive fields (first field, second field) is called a frame.

FIG. 5 is a conceptual diagram showing the relationship between frames and fields, with FIGS. 5(a) and 5(b) showing the first field and the second field, respectively, and FIG. 5(C) showing the first field. This shows a frame consisting of a second field and a second field.

[Invention or problem to be solved]

By the way, when performing picture-in-picture video processing, in order to obtain a high-quality video, it is sufficient to superimpose the video on a frame-by-frame basis.

However, in order to extract a frame-by-frame video signal from a 2:1 increment signal, this signal is stored in separate storage devices for each field, and then the field signals are extracted from each storage device and mixed as frames. Must.

Image processing to arbitrarily enlarge or reduce the video signal in the vertical direction is performed on the video signal for each field stored in the storage device before mixing, but managing the video signal during this processing is complicated and difficult. Ta.

In addition, the video signal input to the storage device can be transferred to an external CPU.
etc., it was difficult to read out the video signals of the first field and the second field alternately line by line.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the video processing device of the present invention includes:
RGB of the first video signal which is a 2:1 interlaced signal
An A/D conversion means for quantizing a luminance signal and converting it into a digital RGB luminance signal, a video storage means for storing the digital RGB luminance signal, and an analog version of the digital RGB luminance signal read from the video storage means. D/A converting means; mixing means for partially replacing the RGB luminance signal of the second video signal with the RGB luminance signal from the D/A converting means; control means for controlling each of the means based on a command indicating how to insert a screen based on an RGB luminance signal from the means; This is a 2:1 interlaced signal that constitutes one complete screen (frame), and this control means causes the storage means to store each line of the first field video signal by skipping every other line, and also stores the second field video signal by skipping every other line. Each line of the signal is stored between the lines where the first field video signal is stored.

[Effect]

If the signal is written in the video memory in this manner, it can be read out frame by frame without being aware of whether it is a first field video signal or a second field video signal. Therefore, arbitrary enlargement/reduction of the video signal can be easily performed at the time of reading.

[Embodiment] FIG. 1 is a block diagram of a video processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the connection relationship between the video processing device, a personal computer, and a personal computer monitor.

The video processing device 1 receives a personal computer video signal 3 (RGB luminance signal and vertical/horizontal synchronization signal) coming from a personal computer 2 and an NT video signal coming from a video input terminal 4.
The SC composite video signal 5 is input. Then, the video processing device 1 synthesizes these two video signals and outputs a video signal 8, in which the screen 7 of the NTSC composite video signal 5 is inserted into the screen 6 of the PC video signal 3, to the computer monitor 9. How to insert the screen 7 into the screen 6 is based on a command 10 from the personal computer 2, and processes such as extracting a desired portion from the screen of the video signal and enlarging the extracted screen are performed. .

The NTSC composite video signal 5 is applied to the video input terminal 4 from a TV tuner, video deck, etc. (not shown).

Next, the internal configuration of the video processing device 1 will be explained.

The video signal decoder 21 receives the NTS from the video input terminal 4.
A C composite video signal 5 is input, and an RGB luminance signal 23, a horizontal synchronization signal, a vertical synchronization signal, and an odd/even discrimination signal are extracted from this NTSC composite video signal 5. The odd/even discrimination signal is a signal synchronized with the first field signal and the second field signal. For example, if the odd/even discrimination signal is high level rHJ when the first field signal is applied to the NTSC composite video signal 5, the timing at which the NTSC composite video signal 5 changes from the first field signal to the second field signal , the odd/even discrimination signal is inverted from high level rHJ to low level rLJ.

The A/D converter (ADC) 22 is a video signal decoder 21
The RGB luminance signal 23 arriving from the memory write controller 24 is quantized at the timing of the clock signal CKAD from the memory write control section 24 and converted into a digital RGB luminance signal 25. The video memory 26 has a configuration of 960 rows x 306 columns x 4 bits, and this is provided for each color of R1G%B.

The memory write control unit 24 sends a clock signal C to the ADC 22.
In addition to outputting KAD, a write control signal WETV is output to the video memory 26. The clock signal CKAD is a signal synchronized with the horizontal synchronization signal from the video signal decoder 21, and has a period of 1/1 of the period of the horizontal synchronization signal (for example, 63.5 μs).
It has a period of N (N is a positive integer). Write control signal WE
TV is a signal that permits writing of the digital RGB luminance signal 25 coming from the ADC 22, and is a set of a plurality of control signals. The internal configuration of the memory write control section and a specific example of the write control signal WETV will be described later using FIG.

The memory read control unit 27 performs read control of the video stored in the video memory 26. This memory read control section 27 is
Based on the conditions instructed by the personal computer 2, a read control signal is sent to the video memory 26, and a clock signal CKDA is sent to the D/A converter (DAC) 28. The read control signal is a digital RG from the video memory 26.
This is a signal that controls reading of the B luminance signal. Although the specific form of the read control signal is omitted here, it is usually a set of a plurality of control signals. For example, the video memory 26
A signal that specifies or advances a pixel address for readout on the memory screen, a control signal that permits readout in pixel units, a control signal that permits readout of only a desired area in the horizontal direction (line) of the memory screen, Similarly, it is composed of control signals that permit reading of only a desired area in the vertical direction. These control signals are
All the readout basic synchronization signals generated within the memory readout control section 27 are counted and are generated based on whether or not the counted value reaches a set value set for each control signal. These set values can be adjusted based on commands from <-sonal computer 2.

The DAC 28 samples the digital RGB luminance signal 29 read from the video memory 26 at the timing of the clock signal CADA and converts it into an analog RGB luminance signal 30. A personal computer video signal 3 coming from the personal computer 2 is given to the video signal input terminal 31, and is input as an RGB luminance signal 35, a horizontal synchronization signal and a vertical synchronization signal for the processed video signal. This horizontal synchronization signal and vertical synchronization signal are NTSC composite video signal 5
It is independent from the horizontal and vertical synchronization signals.

The video signal output terminal 32 is connected to the R from the video switch 33.
This terminal outputs the GB luminance signal 34 and the horizontal synchronization signal and vertical synchronization signal from the video signal input terminal 31, and the video signal 8 (RGB luminance signal and synchronization signal) from the video signal output terminal 32 is output to the computer monitor given to 9.

Next, the internal configuration of the memory write control unit 24 including its peripheral elements will be explained using FIG.

In this embodiment, as the video memory 26, for example, CXK1206 manufactured by Sony Corporation or M881C1501 manufactured by Fujitsu Corporation is used. The video memory 26 has 960 lines (COLUMN
) x 306 columns (ROW) x 4 bits, and this is provided for R, G, and B, respectively. Access to the video memory 26 is performed using rows as blocks and columns as lines. In the video memory 26, DINO
~DIN3 is a data input terminal for inputting the digital RGB signal 25, ADDO~ADD3 is an address input terminal,
CKWO is port O soft signal terminal, lNC0 is port 0 line increment terminal, HCLRO is port 0 horizontal clear terminal, VCLRO is port O vertical clear terminal,
WE (negative logic) is a signal terminal for port 0 write enable.

R, G, and B of the digital RGB signal 25 are each 4-bit signals.

In FIG. 3, reference numeral 221 indicates a horizontal write dot clock generation circuit that outputs the horizontal write dot clock signal HWDCK and basic synchronization signal BSYNC, and 222 indicates a horizontal write dot clock generation circuit that outputs the horizontal write start signal HWS and HCLR signal. Indicates a start counter, 223 is a horizontal writing number signal HW
A horizontal write count counter that outputs T is shown. Further, reference numeral 224 indicates a vertical write line clock generation circuit that outputs the vertical write line clock signal VWLCK, 225 indicates a vertical write start counter that outputs the vertical write start signal vWS, and 226 indicates the number of vertical writes. A vertical write counter that outputs a signal VWT is shown. Furthermore, 227 indicates a vertical write offset counter that outputs a vertical write offset signal VWOFT that specifies the vertical write reference position of the video memory 26, and 228 indicates a signal from the first field video signal to the second field video signal. Vertical write field clock signal VWFC synchronized with switching timing to
The vertical offset circuit 229 outputs the vertical write line clock signal VWLCK, and the line adder circuit 229 generates the vertical write 2-line clock signal VWTCK having twice the frequency of the vertical write line clock signal VWLCK. Also, OR circuit 2
30 outputs one of the vertical write 2-line clock signal VWTCK, the vertical write offset signal VWOFT, and the vertical write field clock signal VWFCK as a port 0 line increment signal INC;
The D circuit 231 receives the horizontal write dot clock signal HWDCK.
, creates an AND of the horizontal write start signal HWS, the inverted output of the horizontal write count signal HWT, the inverted output of the vertical write start signal vWS, and the inverted output of the vertical write count signal VWT, and outputs the write enable signal WENBL. The NOR circuit 232 receives the vertical synchronization signal VSTV, the HCLR signal, and the OR circuit 230
It performs a 0R-NOT logical operation on the output signal of and the write enable signal WENBL output from the AND circuit 231, and outputs the port write enable signal WE.

Horizontal synchronization signal H3T extracted by video signal decoder 21
V is applied to a dot clock generation circuit 221, a horizontal write start counter 222, a horizontal write number counter 223, and a vertical write start counter 225. Further, the vertical synchronization signal VSTV similarly extracted by the video signal decoder 21 is sent to the vertical write line clock generation circuit 224, the vertical write start counter 225, the vertical write number counter 226, the vertical write offset counter 227, and the video memory 26. is applied to the port vertical clear terminal VCLR and NOR circuit 232. Similarly, the odd/even discrimination signal EO5 extracted by the video signal decoder 21 is given to the vertical offset circuit 228.

The ADC 22 digitally converts the analog RGB signal LSTV using the hand write dot clock signal HWDCK given as the clock signal CKAD as the sampling timing, and generates the digitally converted RGB signal LSTV.
25 is output to the video memory 26. The dot clock generation circuit 221 is synchronized with the horizontal synchronization signal HSTV (that is, the horizontal synchronization signal)! A horizontal write dot clock signal HWDCK with a period of 1/N (N is a positive integer) is generated for the STV period of 63.5 μs. This horizontal write dot clock signal HWDCK is sent to the ADC 22 as a clock signal C.
In addition to being given as KAD, the horizontal write start counter 22
2. Horizontal writing number counter 223 and AND circuit 231
sent to. The video memory 26 is divided into appropriate block units and addresses are preset. Here, the address preset block unit of the video memory 26 is 6.
When one effective horizontal scanning period of the NTSC composite signal is 50 (μs), the frequency of the horizontal write dot clock signal HWDCK generated by the horizontal write dot clock generation circuit 221 is 60 (dots) 150・1O-6(S)-1,2(M
Hz). Therefore, the horizontal write dot clock signal HWDCK allows analog RGB data to be read during one effective horizontal scanning period.
The signal will be quantized with 60x3 dots. In reality, the video memory 26 is configured to store data for one effective horizontal scanning period using 960 dots (16 blocks), so one block is 60 dots for each of the digital R, G, and B signals. Up to 16 blocks can be used, in this case 1.2 (MHz) x 16 (blocks) - 19,2 (
Digital RGB signals for one effective horizontal scanning period can be written block by block using the horizontal write dot clock HWDCK (MHz).

In this way, the dot clock generation circuit 221 outputs the horizontal write dot clock signal HWDCK with a frequency based on the address preset block unit (60 dots) of the video memory 26 and the number of blocks to be used (1 to 16). . Note that the value of the number of blocks to be used is set by an instruction from the personal computer 2.

Further, the dot clock generation circuit 221 is connected to the video memory 26.
Basic synchronization signal BSY used as a clock for the port shift signal terminal CKW (a signal that increments the horizontal write address of the video memory 26 in units of dots).
Generates NC.

The basic synchronization signal BSYNC generated by the horizontal write dot clock generation circuit 221 is used as a signal for basic synchronization of each control circuit and is used by the horizontal write start counter 222.
, horizontal write number counter 223, vertical write line clock generation circuit 224, vertical write start counter 225, vertical write number counter 226, vertical offset counter 22
7 and the video memory 26.

The horizontal write start counter 222 is reset by the horizontal synchronization signal H3TV, and is reset by the horizontal write dot clock signal HWD.
The number of clocks of CK is counted, and from the 81st clock during the valid horizontal scanning period of the NTSC composite signal, a horizontal write start signal HWS that permits writing of the analog RGB signal into the video memory 26 is sent out. At the same time, the horizontal write start counter 222 sends a boat horizontal clear signal HCLR to the video memory 26 by one clock.

The horizontal write count counter 223 is reset by the horizontal synchronization signal HSTV, and when the horizontal write start signal HWS is applied, it starts counting the clock of the horizontal write dot clock signal HWDCK, and the effective horizontal scanning of the NTSC composite video signal 5 is started. A horizontal write count signal HWT that permits writing of digital RGB luminance signals to the video memory 26 is sent only during the E1 clock period. Therefore, the horizontal writing number counter 223 controls the effective horizontal scanning period, and it is possible to select which part of the image is valid in the horizontal direction.

The vertical write line clock generation circuit 224 generates a vertical write ink clock signal VW that is synchronized with the vertical synchronization signal VSTV and has a frequency N times the frequency of the vertical synchronization signal VSTV.
Generates LCK and sends it to line adder circuit 229.

Line adder circuit 229 generates vertical write 2-line clock signal VWTCK having a frequency twice that of vertical write line clock signal VWLCK, and sends it to vertical write number counter 226 and OR circuit 230 .

Note that the above-mentioned value multiplied by N is set by a command from the personal computer 2. The value of N is determined based on the aspect ratio suitable for the dot clock generation circuit 221.

The vertical write start counter 225 is set by the vertical synchronization signal VSTV, counts the number of clocks of the horizontal synchronization signal HSTV, and starts from the 82nd clock during the vertical effective scanning period of the video signal VSTV by analog RGB of the effective horizontal scanning.
AN vertical write start signal vWS that allows signal quantization
It is output to the D circuit 231 and the vertical write number counter 226. Therefore, the vertical write number counter 226 is reset by the vertical synchronization signal VSTV, and the vertical write start signal VW
When S is given, the vertical write 2-line clock signal VW
It starts counting the TCK clock and sends out a vertical write count signal VWT that permits writing of the digital RGB luminance signal into the video memory 26 for only E2 clocks within the vertical effective scanning period of the NTSC composite video signal. Therefore,
The vertical write count counter 226 controls the vertical effective scanning period, and determines which part of the image is valid in the vertical direction.

The writing reference position in the horizontal direction with respect to the display screen of the video memory 26, that is, the writing position in the COL UMN direction, is set so that the personal computer 2 writes one block of 60 x 3 bits of the quantized digital RGB signal according to the address preset mode. This is done by specifying a block. Block designation at this time is address input signal ADDO~A
This is done in 16 steps using DD3. That is, address input signals ADDO to ADD3 are set by the personal computer 2. Further, a writing reference position in the vertical direction with respect to the display screen of the video memory 26 is set by a vertical writing offset counter 227. That is, the vertical write offset counter 227 is reset by the vertical synchronization signal VSTV, and generates the vertical write offset signal VWOFT, that is, the line increment signal INC, which offsets the vertical writing position of the video memory 26 in synchronization with the basic synchronization signal BSYNC. The S3 clock is sent out to control the vertical writing reference position of the video memory 26.

Further, an odd/even discrimination signal EO5 and a vertical write offset signal VWOFT extracted from the video signal decoder 21
is applied to vertical offset circuit 228. Then, at the timing when this odd/even discrimination signal EO8 indicates the state of the second field and the vertical write offset signal VWOFT has finished sending out the above-mentioned line increment signal INC, the vertical write field clock signal VWF
CK is applied to the port 0 line increment signal terminal lNC0 of the video memory 26 via the OR circuit 230.

In other words, writing of the first field video signal to the video memory 26 is performed every other line by the vertical write 2-line clock signal VWTCK from the start position which is incremented by 83 lines from the position reset by the vertical synchronization signal VSTV. Alternatively, the writing of the second field video signal into the video memory 26 is performed in one line by the vertical write field clock signal VWFCK after the vertical write reference position of the video memory 26 has been moved to the above-mentioned top position. This is performed every other line from the incremented position. Therefore, the video signal of the second field is written between the lines where the video signal of the first field is written.

FIG. 6 is a conceptual diagram showing the situation in the video memory 26 of one frame in RGB. It can be seen that within the video memory 26, a first field 261 and a second field 262 are written to each other.

Note that the value of 81, the value of El, the value of s2, the value of E2, and the value of S3 are set based on instructions from the personal computer 2.

Next, the operation of the memory write control section 24 and its peripheral circuits will be explained with reference to the timing chart of FIG. 4.

(1) First, whether the vertical synchronization signal VSTV/＼level rH
J (see FIG. 4(a)), the vertical write start counter 225, the vertical write count counter 226, and the vertical write offset counter 227 are reset, and the vertical write start signal VWS and the vertical write count signal VWT are reset. or low level r
becomes LJ (see Figures 4(d) and (e)).

Moreover, the odd/even discrimination signal EO5 is the vertical synchronization signal VST.
The signal changes in synchronization with V, holds low level rLJ while the first field video is being written, and holds /\\low level rHJ while the second field video is being written. (See Figure 4(s)).

(2) The vertical write offset counter 227 creates a vertical write offset signal VWOFT from the basic synchronization signal BSYNC, and outputs the clock of this vertical write offset signal VWOFT for S3 clocks (see FIG. 4(i)). ). When this vertical write is turned off, the cut signal VWOFT is applied to the port O line increment signal terminal lNC0 of the video memory 26 via the OR circuit 230.
6 is a vertical address that is incremented 83 times, and the horizontal line in the video memory 26 from which writing starts is offset.

(3) On the other hand, when the number of clocks of the horizontal synchronization signal H3TV reaches 82, the vertical write start counter 225 sets the vertical write start signal WS to high level rHJ to permit quantization of the vertical effective scanning period (the (See Figure 4(e)). Thereby, it is possible to control which horizontal line on the screen is made valid based on the NTSC composite selection signal.

(4) After the vertical write address of the video memory 26 is offset, when the horizontal synchronizing signal HSTV becomes high level "Hj" (see FIG. 4(k)), the horizontal write start counter 2
22 and the horizontal writing number counter 223 are reset,
The horizontal write start signal HWS and horizontal write count signal HWT are set to low level rLJ (see FIG. 4 (0) and (p)). Further, the horizontal write dot clock generation circuit 221 outputs the horizontal write dot clock signal HWDCK (the fourth
(See figure (n)). This horizontal write dot clock signal HW
The ADC 22 receiving DCK operates using the horizontal write dot clock signal HWDCK as a sampling hold signal and a data latch signal, and samples analog RGB.

Further, the horizontal write start counter 222 counts the number of clocks of the horizontal write dot clock signal HWDCK, and when the count value reaches 81, the horizontal write start signal HWS is set to a high level rHJ, and the image of the effective horizontal scanning period is Writing to the memory 26 is permitted (see FIG. 4(o)).

At the same time, the horizontal write start counter 222 outputs the port horizontal clear signal HCLR of the video memory 26 for one clock to prepare for writing.

At this time, the AND circuit 231 receives the horizontal write start signal HWS at high level rHJ, and the low level rLJ which is inverted and input.
Create an AND condition for the vertical write count signal VWT and convert the horizontal write dot clock signal HWDCK to the write enable signal WE.
It will be sent to the NOR circuit 232 as NBL. Furthermore, the NOR circuit 232 outputs a port horizontal clear signal HCLR of high level rHJ, a vertical synchronization signal VSTV of high level rHJ, and a vertical write offset signal VWOFT or vertical write line clock signal VWL of high level rHJ.
A logical operation is performed on the N0T-OR condition of CK and the write enable signal WENBL, and the result is sent to the write enable signal terminal WE of the video memory 26 as a write enable signal WE.

The video memory 26 becomes writable upon receiving the write enable signal WE, and the data latch signal 25 output from the ADC 22 is written therein.

At the same time, the horizontal write count counter 223 is counting the number of clocks of the horizontal write dot clock signal HWDCK, and until the count value reaches El, the digital RGB
Writing of the luminance signal 25 is permitted. Then, when the count value reaches El, the horizontal write number counter 223 sets the horizontal write number signal HWT to a high level rHJ to prohibit writing (see FIG. 4(p)).

Thus, while the digital RGB luminance signal LSTV25 is being written, the vertical write line clock generation circuit 22
4 outputs the vertical write line clock signal VWLCK, horizontal writing is performed to the same line address. Then, the vertical write line clock signal VWLCK generated by the vertical write line clock generation circuit 224 is converted into the vertical write 2 line clock signal VWTCK with twice the frequency by the line adder circuit 229,
This clock signal is sent as a boat line increment INC signal to the video memory 26.
The vertical write line address advances by "2". Therefore, writing in the vertical direction is done every other line (Fig. 4(d)
)reference).

Writing progresses in the vertical direction in this way, and when the writing of the first field video is completed, the vertical synchronizing signal VST
V is applied to the port vertical clear terminal VCLR of the video memory 26, the write position for the display screen of the video memory 26 is set, and the odd/even discrimination signal EO8 becomes high level rHJ. Then, the vertical write offset counter 227 increments by S3 lines.

The count end signal of this vertical write offset counter 227 is given to the vertical offset circuit, and
When the even number discrimination signal EO3 is in the state of high level rHJ, the vertical write field clock signal VWF is applied to the port 0 line increment signal terminal lNC0 of the video memory 26.
CK is given, and the vertical writing position of the video memory 26 is incremented by one line (see FIG. 4(U)).
.

Writing further progresses in the vertical direction, and the line addition circuit 22
Vertical write 2-line clock signal VWT output from 9
When the clock number of CK reaches E2, the vertical write number counter 226 sets the vertical write number signal VWT to high level rHJ, and stops writing to the video memory 26 for the vertical effective scanning period (FIG. 4(f) )reference). This write stop continues until the next vertical synchronization signal VSTV becomes high level rHJ.

Note that although the above operation uses high level rHJ as active logic, it is the same even if low level rLJ is used as active logic.

As described above, by controlling the control signals output to the ADC 22 and the video memory 26, the digital RG of the first and second fields of the NTSC composite video signal is
The B luminance signal can be written to the display screen of the video memory 26 alternately line by line.

The memory read control unit 27 then reads the video memory 2 in synchronization with the horizontal and vertical synchronizing signals from the video signal input terminal 31.
By scanning the screen of No. 6, the RGB luminance signals can be read out without being aware of the first and second fields of the screen. Read digital RG
The B luminance signal 29 is converted into an analog RGB luminance signal 30 by the DAC 28 as shown in FIG.
given to. This analog RGB luminance signal 30 is outputted from the video output terminal 32 to the corresponding display device 9 along with the synchronization signal 35 from the video signal input terminal 31.

〔Effect of the invention〕

As explained above, according to the video processing device of the present invention, two
- All or part of the sub-video based on one interlaced video signal can be displayed superimposed on the main video.

This sub-video screen can be displayed as a still image in frame units, and can also be enlarged or reduced as desired. Therefore, images of any size that are compatible with highly detailed video signals such as next-generation high-definition can be easily constructed using a personal computer. You can also easily edit videos for professional use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an application example of this embodiment, FIG. 3 is a block diagram showing a memory write control section constituting the embodiment, and FIG. Fig. 4 is a waveform diagram showing the operation of the memory write control section constituting the embodiment, Fig. 5 is a conceptual diagram showing the relationship between frames and fields, and Fig. 6 shows the situation in the video memory of one frame in RGB. FIG. DESCRIPTION OF SYMBOLS 1... Video processing device, 2... Personal computer, 3... Personal computer video signal, 5... NTSC composite video signal, 9... Personal computer monitor, 21... Video signal decoder, 22... ADC124 ...Memory write control unit, 25...Digital RGB luminance signal, 26...Video memory, 27...Memory read control unit, 28...DA
C. 29... Digital RGB luminance signal, 30... Analog RGB luminance signal, 31... Video signal input terminal, 32
...Video signal output terminal, 33...Video switch,
34... Analog RGB luminance signal, 35... Synchronization signal. (g) vs”rv (i) VWOFT Representative Patent Attorney Yoshiki Hase
Salt 1) Tatsuya (j) WE Waveform diagram (first half) showing the operation of the memory write control section Figure 4 (
1/2) (klH5TV Figure 4 (2/2) Figure 5 is a conceptual diagram showing the relationship with the frame t-field.

Claims (1)

[Claims] 1. A/D conversion means for quantizing the RGB luminance signal of the first video signal and converting it into a digital RGB luminance signal; and an image storing the digital RGB luminance signal from the A/D conversion means. storage means; D/A conversion means for converting the digital RGB luminance signal read from the video storage means into analog; mixing means to replace the signal; and control means for controlling each of the means based on a command indicating how to insert a screen based on the RGB luminance signal from the D/A conversion means into a screen based on the second video signal. In the video processing device, the first video signal is a 2:1 interlaced signal in which one complete screen (frame) is made up of two screens (fields) consisting of interlaced scanning lines, and the control means includes: The storage means stores each line of the first field video signal skipping every other line, and stores each line of the second field video signal between the lines where the first field video signal is stored. Featured video processing device. 2. The control means includes a line addition circuit section that generates a pulse that advances the write line on the storage area of the video storage means twice for each writing process for one line on the video signal; 2. The video processing apparatus according to claim 1, further comprising a second field write position setting circuit section which shifts the write start line on the storage area of the storage means by one line only when writing processing is performed on either one of the fields. Device.