JP2568932B2 - Video processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing apparatus that superimposes another video screen on a part of one video screen, and more particularly, to video data stored in a video memory. The present invention relates to an image processing apparatus capable of obtaining an image without shaking when the image is enlarged / reduced in the horizontal direction.

[Conventional technology]

In the field of so-called personal computers (personal computers), image processing called picture-in-picture in which television images and the like are superimposed and displayed on personal computer images has come to be performed. In other words, it intervenes between the personal computer and the personal computer monitor, takes in the external video signal in addition to the personal computer video signal, especially the general 2: 1 interlaced video signal into the video memory, and creates a part of the personal computer video screen. A video processing device for synthesizing and displaying video signals read from the video memory is being developed.

[Problems to be solved by the invention]

By the way, the increment of the pixel address up to the read start position on the video memory is the first position for determining the display position.
A clock signal is applied. For reading out the pixel address step by step from the top position of the video memory, a second clock signal for horizontal enlargement / reduction display is applied.

Conventionally, when switching from the first clock signal to the second clock signal, that is, when the horizontal synchronizing signal of each field is sufficient, the pixel address is advanced from the head of the video memory to the read start position, and the video signal is read from the read start position. When reading, the video screen sometimes fluctuates in the horizontal direction. This is because the PLL section of the clock generator has a lock unstable area called jitter due to the first clock signal and the second clock signal having different phases, and this jitter causes an extra pulse to be generated. Was. This wobble of the video screen is not so bothersome if the video moves relatively fast and the human eyes are distracted by the motion, but if the screen motion is stationary or slowly changes I feel annoying.

An object of the present invention is to solve such a problem.

[Means for solving the problem]

In order to solve the above problem, a video processing device according to the present invention includes an A / D conversion unit that converts a luminance signal of a first video signal into a digital luminance signal, and stores a digital luminance signal from the A / D conversion unit. Video storage means for reading, a reading means for reading a digital luminance signal from the video storage means, a mixing means for partially replacing the luminance signal of the second video signal with the luminance signal read from the reading means, and a second video signal Control means for controlling each means based on a command indicating how to insert the screen by the luminance signal read from the reading means in the screen by the video processing device,
The control means can arbitrarily set the horizontal read start reference position based on the timing control of the read start signal. When the horizontal line dots are read from the video storage means, the dot clock supplied to the video storage means is controlled. The signal is switched from the first clock signal to the second clock signal at a read start reference position or a position obtained by a predetermined dot coefficient from the read start reference position.

[Action]

In the video processing apparatus according to the present invention, since the first clock signal and the second clock signal, which are the clock signals optimal for stepping and reading in the video memory, are respectively supplied to the video memory, any video data set arbitrarily can be set. The second clock signal applied to the video memory at the start of the memory reading can be generated at a timing not affected by the jitter.

〔Example〕

FIG. 1 is a block diagram of a video processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a connection relationship between the video processing device and a personal computer and a personal computer monitor.

The video processing device 1 is a personal computer 2 that receives a personal computer video signal 3 (RGB luminance signal and vertical
(Horizontal synchronization signal) and an NTSC composite video signal 5 coming from a video input terminal 4. Then, the video processing device 1 combines these two video signals, and outputs a video signal 8 in which the screen 7 of the NTSC composite video signal 5 is inserted into the screen 6 of the personal computer video signal 3 to the personal computer monitor 9. How to insert the screen 7 into the screen 6 is performed based on a command 10 from the personal computer 2. The NTSC composite video signal 5 is supplied to a video input terminal 4 from a TV tuner, a VCR, or the like (not shown).

Next, the internal configuration of the video processing device 1 will be described. The video signal decoder 21 receives the NTSC composite video signal from the video input terminal 4 and extracts an RGB luminance signal and horizontal / vertical synchronization signals from the video signal. The A / D converter (ADC) 22
The RGB luminance signal 23 coming from the video signal decoder 21 is converted into a digital RGB luminance signal 25 at the timing of the clock signal CKAD from the digitizing control unit 24. Image memory 26 is 9
It has a configuration of 60 rows x 306 columns x 4 bits.
It is provided for each of G and B colors.

The digitizing control unit 24 outputs a clock signal CKAD to the ADC 22 and outputs a write control signal WETV to the video memory 26. The clock signal CKAD is a signal synchronized with the horizontal synchronization signal from the video signal decoder 21, and has a period of 1 / N (N is a positive integer) of the period (for example, 63.5 μs) of the horizontal synchronization signal. The write control signal WETV is a signal that permits writing of the digital RGB luminance signal 25 coming from the ADC 22. The specific form of the write control signal WETV differs depending on the specifications of the video memory 26, but is generally a set of a plurality of control signals. For example, a signal for designating or incrementing a pixel address in the storage screen of the video memory 26,
Control signal for permitting writing in pixel units on the screen, non-control signal for permitting writing only to a desired area on the storage screen of the video memory 26, NTSC composite video signal 5
And a control signal for permitting writing only in a desired area in the horizontal direction in the horizontal direction on the screen. These control signals are all sent to the digitizing control
It is created by multiplying the write basic synchronization signal created inside 24 by changing the signal level when the coefficient result reaches a set value. These setting values can be adjusted based on a command from the personal computer 2. By appropriately selecting these setting values, it is possible to arbitrarily specify the resolution, the aspect ratio, and the like. That is, the NTSC composite video signal 5 is stored in the video memory 26.
Can be arbitrarily reduced in the horizontal and vertical directions. Further, the count for creating each control signal is reset for each vertical synchronization signal of the NTSC composite video signal 5. Accordingly, writing of a 2: 1 interlaced video signal in which a vertical synchronization signal is inserted for each field like the NTSC composite video signal 5 is performed in field units.

The superimposition control unit 31 controls reading of video data stored in the video memory 26. The superimpose control unit 31 sends a read control signal to the video memory 26, sends a clock signal CKDA to a D / A converter (DAC) 32, and outputs a video signal CKDA based on the conditions instructed by the personal computer 2. Superimpose permission signal 42 to switch 34
Is sent. Reading of video data by the superimpose control unit 31 is performed completely independently of writing by the digitize control unit 24. The internal configuration of the superimpose control unit 31 will be described later with reference to FIG.

DAC 32 is a digital RGB read from video memory 26.
The luminance signal 40 is sampled at the timing of the clock signal CKDA and converted into an analog RGB luminance signal 41.

The video switch 34 outputs a superimpose permission signal 42
, And superimposes the analog RGB luminance signal output from the DAC 32 on the RGB luminance signal of the personal computer video signal 3 arriving from the input terminal 35, and outputs it as a new RGB luminance signal 44.

The video signal output terminal 38 is connected to the RGB
This terminal outputs a luminance signal 44 and a horizontal / vertical synchronization signal from a video signal input terminal 35. The video signal 8 (RGB luminance signal and synchronization signal) from this output terminal 38 is supplied to a personal computer monitor 9.

Here, the superimpose control unit 31 will be described in detail. FIG. 3 shows the superimpose control unit shown in FIG.
FIG. 31 is a block circuit diagram of 31 and its peripheral circuits. The video memory 26 shown here is a CXK1206 manufactured by Sony Corporation, and the data sheet number 71215-ST, on pages 27 to 31, includes:
A timing chart related to the read port is described. The port used is read port 1 of the second page of the data sheet.

In the video memory 26, the memory drive clock signal HDCK is applied to the port 1 shift signal terminal CKR1, the memory vertical / horizontal reset signal MRST is applied to the port 1 vertical clear terminal VCLR1, and the horizontal reset signal HRST is applied to the port 1 horizontal clear terminal HCLR1.
The vertical offset signal VROFT or the vertical line clock signal VRLCK is connected to the port 1 line increment terminal INC1.
Then, signals VINC, MRST, HRST and SENBL for controlling the port 1 are supplied to the port 1 output enable terminal RE1 (negative logic). In addition, the analog RGB signal LSMEM (1 of R, C, B)
Data, respectively) is read from the port 1 data output DO ₁₀ to DO _13.

The port 1 shift signal CKR1, port 1 vertical clear VCLR1, port 1 horizontal clear signal HCLR1,
The analog RGB signal LSMEM read-controlled by the port 1 line increment signal INC1 and the port 1 output enable RE1 (negative logic) is, for example, 4 bits for each of R, G, and B, and the port 1 data outputs DO _{10 to} DO _{13 respectively.} Output.

The video switch 34 outputs the input of the A terminal or the B terminal from the C terminal in response to the switching signal CNT (= superimpose permission signal 42) input to the switching signal input terminal. Specifically, when the switching signal CNT is at the high level “H”, B
When the input of the terminal is at the low level “L”, the input of the A terminal is output from the C terminal.

The CPU bus 610 is connected to the personal computer 2. Reference numeral 421 is a horizontal reference read dot clock signal HBD.
Reference numeral 422 denotes a horizontal reference read dot clock generator that outputs CK, 422 denotes a horizontal read start counter that outputs a horizontal read start A signal HRSA and a horizontal read direction reset signal HRST, and 423 outputs a horizontal reference start B signal HSB. Reference numeral 424 denotes a horizontal read counter which outputs a horizontal read count signal HRT, and reference numeral 425 denotes a horizontal read dot clock generator which outputs a horizontal read dot clock signal HDDA.

The memory vertical reading offset counter 426 has a function of allowing the personal computer 2 to arbitrarily set the count number of the horizontal reference reading dot clock generator 421, and outputs a vertical reading offset signal VROFT. The vertical blanking number counter 427 outputs a vertical blanking end signal VBE, the vertical read start counter 428 outputs a vertical read start signal VRS, the vertical read number counter 429 outputs a vertical read number signal VRT, and the vertical read line Clock generator 430 outputs a vertical read line clock signal VRLCK.
The AND circuit 431 outputs a superimpose permission signal SENBL, the OR circuit 432 outputs either a vertical read offset signal or a vertical read line increment signal VRLCK as a port line increment signal INC1, and a NOR circuit 4
33 outputs a read enable RE1 signal. Also, code 4
34 and 435 are tri-state circuits, and 436 is an inverter circuit.

An analog RGB luminance signal coming from a color input terminal 506 forming a part of the video input terminal 35 is supplied to an A terminal of the video switch 34. The horizontal synchronization signal HSPC coming from the synchronization terminal 507 which forms a part of the input terminal 35 includes a horizontal reference read dot clock generator 421, a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read number counter 424, and a vertical read offset. Synchronous signal terminals 490 and 491 which are provided to a counter 426, a vertical blanking number counter 427, a vertical read start counter 428, a vertical read number counter 429, and a vertical read line clock generator 430, and also form a part of the output terminal 38.
Respectively. The vertical synchronizing signal VSPC coming from the synchronizing terminal 508 forming a part of the input terminal 35 includes the video memory 26, the vertical offset counter 426, the vertical blacking number counter 427, the vertical reading start counter 428, the vertical reading number counter 429, The signal is supplied to the vertical readout line clock generator 430 and sent to a synchronizing signal terminal 491 which is a part of the output terminal 38.

Horizontal read start counter 422, horizontal 64 clock counter 4
23 and the horizontal readout circuit counter 424 receive the horizontal synchronization signal HSPC.
Resets the count value. The count values of the vertical read offset counter 426, vertical blacking number count 427, vertical read start counter 428, and vertical read number counter 429 are reset by the vertical synchronization signal VSPC.

The signal HBDCK generated by the horizontal reference read dot clock generator 421 is supplied to a horizontal read start counter 422, a horizontal 64 clock counter 423, a horizontal read number counter 424, and a vertical read offset counter 426, and also through a tristate circuit 435. Clock signal HDC for video memory 26
As K, port 1 shift signal terminal CKR1 of video memory 26
Sent to

Further, the horizontal read dot clock generator 425 synchronized with the horizontal read start signal B HRSB, is constituted by a PLL circuit for outputting a frequency N ₂ times the frequency of the signal of the horizontal read start signal B HRSB, horizontal read dot clock Outputs signal HDDA. FIG. 4 shows the configuration of the horizontal readout section including the PLL circuit. This PLL circuit is a circuit that synchronizes a signal of a voltage controlled oscillator (VCO) with a reference clock signal to generate a stable clock signal. The horizontal read dot clock signal HDDA generated by the horizontal read dot clock generator 425 is
The clock signal HDCK of the video memory 26 is supplied to the port 1 shout signal terminal CKR1 and the DAC 32 of the video memory 26 via the tristate circuit 434, and the digital RGB luminance signal LS
It is used as a read clock signal for the MEM and a conversion clock signal for the DAC 32.

Furthermore, line clock generator 430 output vertical read is synchronized with the vertical synchronizing signal VSPC, is constituted by a PLL circuit for outputting a signal N ₃ times the frequency of the vertical synchronizing signal VSPC, the vertical read line clock signal VRLCK Output. The vertical read line clock signal VRLCK generated from the vertical read line clock generator 430 is synchronized with the clock signal HDCK of the video memory 26, and is a line address which is a vertical address of the video memory 26 via the OR circuit 432. To the port 1 line increment terminal INC1 and the port 1 via the OR circuit 432 and the NOR circuit 433.
Output enable RE1 terminal (negative logic).

The superimpose control unit 31 uses these horizontal reference read dot clock signal HBDCK, horizontal read dot clock signal HDDA, and vertical read line clock signal VRLCK,
Basic timing is gained.

In addition, the vertical read offset counter 426 is
The vertical synchronization signal V
After the count value is reset by the SPC, the vertical offset signal that advances the vertical line address of the video memory 26 in synchronization with the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421. VROFT is sent to OR circuit 432.

Further, the analog blanking counter 427 has an analog R
There is a counter (not shown) for deleting the vertical back porch area of the GB luminance signal LSPC. This counter counts the number of clocks of the horizontal synchronization HSP, and outputs a vertical blacking end signal VBE to the vertical read start counter 428 after passing the vertical back porch area. Vertical read start counter 4
Numeral 28 receives the enable signal (vertical blanking end signal VBE) sent from the vertical blanking number counter 427, counts the number of clocks of the horizontal synchronizing signal HSPC, and stores the video memory.
The read start permission signal (vertical read start signal) for the vertical direction from 26 is output to the VRS vertical read number counter 429.
The vertical reading counter 429 receives the permission signal (control signal VRS) sent from the vertical reading start counter 428, counts the number of clocks of the horizontal synchronizing signal HSPC, and
, And outputs a signal indicating a read period in the vertical direction, that is, a vertical read count signal VRT to the AND circuit 431.

And the vertical reading offset counter described above
426, a vertical blanking number counter 427, a vertical read start counter 428, a vertical read number counter 429, and a vertical read line clock generator 430 perform vertical read control of the video memory 26.

The number of clocks of the horizontal reference read dot clock signal HBDCK counted by the vertical read offset counter 426, the number of clocks of the horizontal sync signal HSPC counted by the vertical read start counter 428, and the number of horizontal sync signals HSPC counted by the vertical read counter 429 are counted. The number of clocks is set to a required value according to an instruction from the personal computer 2.

On the other hand, the horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421, and outputs a read start permission signal (horizontal read start) for the video memory 26 in the horizontal direction. A signal HRSA) to the horizontal 64 clock counter 423. The horizontal 64 clock counter 423 outputs a permission signal (horizontal read start A) transmitted from the horizontal read start counter 422.
Signal HRSA), the horizontal reference read dot clock signal H output from the horizontal reference read dot clock generator 421.
Counts the number of BDCKNC clocks. Then, when the count value reaches 64 clocks, which is a characteristic at the time of reading of the video memory 26, the horizontal reading start B signal HRSB is sent to the horizontal reading number counter 424, the horizontal reading dot clock generator 425, and the AND circuit 4
Output to 31. The horizontal reading number counter 424 counts the number of clocks of the horizontal reference reading dot clock signal HBDCK sent from the horizontal reference reading dot clock generator 421, and outputs a permission signal (a horizontal reading number signal HRT) for the reading period of the video memory 26 in the horizontal direction. ) To the AND circuit 431.

Thus, the horizontal read control for the video memory 26 is performed by the horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read number counter 424. The number of clocks of the horizontal reference read dot clock signal HBDCK counted by the horizontal read start counter 422 and the number of clocks of the reference dot clock signal HBDCK counted by the horizontal read circuit counter 424 are set to required values by the personal computer 2, respectively. You.

Next, regarding the operation of the superimposition control unit 31,
This will be described with reference to FIGS. 5, 6, and 7. FIG. FIG. 5 is a timing chart of vertical read permission of the video memory 26, FIG. 6 is a timing chart of vertical offset of the video memory 26, and FIG.
8 is a timing chart of horizontal read permission, and FIG. 8 is a timing chart of horizontal read of the video memory 26.

First, regarding the vertical read permission of the video memory 26,
This will be described with reference to FIG.

When the vertical synchronization signal VSPC becomes high level “H” (fifth
(See (a) of FIG.), The vertical blanking number counter 427, the vertical read start counter 428, and the vertical read number counter 429 are reset, and the vertical blacking end signal VBE, the vertical read start signal VRS, and the vertical read number signal VRT are respectively low. The level becomes “L” (see FIGS. 5 (d), (e) and (f)), and the vertical blacking number counter 427 outputs the horizontal synchronization signal H.
The number of clocks of the SPC is counted, and after passing the vertical back porch area, the vertical blacking end signal VBE is set to the high level “H” (see FIG. 5D). When the vertical blacking end signal VBE becomes high level “H”, the vertical read start counter 428 starts counting the number of clocks of the horizontal synchronization signal HSPC. When the vertical read start counter 428 counts the value set by the personal computer 2, the vertical read start signal VRS is set to the high level "H" (see FIG. 5 (e)). When the vertical read start signal VRS goes to the high level “H”, the start of reading of the digital RGB signal LSMEM in the vertical direction of the video memory 26 is permitted. Start counting the number of HSPC clocks. When the vertical reading circuit counter 429 counts the value set by the personal computer 2, the vertical reading number signal VR
T is set to the high level "H" (see FIG. 5 (f)).

During the period in which the vertical read start signal VRS is at the high level “H” and the vertical read count signal VRT is at the low level “L”, the horizontal read start B signal HRSB is at the high level “H” and the horizontal read count signal HRT is If it is low level “L”, the AND circuit 431 outputs a high level “H” superimpose permission signal SENBL. Therefore, in the video memory 26, the digital RGB signal LSMEM is read based on the vertical read permission during this time.

Next, regarding the vertical offset of the video memory 26, the sixth
This will be described with reference to the drawings.

When the vertical synchronization signal VSPC becomes high level “H” (6th
After the vertical read offset counter 426 is reset, the horizontal reference read dot clock signal HBDC is reset.
Start counting K clocks. While the vertical read offset counter 426 counts the value set by the personal computer 2, the vertical read offset signal
VROFT is supplied to the port 1 line increment INC1 of the video memory 26 via the OR circuit 432 (see FIG. 6 (c)) to offset the vertical read address value of the video memory 26.

At this time, since the vertical synchronization signal VSPC and the vertical read offset signal VROFT are supplied to the NOR circuit 433, the read enable signal RE1 (negative logic) is supplied to the read enable terminal RE1 (negative logic) of the video memory 26, and the read operation is performed. It is allowed. Then, when the value set by the personal computer 2 is counted, a vertical offset is performed, so that the vertical read offset counter 426 stops outputting the vertical read offset signal VROFT until the next vertical synchronization signal VSPC arrives.

Next, the read permission of the video memory 26 in the horizontal direction will be described with reference to FIG.

When the horizontal synchronization signal HSPC is output, the horizontal reading start counter 422, the horizontal 64 clock counter 423, and the horizontal reading number counter 424 are reset, and the horizontal reading start A signal H is reset.
The RSA, the horizontal read start B signal HRSB, and the horizontal read count signal HRT become low level "L" (FIG. 7 (d),
(See (e) and (f)). And a horizontal read start counter
Reference numeral 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421, and when the count value reaches a value set by the personal computer 2, a horizontal read start A signal HR
SA is set to the high level "H" (see FIG. 7 (d)). When the horizontal read start A signal HRSA becomes high level “H”, the horizontal 64 clock counter 423 counts the number of clocks of the reference read dot clock signal HBDCK, and the count value becomes 6
At 4, the horizontal read start B signal HRSB is set to the high level "H" (see FIG. 7 (e)). Note that the horizontal 64 clock counter 423 has a count value of “64” and the high level “H” of the horizontal read start B signal HRSB due to the characteristics of the video memory 26.
And is not limited to 64.

When the horizontal read start B signal HRSB becomes high level “H”, it means that horizontal read of the video memory 26 has been permitted, and the horizontal read counter 424 counts the number of clocks of the horizontal reference read dot clock signal HBDCK. Start counting. When the count value reaches the value set by the personal computer 2, the horizontal reading number signal
HRT is set to the high level "H" (see FIG. 7 (f)).
Further, the horizontal read dot clock generator 425 is synchronized with the horizontal read start B signal HRSB, and outputs the horizontal read dot clock signal.
Output HDDA. When the vertical read start signal VRS is at high level “H” and the vertical read count signal VRT is at low level “L”, the horizontal read start B signal HRSB is at high level “H”.
And the horizontal read count signal HRT is low level "L".
AND circuit that receives the horizontal read error count signal HRT only for a certain period
From 431, a high-level “H” superimpose permission signal signal SENBL is output. Therefore, the video memory 26
Then, the digital RGB signal LSMEM is read based on the vertical read permission during this time.

Next, regarding horizontal reading of the video memory 26,
This will be described with reference to FIGS. The video memory 26 is supplied with a drive clock signal HDCK. The drive clock signal HDCK is a horizontal reference read dot clock signal HBDCK.
(See FIG. 8 (e)) and the horizontal read dot clock signal HD
It is generated from DA (see FIG. 8 (f)). That is, when the superimpose permission signal SENBL is at the low level “L”, the tristate circuit 435 operates to supply the horizontal reference read dot clock signal HBDCK to the video memory 26 as the drive clock signal HDCK (FIG. 8). (D),
(E), (g)). When the superimpose permission signal SENBL becomes high level "H", the horizontal read dot clock signal HDDA is supplied to the video memory 26 as the drive clock signal HDCK (FIGS. 8 (d), (f), (g)).
reference. At this time, the digital signal from the video memory 26
The reading of the LSMEM and the analog conversion of the DAC 32 are performed.

This will be described in detail. When the superimpose permission signal SENBL is at the low level “L”, the video memory 2
No reading is performed from step 6, and the address is advanced to the vertical reading offset point, and so-called reading of digital RGB signals in the horizontal / vertical region where superimposition is not performed is performed. In this case, the operation is only in memory,
The horizontal reference read dot clock signal HBDCK is supplied to the video memory 26 as the drive clock signal HDCK. On the other hand, when the superimpose permission signal SENBL is at the high level “H”, reading from the video memory 26 is performed. That is, when data is read from the video memory 26, the drive clock signal HDCK is set to the horizontal reference read dot clock signal HBDC
When the frequency is lower than K, the readout is enlarged. On the other hand, when the frequency is higher, the readout is reduced. When the frequency is the same, the readout is performed (one-to-one). The data can be displayed in an enlarged, reduced, or (one-to-one) manner with reference to the drive clock signal HDCK.

By the way, in the conventional image processing apparatus, the clock signal given to the video memory 26 is the horizontal reference read dot clock HB.
The state of the horizontal read dot clock HDDA at the timing of switching from DCK to the horizontal read dot clock HDDA was not constant. The reason is as follows.

The timing of switching from the horizontal reference read dot clock HBDCK to the horizontal read dot clock HDDA is given by a superimpose permission signal SENBL. This signal is synchronized with the timing at which the horizontal reference start B signal HRSB becomes high level “H”. I have. Then, the horizontal reference start B signal HRSB becomes high level “H” 64 clocks after the horizontal reference start A signal HRSA becomes high level “H”. Further, the timing at which the horizontal reference start A signal HRSA becomes high level “H” can be freely changed by rewriting the set value of the horizontal read start counter 422 in the personal computer 2. Since the superimpose permission signal SENBL is indirectly synchronized with the horizontal reference start A signal HRSA which is such a variable signal, the timing at which the superimpose permission signal SENBL becomes high level “H” also becomes variable. On the other hand, the horizontal read dot clock HDDA is a signal having a fixed period synchronized with the horizontal synchronization signal HSPC. Therefore, the state of the horizontal read dot clock HDDA at the timing when the superimpose permission signal SENBL becomes high level “H” is not definitive. If the state of the horizontal read dot clock HDDA at the timing when the superimpose permission signal SENBL becomes high level “H” is indeterminate, an extra pulse is generated in the drive clock signal HDCK due to the influence of the jitter described above. There are cases. The following describes this problem.

First, four states shown in FIG. 9 can be considered as the states of the horizontal read dot clock HDDA at the timing when the clock signal supplied to the video memory 26 switches from the horizontal reference read dot clock HBDCK to the horizontal read dot clock HDDA. The first state is a state where the high level "H" is maintained before and after the switching (see FIG. 9 (c)). And the second
The state is a state where the low level “L” is maintained before and after the switching (see FIG. 9D). Further, the third state is a state in which the level changes from the high level “H” to the low level “L” at the switching timing (see FIG. 9E). Further, the fourth state is a state where the level changes from low level "L" to high level "H" at the switching timing (see FIG. 9 (f)). The drive clock signal HDCK consists of a horizontal reference read dot clock HBDCK and a horizontal read dot clock HDD.
A is a synthesized signal (FIGS. 9 (g), (h),
(See (i) and (j)).

The third state is affected by jitter. In other words, in the third state, if there is no influence of jitter, the timing at which the superimpose permission signal SENBL becomes high level "H" and the timing at which the horizontal read dot clock HDDA changes from high level "H" to low level "L" Are identical (see FIG. 10 (c)), but when affected by jitter, the signal shifts backward (see FIG. 10 (d)) or shifts ahead (see FIG. 10 (e)). ). Due to this shift, the drive clock signal HDCK also becomes a signal including the shift (see FIGS. 10 (f), (g) and (h)). When the signal is shifted backward due to the influence of the jitter, a clock signal that is one pulse extra is generated compared to the case where the signal is not affected by the jitter or the signal is shifted before due to the influence of the jitter.
For this reason, in the conventional video processing apparatus, partial image disturbance has occurred.

The present embodiment is designed so as not to generate this extra pulse. That is, the superimpose permission signal SE
By generating the horizontal read dot clock HDDA at the same timing as when the NBL goes to the high level “H”, the signal in the fourth state (see FIG. 9 (f)) is always maintained. And in the video memory,
The drive clock signal HDCK in the fourth state is applied (see FIG. 9 (j)). At this timing, no extra pulse is generated even if jitter occurs. The reason is as follows.

When the driving clock signal HDCK maintains the fourth state,
As in the third state, the signal is shifted backward or forward due to the influence of jitter. The drive clock signal HDCK in this case becomes a signal containing a shift similarly to the third state, but the pulse number itself does not change only by changing the pulse width of the clock signal (FIG. 11 (f), (G),
(H)). In other words, if the fourth state can always be maintained,
Even if jitter occurs, no extra pulse is generated and a clear image can be obtained. In the present embodiment, the conventional problem is solved by holding the fourth state, but the same effect can be obtained by holding the first state or the second state.

Further, the above-described timing chart is an example, and the above-described operation can be performed even when each signal is positive logic or negative logic.

Next, the operation of this embodiment after reading from the video memory 26 will be described.

Analog RGB coming from the color input terminal 506 as described above
The signal LSPC is input to the point A of the video switch 34. or,
The analog RGB signal LSDA read from the video memory 26 and converted by the DAC 32 into analog
Entered at the point. Therefore, by switching the video switch 34 by the superimpose permission signal SENBL,
Analog RGB signal LSMON output from video switch 34
Represents an analog-converted RGB signal LSDA in an image corresponding to the analog RGB signal LSPC coming from the color input terminal 506.
Are output from the output terminal 505 as a signal LSMON corresponding to the image obtained by superimposing the image corresponding to the image. In addition to the output of the analog RGB signal LSMON, the horizontal synchronizing signal and the vertical synchronizing signal VSPC are also output from the output terminal 38 (including the output terminal 505). Note that the above-described timing chart is an example, and the above-described operation can be performed even when each signal is positive logic or negative logic.

Also, as can be seen from the configuration of FIG. 3, the high level "H"
Is output to the tri-state circuit 434 via the NOT circuit 436,
The tristate circuit 434 operates, and the horizontal read dot clock signal HDDA is sent out as the drive clock signal HDCK. Conversely, when the superimpose permission signal SENBL is at the low level “L”, the tristate circuit 435 operates, and the horizontal reference read dot clock signal HBDCK is supplied to the video memory 26 as the drive clock signal HDCK. That is, when the superimpose is performed when the superimpose permission signal SENBL is at the high level “H”, the video memory 26 is accessed by the horizontal read dot clock HDDA output from the horizontal read dot clock generator 425, and the digital RGB The signal LSMEM is read. On the other hand, when the superimpose permission signal SENBL is at the low level “L” and superimposition is not performed, the video memory 26 is accessed by the horizontal reference read dot clock HBDCK from the horizontal reference read dot clock generator 421, and the vertical read is performed. Address advance to the offset point,
The so-called skipping of the digital RGB signals in the horizontal / vertical region where the superimposition is not performed is performed so as to prepare for the timing when the next superimposition permission signal SENBL becomes high level “H”.

By such an operation, as shown on the personal computer monitor 9 in FIG. 2, the child screen 7 by the external video signal is inserted at an arbitrary position in the parent screen 6 by the personal computer video signal in an arbitrary enlarged / reduced state. A composite screen can be obtained.

〔The invention's effect〕

According to the image processing apparatus of the present invention as described above,
A stable clock signal can be supplied to the video memory without being affected by the jitter, and a video free from fluctuation in the horizontal direction can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an application example of this embodiment, FIG. 3 is a block diagram showing an internal configuration of a superimpose control section, FIG.
5 is a block diagram showing the internal configuration of the horizontal read portion of the superimpose control unit. FIGS. 5 to 9 are waveform diagrams showing the operation of the superimpose control unit. FIG. FIG. 11 is a waveform chart showing the influence of jitter in the fourth state. 1 ... video processing device, 2 ... personal computer,
3 PC video signal 5 NTSC composite video signal 6
…… Main screen, 7 …… Sub screen, 9 …… PC monitor, 21
... Video signal decoder, 22 ... ADC, 24 ... Digitize control unit, 26 ... Video memory, 31 ... Superimpose control unit, 32 ... DAC, 34 ... Video switch, 35 ... Video input terminal , 38 ... Video output terminal.

Claims (2)

(57) [Claims] 1. A / D conversion means for converting a luminance signal of a first video signal into a digital luminance signal; a video storage means for storing a digital luminance signal from the A / D conversion means; Reading means for reading a digital luminance signal; mixing means for partially replacing a luminance signal of the second video signal with the luminance signal read from the reading means; reading from the reading means during a screen by the second video signal Control means for controlling each of the means based on a command indicating how to insert a screen based on the emitted luminance signal, wherein the control means reads a horizontal read start reference position. It can be arbitrarily set based on the timing control of the start signal. In the dot reading of the horizontal line from the video storage means, the video storage means Image processing apparatus, characterized in that the first clock signal at a position where a dot clock signal by a predetermined dot count from the read start reference position or there is for switching to the second clock signal to be supplied to. 2. The video processing device according to claim 1, wherein a first PLL (phase locked loop) circuit using a horizontal synchronization signal as a clock signal outputs the first clock signal, and the first clock signal And a counter circuit that can set an arbitrary count value as an input signal. An output signal from the counter circuit becomes a reference phase signal using a signal synchronized with the read start signal as an input signal of the second PLL circuit. Wherein the second PLL circuit generates the second clock signal as an output signal.