JPS62146093A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To display two videos as a master and a secondary pictures and to display the video having no noise or skew when inputting a video signal during a high speed reproduction of a VTR and during a reverse rotation and high speed reproduction for the secondary picture by including a memory for storing the video signal, a circuit controlling it and a circuit of a time base correction in the VTR. CONSTITUTION:The AD converted signal 13 for the secondary picture is converted into a parallel signal by a serial/parallel converting circuit 14, written in the memory 31, and stored only during a determined period of a horizontal synchronizing period in a rate of 1H period to 3H period by the timing control circuit 33. A multiplexer 29 outputs the signal 28 for the secondary picture onlyduring a period in which both vertical and horizontal signals of the master picture go high and during other periods, outputs the signal 5 for the master picture in the operation. The timing control circuit 33, when the multiplexer 29 outputs the signal 28, controls a memory address generating circuit 32 so as to output the signal for displaying the secondary picture stored in the memory 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is capable of displaying two images simultaneously on one screen by incorporating a memory for storing image signals, a circuit for controlling the same, and a circuit for time axis correction. A magnetic device that can display images as a parent and child screen, and display images without noise or skew even when inputting a video signal for high-speed playback of a video tape recorder (TR) or high-speed reverse playback as a video signal for displaying a child screen. The present invention relates to a recording/reproducing device.

BACKGROUND OF THE INVENTION The development of memory technology and digital technology in recent years has been remarkable, and even in the field of video equipment, the introduction of digital technology has rapidly reduced costs, improved performance, and increased functionality.

In the field of television receivers (hereinafter abbreviated as TV), such digitization was promoted from an early stage, and as one of the multi-functionality features, field memory for storing screen images was installed, allowing for the recording of images within a single screen. TVs have already been developed that can reduce and display images stored on the screen. Also VT
In the field of R, there is also a growing movement to improve the performance of conventional analog technology by introducing digital technology.

For slow playback and still playback, which are one of the VTR's special playback functions, the VTR has a built-in field memory that stores one screen, and the signal is stored only during the period when sufficient playback output from the video head is obtained. A VTR that plays back images free of noise and noise by storing and reading them.
has already been developed.

Another important feature of the VTR's special playback function is
There are high-speed playback and reverse high-speed playback. In this mode, the tape is fast forwarded or rewound so quickly that the video head traces across multiple tracks recorded with alternating azimuth heads, but the two main By providing auxiliary heads with different azimuth angles in the vicinity of the head and appropriately switching these heads so as to always obtain sufficient reproduction output, it is possible to obtain reproduction output without noise.

Problems to be Solved by the Invention However, during the above-mentioned high-speed playback and reverse high-speed playback,
Since the playback outputs of different tracks are connected by switching heads, the horizontal synchronization signal becomes discontinuous at this switching section, causing skew. Although a means for correcting this skew using a variable delay line has been proposed, it has not been possible to sufficiently remove the skew.

The present invention provides a memory for storing video signals in a VTR;
By incorporating a circuit to control it and a circuit for time axis correction, it is possible to simultaneously display two images on the screen as a parent and child screen, and to use V as a video signal for displaying the child screen.
To provide a magnetic recording and reproducing device capable of displaying an image without noise or skew even when inputting a video signal during high-speed reproduction of TR or high-speed reverse reproduction.

Means for Solving the Problems In order to solve the above problems, the magnetic recording and reproducing apparatus of the present invention provides a signal for switching two composite video signals into a main screen display signal and a sub screen display signal, respectively. a switching circuit; a demodulator that demodulates a small screen display signal among the signals switched by the signal switching circuit into a luminance signal Y and two color difference signals R-Y and B-Y; and an output of the demodulator. A multiplexer that multiplexes the luminance signal and two color difference signals to be sent out, an analog/digital (AD) converter that converts the output signal of the multiplexer into a digital signal, and an analog/digital (AD) converter that converts the output of the AD converter into a parallel signal. a serial-to-parallel conversion circuit; a memory for storing the output signal of the serial-to-parallel conversion circuit; and a parallel converter for converting the signal read from the memory into a serial signal.
a serial conversion circuit; and a first digital/analog converter for converting the output signal of the parallel-serial conversion circuit into an analog signal.
DA) converter, second and third ODA converters for converting the signal read from the memory into an analog signal; Second. a modulator that modulates three signals respectively output from the third DA converter; and a multiplexer that multiplexes the main screen display signal that is one output of the signal switching circuit and the output signal of the modulator. , a memory address generation circuit that generates an address for accessing the memory, and a timing control circuit that generates a write timing control signal when writing a signal to the memory based on a horizontal synchronization signal of the child screen display signal. It is prepared.

Function The present invention uses the above-described configuration to convert two video signals into
It is possible to output signals in a mixed format so that one side can be displayed as a main screen and the other as a sub screen, and the timing of writing when storing signals that should not be displayed on the sub screen in memory. By generating the horizontal synchronization signal of the signal as a reference, the time axis of the signal is corrected, and as a result, the horizontal synchronization signal can be used as a sub-screen signal, like the signal during high-speed playback or high-speed reverse playback of a VTR. Even when a signal with phase discontinuity is input, an image without skew can be reproduced.

Embodiments Hereinafter, magnetic recording and reproducing apparatuses according to embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In Figure 1, 1 and 2 are video input terminals, 3 is a signal switch, 4 and 6 are output signals of the signal switch, and 6 is a signal 4.
7,8°9 is the output signal of the demodulator 6, 1o is the multiplexer that multiplexes the signals 7,8°9, 11 is the output signal of the multiplexer, 12 is the signal 11'! ! - AD converter for converting into a digital signal, 1
3 is a digital signal that is the output of 12 AD converters, 1
4 is a serial-to-parallel conversion circuit that converts the signal 13 into parallel; 16 is a parallel digital signal that is the output of the serial-to-parallel conversion circuit 14; 31 is a memory for storing the signal 16; 16, 19.20 are digital signals read from the memory 31; 17 is a parallel-to-serial conversion circuit that converts the signal 16 into a serial signal; 18 is an output signal of the parallel-to-serial conversion circuit 17;

21, 22, and 23 are the digital signals 18 and 23, respectively.
19, 20'ii DA converters for converting into analog signals; 24, 25; 26 are DA converters 21, 22, respectively;
．． The analog signal which is the output of 23, 27 is the signal 24, 2
28 is the output signal of the modulator 27, 29 is a multiplexer that multiplexes signals 6 and 28, and 3o is the output signal of the multiplexer 29.

32 is a memory address generation circuit that controls the access address of the memory 31; 33 is a multiplexer 1o and an AD
A timing control circuit that generates signals for controlling the converter 12, the serial-parallel conversion circuit 14, the memory 31, the parallel-serial conversion circuit 17, the DA converters 21, 22, 23, the multiplexer 29, and the memory address generation circuit 32. be. 3
4 is a signal that controls the multiplexer 1o, 36 is a clock signal for the AD converter 12, and 36 is a serial-parallel conversion circuit 1
37 is a signal that controls the parallel-to-serial conversion circuit 17 , 38 is an address signal that specifies the address of the memory 31 , 39 is a signal that controls the memory address generation circuit 32 , 40 is a signal that controls the memory 31 Signal, 41 is D
A signal 42 controls the A converter 21, 22, 23'i, and the multiplexer 29. 43 is signal 4
44 is a sync separation circuit that separates the horizontal sync signal and vertical sync signal from the signal 6; 46 is a sync separation circuit that separates the horizontal sync signal and vertical sync signal from the signal 6; The vertical synchronization signal 46 is a horizontal synchronization signal and a vertical synchronization signal separated by the synchronization separation circuit 44.

The operation of the magnetic recording/reproducing apparatus of this embodiment configured as described above will be described below with reference to FIGS. 1 to 6.

First, in FIG. 1, the video signal input terminal 1゜2 has the following:
Composite video signal, e.g. tuner output signal or VT
An R reproduction signal is input. These two composite video signals are
The signal is switched between signal 4 and signal 6 by signal switch 3. Signal 6 is a main screen display signal that is displayed in the size of the entire display screen, and signal 4 is a signal that is about one-third the size of the entire display screen, both vertically and horizontally, and is inserted into the main screen. This is a signal for displaying a small screen. A signal 4, which is a signal for displaying a small screen, is demodulated by a demodulator 6 into a luminance signal Y and two color difference signals RY and BY.

Signals 7, 8.9 correspond to this, respectively. The luminance signal Y and the color difference signals R-Y and B-Y are multiplexed by a multiplexer 1o.
3H period), the luminance signal Y is output during two horizontal synchronization periods (2H period), and the remaining one horizontal synchronization period outputs the luminance signal Y and the color difference signals R-Y and B-Y, . . . Y, R. -Y, Y,
B-Y, Y, R-Y, Y, R-Y, Y.

It switches and outputs B-Y, Y, R-Y, . . . . FIG. 2 67 shows the output of the multiplexer at this time.

The signal 11 multiplexed in this manner is subjected to AD conversion by the AD converter 12. FIG. 2 68 shows the AD conversion clock at this time. The analog signal 11 is converted into a digital signal at the rising edge of this clock.

The AD-converted signal 13 is converted by a serial-parallel conversion circuit,
The signals are converted into parallel signals and written into the memory 31. This operation will be explained with reference to FIG.

FIG. 3 is a diagram for explaining the operation of reading and writing signals to and from memory. In Figure 3, 80°81 is a shift register, 82.84, 85.86 are latch circuits (D
87 to 95 are digital signals, 83 is a 3-state buffer, 13 is a signal input terminal, 18, 19° 20 is a signal output terminal, 62, 63
, 64, 65°66', 69', and 70' are control signal input terminals.

(When the signal 11 is converted into an n-bit digital signal by the AD converter shown in FIG. 12, the number of shift registers 80 and 81 shown in FIG. 3 is n, respectively.) A digital signal corresponding to 13 in FIG. 1 is input. This signal is shown in Fig. 269.
The signals are sequentially stored in the shift register 8o at the rising timing of the clock shown in FIG. Six pieces of data are sequentially stored in the shift register 8o, and when the six pieces of data are collected, they are latched into the launch circuit 82 at the rising timing of the clock shown in FIG. 270. The signal launched into the latch circuit 82 is output to the data bus of the memory by the 3-state buffer 83 during the period when the signal shown in FIG. 2 65 is High.

During the period when the signal 66 in FIG. 2 is Low, the output of the 3-state buffer 83 is in a high impedance state. The signal output to the data bus of the memory is WE as shown in FIG.
The doubled signal is stored in memory. This WE multiplied signal is controlled by the timing control circuit shown in FIG. 133 for one horizontal synchronization period (3H period) of the signal shown in FIG.
1H period), and is controlled to be Low only during a certain period of the horizontal synchronization period. Therefore, only the signals for this period are stored in the memory.

The signal stored in the memory is then latched by the latch circuit 84 at the rising timing of the clock shown in FIG. 264. Of the signals latched by the latch circuit 84, the Y signal is input in parallel to the shift register 81, then shifted at the rising timing of the clock shown in FIG. 2, and sequentially output from the output terminal 18. This output signal corresponds to the signal in FIG. 18.

Also, among the signals latched by the latch circuit 84, R-
The Y and BY signals are respectively latched by latch circuits 85 and 86 at the rising timing of the tarlock shown in FIG. 263. The latched signals are output from the signal output terminals 19 and 20. These output signals correspond to signals 19 and 20 in FIG. 1, respectively.

As described above, the digital signals (18.19.20 in FIG. 1) read out from the memory are converted to 21.22 in FIG.
．． The DA converter shown in 23 performs DA conversion at the rising timing of the clock 61 in FIG. 2, respectively.

The three DA-converted signals are modulated by the modulator shown in FIG. 2 27 and input to the multiplexer 29 together with the signal shown in FIG. 1 6. The multiplexer 29 switches and outputs the signal shown in FIG. 1 5 and the signal shown in FIG. 1 28 so that these two signals are appropriately displayed as a parent and child screen. Next, the operation of appropriately inserting and displaying the child screen signal into the main screen signal will be explained using FIG.

First, as mentioned earlier, the signal for displaying the sub-screen is transmitted during the horizontal synchronization period at a ratio of one horizontal inter-period (1H period) to three horizontal inter-periods (3H period) of the sub-screen display signal. Only a certain fixed period of time is memorized.

In FIG. 4, reference numeral 100 indicates a horizontal synchronization signal of the small screen display signal, and 102 indicates a period during which the small screen display signal is stored in the memory. A small screen display signal is stored in the memory during a period W shown at 102 in FIG. In this way, when the signals written in the memory are to be displayed as a child screen, the timing of reading them must be synchronized with the main screen display signal. Figure 6 110
120 shows the vertical synchronization signal of the main screen display signal, and FIG. 6 120 shows the horizontal synchronization signal of the main screen display signal.

The multiplexer in FIG. 129 outputs the signal in FIG. 128 only during the period when the signal shown in FIG. 5 111 and the signal shown in FIG. 6 121 are both high, and at other times outputs the signal in FIG. Works to output. In the timing control circuit of FIG. 133, the multiplexer of FIG.
The memory address generation circuit is controlled so that the small screen display signal stored in the memory is output when the signal shown in FIG. 28 is being output.

As described above, the output signal shown in FIG. 130 can be obtained by inserting the sub-screen display signal into the main-screen display signal.

Next, the second section describes the operation when a signal with discontinuity in the horizontal synchronization signal, such as a signal during high-speed playback or reverse high-speed playback of a VTR, is input as a signal for displaying a sub-screen.
This will be explained with reference to the figures and FIG.

As mentioned above, in FIG. 4, 100 is the horizontal synchronization signal of the sub-screen display signal, and the sub-screen display signal is 10
The second signal is written during the High period. In FIG. 4, a signal 101 is the output of a mono multivibrator triggered by the horizontal synchronizing signal 100, and the rising position of 102 is determined by the fall of this signal. In this way, the position where the signal is written is
The AD converter clock after the signal 102 becomes High (68 in Figure 2) and the latch circuit 07 in Figure 3 82
This will be determined by the timing of the return (70 in Figure 2).

If the horizontal synchronization signal of the child screen is not synchronized with these clocks, the writing position will be different for each horizontal synchronization period, and if this signal is read out in a truncated manner, skew will occur.

Therefore, these two clocks, ie, the clocks 68 and 70 in FIG. 2, are reset at the beginning of the horizontal synchronization signal of the child screen.

By doing this, the position at which the signal is written into the memory is approximately the same as the horizontal synchronization signal, and the signal read out becomes a signal without skew.

As explained above, by adopting the configuration shown in FIG. 1 and generating the timing for writing the sub-screen display signal into the memory based on the horizontal synchronization signal of the sub-screen display signal, A VT that can output a signal in the form of a mixture of two video signals as a parent and child screen, and can also play back images without skew when displaying images during high-speed playback or reverse high-speed playback on the child screen.
R1 can be realized.

Effects of the Invention As described above, according to the present invention, it is possible to display a parent-child screen on a VTR, which could only be achieved with a special TV in the past. The effect of being able to see the screen is obtained. Furthermore, when displaying an image during high-speed playback or reverse high-speed playback of a VTR on a small screen, an excellent effect can be obtained in which an easy-to-see image without skew can be viewed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation, and FIG. 3 is a block diagram of the main part of this embodiment. FIG. 6 is a signal waveform diagram for explaining the operation. 1.2...Composite video input terminal, 3...Signal switcher, 6...Demodulator, 10, 29...
...Multiplexer, 12...AD converter, 14...Series-parallel conversion circuit, 17...
Parallel-serial conversion circuit, 21゜22.23...DA converter, 27...Modulator, 31...Memory, 32...Memory address generation circuit, 33...・・・
Timing control circuit, 43.44...Synchronization separation circuit, 80.81...Shift register, 82.
84, 85.86...Latch circuit.

Claims (1)

[Claims] A signal switching circuit that switches two composite video signals into a main screen display signal and a sub screen display signal, respectively, and a luminance signal Y and a sub screen display signal among the signals switched by the signal switching circuit. two color difference signals R
A demodulator that demodulates -Y and B-Y, a multiplexer that multiplexes the luminance signal sent as the output of the demodulator and two color difference signals, and an analog/multiplexer that converts the output signal of the multiplexer into a digital signal. a digital converter; a serial-to-parallel conversion circuit for converting the output of the analog/digital converter into parallel signals;
a memory for storing the output signal of the parallel conversion circuit; a parallel-to-serial conversion circuit for converting the signal read from the memory into a serial signal; and a first circuit for converting the output signal of the parallel-to-serial conversion circuit into an analog signal. a digital/analog converter, second and third digital/analog converters that convert signals read from the memory into analog signals, and the first, second, and third digital/analog converters. a modulator that modulates the three output signals, a multiplexer that multiplexes the main screen display signal that is one output of the signal switching circuit and the output signal of the modulator, and an address for accessing the memory. A memory address generation circuit that generates a memory address, and a write timing control signal when writing a signal to the above memory,
A magnetic recording and reproducing device comprising: a timing control circuit that generates the signal for displaying the small screen using a horizontal synchronization signal as a reference.