JPH0292175A - Video signal processor - Google Patents

Abstract

PURPOSE:To form a video signal, in which framing is executed for recording by writing regenerative video signal only in an effective picture range into a memory in synchronization with a synchronizing signal in the video signal, reading the written signal in synchronization with the reference synchronizing signal, and adding the reference synchronizing signal. CONSTITUTION:A luminance signal Y and a chroma signal C read from a digital memory 3 are recorded on a recording device 17. At such a time, the read signals are in a phase fixed by the reference synchronizing signal, and the recording is attained by using the signal. That is, the reproduced luminance signal and a color difference signal are written in turn at every line in the digital memory 3, and by reading them according to the referential synchronizing signal, the signals in the fixed phase are taken out. In addition, delay quantities of delay circuits 11, 12 and 13 are ready to prevent reading from surpassing writing, and they are sufficient to be approximately several horizontal periods corresponding to the jitter portion of a reproducing device 1. Thus, the excellent recording is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for transmitting a video signal reproduced from a VTR to another VTR.
The present invention relates to a video signal processing device used when recording in TR.

[Summary of the Invention] The present invention relates to a video signal processing device, which writes a reproduced video signal into a memory device only in an effective screen range in synchronization with a synchronization signal in the signal, and uses this written signal as a reference synchronization signal. By reading out the signal in synchronization with the reference signal and adding this reference synchronization signal, it is possible to form a video signal for recording in which framing has been performed.

[Conventional technology]

When so-called splice recording is performed in a general consumer VTR, recording is performed without taking into consideration the continuity of the phase (framing) of the luminance signal at the splice portion. Therefore, phase discontinuity occurs with probability 2, but
Conventionally, the effects of such phase discontinuities have been ignored, with only a slight skew appearing at the top of the field when a video is played back by a receiver.

[Problem to be Solved by the Invention] However, in recent years, due to improvements in the performance of VTRs and the implementation of so-called editing, a situation has arisen in which splicing is repeated at intervals of several frames. In such a case, if the above-mentioned skew occurs frequently, the influence may spread to other parts and cause a problem.

Furthermore, in some so-called 8mm VTRs, the correspondence between odd or even fields of the luminance signal and a pair of rotating heads is uniquely determined, and in that case, the above-mentioned phase discontinuity causes servo disturbance. Therefore, recording (dubbing) of such signals becomes impossible.

This application was filed in view of these points.

[Means to solve the problem]

In the present invention, a reference vertical synchronization signal from a reference synchronization generation circuit (9) is supplied to a reproducing device (1), a video signal is reproduced in synchronization with the reference vertical synchronization signal, and the reproduced video signal is synchronized. The signal is separated (circuit (7)), and with this separated synchronization signal, only the signal in the effective screen range of the reproduced video signal is written into the memory device (3), and the reference from the reference synchronization generation circuit is written. The synchronization signal is delayed by a predetermined amount (circuit (
11) (12)) The delayed synchronization signal is used to read out the signal of the effective screen range from the memory device, and the read signal of the effective screen range is applied to the signal from the reference synchronization generation circuit. Quantitative and Equivalent Delay (Circuit (16)
)) are applied (switch (15)), and the video signal obtained by adding at least the synchronization signal to the signal of the effective screen range is supplied to the recording device (17). This is a video signal processing device that performs recording.

[For production]

According to this, the signal read from the memory device has a phase determined by the reference synchronization signal, and good recording can be performed using this signal.

[Embodiment] In FIG. 1, (1) is a playback device such as a VTR that is externally synchronized by a vertical synchronization signal (VD),
The reproduced luminance signal (Y) from this reproduction device (1) is digitized by the AD conversion circuit (2) and stored in the digital memory (
3). Further, the chroma signal (C) from the playback device (1) is supplied to the decoder (4) and the color difference signal (R-
Y, B-Y) are decoded, and these signals are arranged alternately at every other sample in the matrix circuit (5) and sent to the AD
The signal is supplied to a conversion circuit (6), and the digitized signal is supplied to a digital memory (3). Furthermore, the luminance signal (Y) from the playback device (1) is sent to the sync separation circuit (7).
The separated vertical and horizontal synchronization signals are supplied to the write address generation circuit (8) of the digital memory.

As a result, the luminance signal (
The signals in the effective screen range of Y) and chroma signal (C) are written into the digital memory (3).

On the other hand, (9) is a reference synchronization generation circuit driven by a crystal oscillator (10), and the vertical synchronization signal (VD) from this generation circuit (9) is supplied to the external synchronization terminal of the playback device (1). At the same time, vertical synchronization signal and horizontal synchronization signal (H
D) is supplied to the read address generation circuit (13) of the digital memory through predetermined delay circuits (11) (12). Then, the read luminance signal is transferred to the DA conversion circuit (14).
), and this analog signal is converted into an analog signal by the switch (1
5) is supplied to one of the fixed contacts.

In addition, a black burst signal (B/
B) is supplied to the other fixed contact of the switch (15) through a delay circuit (16) equivalent to the delay circuits (11) and (12) described above, and this switch (15) receives the valid signal from the address generation circuit (13). The other fixed contact is switched to the other fixed contact during a period when the signal in the memory (3) is not read out by a signal indicating that the screen is out of range. The brightness signal (Y) from this switch (15) is supplied to the recording device (17).

Furthermore, the chroma signal read out from the digital memory (3) is supplied to the DA conversion circuit (18), and this analogized signal is supplied to the matrix circuit (19), where color difference signals are alternately arranged every other sample. (RY, B-
Y) are separated and these signals are fed to the encoder (20). The chroma signal (C) from this encoder (20) is supplied to the recording device (17). Also, the vertical synchronization signal (VD) from the delay circuit (12) is transmitted to the recording device (17).
) is supplied to the external synchronization terminal.

As a result, the luminance signal (Y) and chroma signal (C) read from the digital memory (3) are transferred to the recording device (17).
recorded in

In this way, the signal reproduced by the reproduction device (1) is transmitted to the recording device (
According to the above-mentioned device, the signal read from the memory device has a phase determined by the reference synchronization signal, and this signal is used to perform good recording. be able to.

That is, in the above device, the digital memory (3)
A reproduced luminance signal and a color difference signal are written in order for each horizontal line, and when read out in accordance with a reference synchronization signal, a signal of a determined phase is extracted.

Note that the delay amount of the delay circuits (11), (12), and (16) described above is to prevent the successive output from overtaking the writing, and if it is several horizontal periods corresponding to the jitter of the playback device (1), good.

In addition, in the above-mentioned device, if the phase of the reproduction (write) signal and the phase of the successive signal are opposite, the arrangement of interlaced scanning may be upside down. It is also possible to determine this and shift the succession by one horizontal line in one field.

Furthermore, when the relationship between the phase of the luminance signal and the rotary head is uniquely determined, such as in an 8 mm VTR, the switching pulse for switching the head of the recording device (17) is used to
This signal may be used to reset the phase of the synchronization signal from the generation circuit (9) so that they match.

〔Effect of the invention〕

According to this invention, the signal read from the memory device has a phase determined by the reference synchronization signal, and it has become possible to perform good recording using this signal.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention. (1) is a playback device, (3) is a digital memory, (input is a synchronization separation circuit, (9) is a reference synchronization generation circuit, (11)
(12) (16) is a delay circuit, (15) is a switch,
(17) is a recording device.

Claims (1)

[Claims] A reference vertical synchronization signal from a reference synchronization generation circuit is supplied to a reproducing device, a video signal is reproduced in synchronization with this reference vertical synchronization signal, and a synchronization signal of this reproduced video signal is separated. With the synchronization signal separated from the lever, only the signal of the effective screen range of the reproduced video signal is written into the memory device, and the reference synchronization signal from the reference synchronization generation circuit is delayed by a predetermined amount to generate this delayed synchronization. A signal of the effective screen range is read from the memory device according to the signal, and at least a synchronization signal delayed by an amount equal to the predetermined amount from the reference synchronization generation circuit is added to the read signal of the effective screen range. A video signal processing device, wherein the video signal obtained by adding at least the synchronization signal to the signal of the effective screen range is supplied to a recording device to perform recording.