JP2001352526A - Scanning line conversion circuit and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scanning line conversion circuit that simplifies the circuit configuration to reduce the circuit cost and to provide a receiver employing the scanning line conversion circuit. SOLUTION: A coefficient device 81 multiplies a video signal i1 of a 1st line by a filter coefficient k1, a selection circuit 83 stores the result of the multiplication to a line memory 84, the coefficient device 81 multiplies a video signal i2 of a 2nd line by a filter coefficient k2, and an adder 82 adds the output of the coefficient device 81 to the output of the line memory 84, the selection circuit 83 stores the result of the sum to the line memory 84, and the coefficient device 81 multiplies a video signal i3 of a 3rd line by a filter coefficient k3 and the adder 82 adds the output of the coefficient device 81 to the output of the line memory 84, and an output switch 86 outputs the output k1.i1+k2.i2+k3.i3 of the adder 82 as a 1st line video signal o1 after the conversion is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scanning line conversion circuit for converting the number of scanning lines of a video signal and a receiving apparatus using the scanning line conversion circuit.

[0002]

2. Description of the Related Art In recent years, digitalization of television broadcasting has been promoted, and various video formats such as 1080i and 480i have been adopted in digital broadcasting of BS (broadcast satellite). ) The number of scanning lines of the 1080i video signal used for broadcasting is 540. On the other hand, the number of scanning lines of a video signal based on a broadcasting system such as NTSC or PAL used for conventional analog broadcasting is 263 or 313.

[0003] As described above, video signals having various numbers of scanning lines are used in a mixed manner. For example, an image based on video signals having different numbers of scanning lines is displayed on a television compatible with a conventional broadcasting system such as NTSC or PAL. To do so, it is necessary to convert the number of scanning lines into a number conforming to a broadcasting system such as NTSC or PAL, and the following scanning line conversion circuit is used.

FIG. 11 is a block diagram showing a configuration of a conventional scanning line conversion circuit. The scanning line conversion circuit shown in FIG. 11 includes line memories 101 to 103, selection circuits 104 to 1
06, coefficient units 107 to 109, and an adder 110.

[0005] The video signals HT before scanning line conversion are sequentially input to the line memories 101 to 103 for each scanning line. For example, the video signals i1 of the first to third lines before scanning line conversion are input.
To i3, respectively, and each of the line memories 101 to 1
03 denotes the stored video signals i1 to i of the first to third lines.
3 is output to the selection circuits 104 to 106. Selection circuit 10
4 to 106 select the outputs of the line memories 101 to 103 and output the video signals i1 to i3 of the first to third lines to the coefficient units 107 to 109.

[0006] The coefficient unit 107 outputs the video signal i of the first line.
1 is multiplied by the filter coefficient k1 and output to the adder 110. The coefficient unit 108 multiplies the video signal i2 of the second line by the filter coefficient k2 and outputs the result to the adder 110. The coefficient unit 109 multiplies the video signal i3 of the third line by the filter coefficient k2 and outputs the result to the adder 110. Adder 110
Is the sum of the outputs of the coefficient units 107 to 109, and as a converted video signal VT, k1 · i1 + k2 · i2 + k3 ·
i3 is output.

In this way, the filter operation of three taps is performed, and the video signal VT of one scanning line is output from the video signal HT of three scanning lines of the first to third lines. By repeating such processing, the number of scanning lines of the video signal HT is reduced to three.
A video signal VT having one-half scanning line is created.

[0008]

As described above, in the conventional scanning line conversion circuit, when the number of scanning lines is reduced to 1 / n, the video signals of n scanning lines before conversion are converted into n pieces of video signals. The output of the n line memories is selected by the n selection circuits, and the outputs of the n line memories are multiplied by the filter coefficients by the n coefficient units. This necessitates a device, which complicates the circuit configuration and increases the circuit cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a scanning line conversion circuit capable of simplifying a circuit configuration and reducing a circuit cost, and a receiving device using the scanning line conversion circuit.

[0010]

Means for Solving the Problems (1) First invention A scanning line conversion circuit according to a first invention is a scanning line conversion circuit for converting the number of scanning lines of a video signal. Multiplication means for multiplying the output of the multiplication means for each scanning line, an addition means for adding the output of the line memory and the output of the multiplication means,
Selecting means for selecting one of the output of the multiplying means and the output of the adding means and outputting it to the line memory; controlling the value of the filter coefficient multiplied by the multiplying means and controlling the selecting operation of the selecting means Control means for performing the operation.

In the scanning line conversion circuit according to the present invention,
The output of the multiplying means obtained by multiplying the input video signal by the filter coefficient can be selected by the selecting means and stored in the line memory. Therefore, the video signal i1 of the first line is multiplied by the filter coefficient k1 to store k1 in the line memory.
I1 can be stored.

Further, the control means can control the value of the filter coefficient multiplied by the multiplying means,
The output of the line memory and the output of the multiplication means can be added by the addition means, and the output of the addition means can be selected by the selection means and stored in the line memory. Therefore, the output k2 · i2 of the multiplication means obtained by multiplying the video signal i2 of the second line by another filter coefficient k2 and the output k of the line memory
Add 1 · i1 to the line memory and add k1 · i1 + k2
I2 can be stored.

Therefore, by repeating the above processing, the line memory is stored in the line memory as k1 · i1 + k2 · i2 +.
(N-1) .i (n-1) is stored, and finally the output kn.in of the multiplication means obtained by multiplying the video signal in of the n-th line by another filter coefficient kn and the output k1.multidot.
.. + k (n−1) · i (n−1) are added to obtain k1 · i1 + k2 · i2 +... + kn · in.

As described above, the video signal of n scanning lines can be converted into the video signal of one scanning line by using one multiplying means, one line memory and one selecting means. A scanning line conversion circuit which can simplify a circuit configuration and reduce circuit cost can be realized.

(2) Second invention In a scanning line conversion circuit according to a second invention, in the configuration of the scanning line conversion circuit according to the first invention, the multiplying means includes a first filter for converting the input video signal into a first filter. The control means includes first multiplying means for multiplying a coefficient and second multiplying means for multiplying an input video signal by a second filter coefficient, and the control means is multiplied by the first and second multiplying means. The values of the first and second filter coefficients are controlled respectively, the adding means adds the output of the line memory and the output of the first multiplying means, and the selecting means selects the output of the second multiplying means and the adding means. Is selected and output to the line memory.

In this case, the output of the second multiplying means obtained by multiplying the input video signal by the second filter coefficient can be selected by the selecting means and stored in the line memory. Therefore, the video signal i1 of the first line can be multiplied by the filter coefficient k1 by the second multiplication means, and k1 · i1 can be stored in the line memory.

The value of the first filter coefficient multiplied by the first multiplying means can be controlled by the control means, and the output of the line memory and the input video signal can be controlled by the adding means by the first filter. The output of the first multiplication means multiplied by the coefficient is added, and the output of the addition means can be selected by the selection means and stored in the line memory. Therefore, the output k2 · i of the first multiplying means that multiplies the video signal i2 of the second line by another filter coefficient k2.
2 and the output k1 · i1 of the line memory can be added to store k1 · i1 + k2 · i2 in the line memory. Therefore, by repeating the above processing, k1 · i1 + k2 · i2 +... + Kn · in is stored in the line memory.
Can be stored.

The control means can control the values of the first and second filter coefficients multiplied by the first and second multiplication means, and the addition means outputs the image of the line memory and the input image. The output of the first multiplying means obtained by multiplying the signal by the first filter coefficient is added, and at the same time, the output of the second multiplying means obtained by multiplying the input video signal by the second filter coefficient is selected by the selecting means. And store it in the line memory.

Therefore, the video signal i of the (n + 1) th line
The output k (n + 1) .i (n + 1) of the first multiplication means obtained by multiplying (n + 1) by another filter coefficient k (n + 1) and the output k1 · i1 + k2 · i2 +...
and k1 · i1 + k2 · i2 +... + k (n
+1) .i (n + 1), and the output k1.i (n +) of the second multiplication means in which the video signal i (n + 1) of the (n + 1) th line is multiplied by another filter coefficient k1.
1) can be stored in the line memory.

As a result, the video signal i of the (n + 1) th line
(N + 1) can be separately multiplied by different filter coefficients k (n + 1) and k1, and the video signal i (n + 1) of the (n + 1) th line is used for the conversion processing of the video signals of the two scanning lines after the conversion. Can be. Therefore, the number of scanning lines is n
In order to reduce the number of taps, increase the number of filter taps,
A video signal of one scanning line can be created from a video signal of n + 1 scanning lines.

As described above, by using two multiplying means, one line memory and one selecting means, the number of scanning lines can be reduced to n.
In the case of conversion to one-half, the number of taps is increased and a video signal of one scanning line can be created from a video signal of n + 1 scanning lines, so that the circuit configuration is simplified and the circuit cost is reduced. And a higher definition video signal can be created.

(3) Third invention In a scanning line conversion circuit according to a third invention, in the configuration of the scanning line conversion circuit according to the first invention, the control means controls the filter coefficient to be equal to the first filter coefficient. The multiplication means is controlled so as to switch to the filter coefficient of 2 in a time-division manner.

In this case, the filter coefficient of the multiplication means is set to the first
And the second filter coefficient can be switched in a time-division manner, so that the video signal i of the (n + 1) th line
(N + 1) can be multiplied by time division with different filter coefficients k (n + 1) and k1. Therefore, similarly to the second invention, the video signal i (n + 1) of the (n + 1) th line can be used for the conversion processing of the video signal of the two scanning lines after the conversion, and the number of scanning lines is reduced to 1 / n. In this case, the number of taps of the filter is increased, and a video signal of one scanning line can be created from the video signal of n + 1 scanning lines.

Therefore, the number of scanning lines can be reduced to n by using one multiplying means, one line memory and one selecting means.
In the case of conversion to one-half, the number of taps is increased and a video signal of one scanning line can be created from a video signal of n + 1 scanning lines, so that the circuit configuration is simplified and the circuit cost is further reduced. In addition to the reduction, it is possible to create a higher definition video signal.

(4) Fourth Invention A receiving device according to a fourth invention is a receiving device for receiving a first video signal having a first number of scanning lines, and a first video received by the receiving device. The signal is compressed in the horizontal direction, and is also compressed in the vertical direction by the scanning line conversion circuit according to any one of the first to third aspects of the present invention, so that the first video signal has a second scanning line number smaller than the first scanning line number. Compression means for converting the second video signal into a number of second video signals.

In the receiving apparatus according to the present invention, the received first video signal having the first number of scanning lines is compressed in the horizontal and vertical directions, and the second scanning having less than the first number of scanning lines is performed. It can be converted to a second video signal having the number of lines. Therefore, it is possible to convert a high-definition video signal from an HD broadcast or the like into a video signal according to a conventional broadcasting system such as NTSC or PAL, and to convert the signal from a conventional NTSC or PAL.
It is possible to display an image by HD broadcasting or the like using a display device or the like compatible with a broadcasting system such as AL.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a vertical processing circuit used in a digital broadcast receiving apparatus will be described as an example of a scanning line conversion circuit according to the present invention. Note that the scan line conversion circuit to which the present invention is applied is not particularly limited to this example, and any scan line conversion circuit that reduces the number of scan lines of a video signal can be similarly applied to other scan line conversion circuits. Can be similarly used for the receiving device and the like.

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving apparatus using a vertical processing circuit according to one embodiment of the present invention.

The digital broadcast receiving apparatus shown in FIG. 1 includes a tuner section 2, an AV (audio / video) decoder 3, an image compression circuit 4, and AV output circuits 5 and 6. The image compression circuit 4 includes a horizontal processing circuit 7 and a vertical processing circuit 8.

The tuner 2 is a digital broadcast, for example,
A BS (Satellite Broadcasting) receives a BS-IF signal output from an antenna 1 such as a parabolic antenna for receiving a BS radio wave by digital broadcasting, selects a desired transmission channel from the BS-IF signal, and performs a predetermined demodulation process and the like. Then, the transport stream TS is output to the AV decoder 3.

The AV decoder 3 decodes the input transport stream TS and outputs a digital video signal V
S is output to the image compression circuit 4 and the AV output circuit 5.

When the input digital video signal VS is a high-definition video signal by HD broadcasting or the like, the AV output circuit 5 converts the high-definition digital video signal VS by HD broadcasting or the like to the broadcasting system as a main video output. The main image signal HD is converted into a main video signal HD that can be displayed on a display device such as a television and output to a display device or the like (not shown) corresponding to a broadcasting system such as HD broadcasting.

When the input digital video signal VS is a high-definition video signal such as an HD broadcast, the image compression circuit 4 compresses the digital video signal VS in the horizontal direction and the vertical direction to use a conventional video signal such as NTSC or PAL. The compressed digital video signal VT having the number of horizontal pixels and the number of scanning lines suitable for the broadcasting system is output to the AV output circuit 6.

The AV output circuit 6 converts the compressed digital video signal VT into a sub video signal SD which can be displayed on a display device such as a television compatible with a conventional broadcasting system such as NTSC or PAL as a sub video output. NTSC or PA
L or the like (not shown) corresponding to a conventional broadcasting system such as L.

The horizontal processing circuit 7 includes a high-definition main video output conforming to a broadcasting system such as HD broadcasting and NTSC or PAL.
Digital video signal VS is compressed in the horizontal direction in accordance with the ratio of the number of pixels in one scanning line to the sub-resolution output of a normal resolution conforming to the conventional broadcasting system such as The signal HT is output to the vertical processing circuit 8.

The vertical processing circuit 8 compresses the digital video signal HT compressed in the horizontal direction in the vertical direction according to the ratio of the number of scanning lines between the main video output and the sub video output, that is, the scanning for the main video output. The digital video signal HT having the number of lines is converted into a digital video signal VT having the number of scanning lines for outputting a sub-video and output to the AV output circuit 6.

With the above-described configuration, the digital broadcast receiving apparatus shown in FIG.
And a sub-video output based on a conventional broadcasting system such as C or PAL.
It can be converted into a video signal according to a conventional broadcasting system such as C or PAL, and a video according to HD broadcasting or the like can be displayed using a display device or the like compatible with a conventional broadcasting system such as NTSC or PAL.

In this embodiment, the tuner unit 2 and A
The V decoder 3 corresponds to a receiving unit, the image compression circuit 4 corresponds to a compression unit, and the vertical processing circuit 8 corresponds to a scanning line conversion circuit.

Next, the vertical processing circuit 8 shown in FIG. 1 will be described in detail. FIG. 2 is a block diagram showing a configuration of the vertical processing circuit 8 shown in FIG.

The vertical processing circuit shown in FIG.
An adder 82, a selection circuit 83, a line memory 84, a control circuit 85, and an output switch 86 are included.

The coefficient unit 81 has a filter coefficient k set by the control circuit 85 for the input digital video signal HT.
, And outputs the result of the multiplication to the adder 82 and the selection circuit 83. The adder 82 adds the output of the coefficient unit 81 and the output of the line memory 84, and outputs the addition result to the selection circuit 83 and the output switch 86. The selection operation of the selection circuit 83 is controlled by the control circuit 85,
And the output of the adder 82 are output to the line memory 84. The output switch 86 is connected to the control circuit 8
5 controls the output operation, and outputs the output from the adder 82 as a digital video signal VT at a predetermined timing. The control circuit 85 switches the filter coefficient k of the coefficient unit 81, the selection operation of the selection circuit 83, and the output operation of the output switch 86 for each scanning line of the input digital video signal HT.

In this embodiment, the coefficient unit 81 corresponds to a multiplying unit, the adder 82 corresponds to an adding unit, and the selecting circuit 8
3 corresponds to the selection means, and the control circuit 85 corresponds to the control means.

FIG. 3 is a schematic diagram showing an example of a scanning line conversion process executed by the vertical processing circuit shown in FIG. The scanning line conversion process shown in FIG. 3 is a 1/3 compression process for compressing the number of scanning lines to one third, and converts a video signal of one scanning line from a video signal of three scanning lines that are input. Create

As shown in FIG. 3, in the vertical processing circuit shown in FIG. 2, the filter coefficient k1 is applied to the video signal i1 of the first line.
, A value obtained by multiplying the video signal i2 of the second line by the filter coefficient k2, and a value obtained by multiplying the video signal i3 of the third line by the filter coefficient k3 are added. It is output as a video signal o1. Similarly,
The video signal o2 of the second line after conversion is created from the video signals i4 to i6 of the fourth to sixth lines, and the video signal o3 of the third line after conversion from the video signals i7 to i9 of the seventh to ninth lines. Is created. That is, the input video signals of the three scanning lines are multiplied by predetermined filter coefficients k1 to k3 to perform a filtering process, thereby producing an output video signal of one scanning line, and the number of scanning lines is reduced to one third. Reduced.

FIG. 4 is a block diagram for explaining a specific operation of the vertical processing circuit shown in FIG. 2 in the scanning line conversion processing shown in FIG.

First, as shown in FIG. 4A, when the video signal i1 of the first line is input to the coefficient unit 81, the control circuit 85 determines the filter coefficient of the coefficient unit 81 as the processing of the start line. Switching to k1, the coefficient unit 81 multiplies the video signal i1 of the first line by the filter coefficient k1. At this time, the selection circuit 83 is controlled by the control circuit 85 to select the coefficient unit 81, and the output of the coefficient unit 81 is temporarily stored in the line memory 84. That is, the line memory 8
4 stores k1 · i1. In this processing, the output switch 86 is controlled by the control circuit 85 to add the adder 8.
2 is set not to be output, and the output of the output switch 86 is turned off.

Next, as shown in FIG. 4 (b), when the video signal i2 of the second line is input to the coefficient unit 81 as the processing of the continuous line, the control circuit 85 sets the filter coefficient of the coefficient unit 81. Is switched to k2, the coefficient unit 81 multiplies the video signal i2 of the second line by the filter coefficient k2, and
Output to 2. Here, by the processing shown in FIG. 4A, k1 · i1 is stored in the line memory 84, and the adder 82 outputs k2 · i output from the coefficient unit 81.
2 and k1 · i1 output from the line memory 84 are added and output to the line memory 84. The line memory 84 temporarily stores k1 · i1 + k2 · i2. In this process, the output switch 86 is set by the control circuit 85 so as not to output the output of the adder 82, and the output of the output switch 86 is turned off.

FIG. 5 is a timing chart for explaining the operation of the coefficient unit 81 and the line memory 84 in the processing of the continuation line shown in FIG.

As shown in FIG. 5, each pixel p constituting one scanning line as input data is synchronized with a predetermined clock.
.. Are sequentially input to the coefficient unit 81 every two clock cycles, and delayed by one clock, the multiplied values k · p0 to k · p
Are sequentially output from the coefficient unit 81. At this time, the data m0 to m2,... Are sequentially read from the line memory 84 in one clock period in synchronization with the output of the coefficient unit 81, and the output k · p0 + m0 of the adder 82 is read in the remaining one clock period.
... K · p2 + m2,... Are sequentially written to the line memory 84. As described above, the data in the line memory 84 is read in the first half of the output period of the coefficient unit 81, and the data is written in the line memory 84 in the second half. Then, the processing of the continuation line shown in FIG.

Finally, as the processing of the end line, as shown in FIG. 4C, when the video signal i3 of the third line is input to the coefficient unit 81, the control circuit 85 sets the filter coefficient of the coefficient unit 81. Is switched to k3, the coefficient unit 81 multiplies the video signal i3 of the third line by the filter coefficient k3, and
Output to 2. Here, by the processing shown in FIG. 4B, k1 · i1 + k2 · i2 is stored in the line memory 84, and the adder 82 outputs k3 · i3 output from the coefficient unit 81 and output from the line memory. K1 · i1
+ K2 · i2. At this time, the output switch 8
6 is controlled by the control circuit 85 and outputs the output k1 · i1 + k2 · i2 + k3 · i3 of the adder 82 as the converted first-line video signal o1.

By the above processing, a 3-tap filter processing is performed, a video signal of one scanning line is created from a video signal of three scanning lines, and the above processing is repeated. Is performed.

In the above description, the case where a video signal of one scanning line is created from a video signal of three scanning lines has been described. However, the processing shown in FIG. Thus, a video signal of one scanning line can be created from video signals of an arbitrary number of scanning lines. Thus, for example, 1080i (540 scanning lines and interlaced), 720p (720 scanning lines and progressive), 480p (480 scanning lines and progressive) and 480i (240 scanning lines and interlaced) Various images can be converted into 480i images, or letterboxes can be arranged in the upper and lower parts of the display screen to display an image having 180 scanning lines in the middle part.

As described above, in this embodiment, one coefficient unit 81, one line memory 84, one selection circuit 83 and the like are used to convert n scan line video signals into one scan line. Therefore, a scanning line conversion circuit that can simplify the circuit configuration and reduce the circuit cost can be realized.

Next, another embodiment of the vertical processing circuit 8 shown in FIG. 1 will be described. FIG. 6 is a block diagram showing a configuration of another embodiment of the vertical processing circuit 8 shown in FIG.

The difference between the vertical processing circuit shown in FIG. 6 and the vertical processing circuit shown in FIG. 2 is that a coefficient unit 87 is added, and a selection circuit 83 selects one of the output of the coefficient unit 87 and the output of the adder 82. And the control circuit 85 is changed to a control circuit 85a for controlling the coefficient units 81 and 87, the selection circuit 83a and the output switch 86, and the other points are the vertical ones shown in FIG. The same parts as those of the processing circuit are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 6, the coefficient unit 87 receives the digital video signal HT which has been subjected to the horizontal compression processing by the horizontal processing circuit 7 and converts the filter coefficient k 'set by the control circuit 85a into a digital signal. The video signal HT is multiplied, and the multiplication result is output to the selection circuit 83a. Selection circuit 8
3a, the selection operation of which is controlled by the control circuit 85a, and outputs one of the output of the coefficient unit 87 and the output of the adder 82 to the line memory 84. Control circuit 85a
Switches the filter coefficients k and k ′ of the coefficient units 81 and 87, the selection operation of the selection circuit 83a, and the output operation of the output switch 86 for each scanning line of the input digital video signal HT.

In this embodiment, the coefficient unit 81 corresponds to the first multiplying unit, the coefficient unit 87 corresponds to the second multiplying unit, the adder 82 corresponds to the adding unit, and the selecting circuit 83a selects The control circuit 85a corresponds to control means.

FIG. 7 is a schematic diagram showing an example of a scanning line conversion process executed by the vertical processing circuit shown in FIG. The scanning line conversion process shown in FIG. 7 is a 1/3 compression process for compressing the number of scanning lines to one third, and converts a video signal of one scanning line from an input video signal of four scanning lines. Create

As shown in FIG. 7, in the vertical processing circuit shown in FIG. 6, the filter coefficient k1 is applied to the video signal i1 of the first line.
, A value obtained by multiplying the video signal i2 of the second line by the filter coefficient k2, a value obtained by multiplying the video signal i3 of the third line by the filter coefficient k3, and a filter coefficient obtained by multiplying the video signal i4 of the fourth line by the filter coefficient A value multiplied by k4 is added, and the result is output as the converted first-line video signal o1. Similarly, the second line video signal o2 after conversion is created from the fourth to seventh line video signals i4 to i7, and the third line after conversion from the seventh to tenth line video signals i7 to i10. Is generated.

As described above, three of the input video signals are
Four scans are performed, as well as an end line used for converting a video signal to be output in which a video signal of m + 1 lines (m is a positive number) is output, and a start line used for conversion of a video signal to be output next. The input video signal of the line is multiplied by a predetermined filter coefficient k1 to k4 to perform a filtering process, an output video signal of one scanning line is created, and the number of scanning lines is reduced to one third.

FIG. 8 is a block diagram for explaining a specific operation of the vertical processing circuit shown in FIG. 6 in the scanning line conversion processing shown in FIG.

First, as the processing of the start line, when the video signal i1 of the first line is input to the coefficient unit 87 as shown in FIG. 8A, the control circuit 85a changes the filter coefficient of the coefficient unit 87. Switching to k1, the coefficient unit 87 multiplies the video signal i1 of the first line by the filter coefficient k7. At this time, the selection circuit 83a controls the coefficient unit 8 by the control circuit 85a.
The output of the coefficient unit 87 is temporarily stored in the line memory 84. That is, k1 · i1 is stored in the line memory 84. In this processing, the output switch 86 is set by the control circuit 85a so as not to output the output of the adder 82, and the output of the output switch 86 is turned off.

Next, as the processing of the continuation line, as shown in FIG. 8B, when the video signal i2 of the second line is input to the coefficient unit 81, the control circuit 85a makes the filter coefficient of the coefficient unit 81 Is switched to k2, and the coefficient unit 81 multiplies the video signal i2 of the second line by the filter coefficient k2 and outputs the result to the adder 82. Here, by the processing shown in FIG. 8A, k1 · i1 is stored in the line memory 84, and the adder 82 outputs k2 · i output from the coefficient unit 81.
2 and k1 · i1 output from the line memory are added and output to the line memory 84.
• Store i1 + k2 · i2 once. In this processing, the output switch 86 is set by the control circuit 85a so as not to output the output of the adder 82, and the output of the output switch 86 is turned off.

Next, the above-described processing of the continuation line is performed on the video signal i3 of the third line, and the video signal i3 of the third line is multiplied by the filter coefficient k3 by the coefficient unit 81. In the memory 84, k1 · i1 + k2 ·
i2 + k3 · i3 is stored.

Next, as the processing of the end line and the start line, when the video signal i4 of the fourth line is input to the coefficient units 81 and 87, as shown in FIG. The filter coefficient of the multiplier 81 is switched to k4, and the filter coefficient of the multiplier 87 is switched to k1. The multiplier 81 multiplies the video signal i4 of the fourth line by the filter coefficient k4 and outputs the result to the adder 82. 87 multiplies the video signal i4 of the fourth line by the filter coefficient k1 and outputs the result to the selection circuit 83a.

Here, by the processing shown in FIG.
The line memory 84 has k1 · i1 + k2 · i2 + k3 ·
i3 is stored, and the adder 82 adds k4 · i4 output from the coefficient unit 81 and k1 · i1 + k2 · i2 + k3 · i3 output from the line memory 84.
At this time, the output switch 86 is controlled by the control circuit 85a, and the output k1 · i1 + k2 · i2 + of the adder 82 is output.
k3 · i3 + k4 · i4 is output as the converted first-line video signal o1.

On the other hand, the selection circuit 83a is controlled by the control circuit 85a so as to select the coefficient unit 87 side.
7 is temporarily stored in the line memory 84. That is, k1 · i4 is stored in the line memory 84.

Next, the video signals i of the fifth and sixth lines
5, the processing shown in FIG. 8B is executed for i6,
The processing shown in FIG. 8C is performed on the video signal i7 on the seventh line, and the video signal i4 on the fourth to seventh lines is executed.
To i7, a video signal o2 of the converted second line is created.

The above process is repeated, and after the process shown in FIG. 8B is performed on the video signal ix-1 of the line immediately before the last line at the lower end of the display screen, finally, As the processing of the last line, when the video signal ix of the last line is input to the coefficient unit 81 as shown in FIG.
The control circuit 85a switches the filter coefficient of the coefficient unit 81 to k4, and the coefficient unit 81 multiplies the video signal ix of the last line by the filter coefficient k4 and outputs the result to the adder. Here, the processing shown in FIG.
Has k1.ix-3 + k2.ix-2 + k3.ix-1
Are stored in the adder 82. The adder 82 outputs k4 · ix output from the coefficient unit 81 and k1 · x output from the line memory.
ix−3 + k2 · ix−2 + k3 · ix−1. At this time, the output switch 86 is controlled by the control circuit 85, and the output k1 · ix−3 + k2 ·
ix−2 + k3 · ix−1 + k4 · ix is output as the video signal oy of the final line after the conversion.

By the above processing, a 4-tap filter processing is performed, a video signal of one scanning line is created from a video signal of four scanning lines, and the above processing is repeated. Is performed. In the above description, a case has been described in which a video signal of one scanning line is created from a video signal of four scanning lines. However, by continuing the processing shown in FIG. The video signal of one scanning line can be created from the video signals of the number of scanning lines.

As described above, in this embodiment, when performing 1 / n compression processing using two coefficient units 81 and 87, one line memory 84, and one selection circuit 83a, n + 1 Can be converted into the video signal of one scanning line, so that it is possible to realize a scanning line conversion circuit that can simplify the circuit configuration and reduce the circuit cost.

In the present embodiment, when performing 1 / n compression processing, the video signal of one scanning line is created from the video signal of n + 1 scanning lines. Can be increased. Therefore, the filter characteristic slope at the filter cutoff frequency can be made steeper, and the filter characteristic can be further improved, so that a higher definition video signal can be converted. Can be determined.
For example, when displaying a black-and-white stripe pattern, the limit of discrimination as a stripe can be narrowed, and a higher definition image can be obtained.

Next, still another embodiment of the vertical processing circuit 8 shown in FIG. 1 will be described. FIG. 9 is a block diagram showing a configuration of still another embodiment of the vertical processing circuit 8 shown in FIG.

The difference between the vertical processing circuit shown in FIG. 9 and the vertical processing circuit shown in FIG. 2 is that a coefficient setting circuit 88 for switching the filter coefficient of the coefficient unit 81a to time division under the control of the control circuit 85b is added. Figure 2
Are the same as those of the vertical processing circuit shown in FIG.

As shown in FIG. 9, the coefficient setting circuit 88
Controlled by the control circuit 85b, the filter coefficient of the coefficient unit 81a is switched to a first filter coefficient k and a second filter coefficient k 'in a time-division manner.

In this embodiment, the coefficient unit 81a corresponds to a multiplying unit, the adder 82 corresponds to an adding unit, the selecting circuit 83 corresponds to a selecting unit, and the control circuit 85b and the coefficient setting circuit 88 correspond to the controlling unit. Is equivalent to

The vertical processing circuit shown in FIG. 9 can also execute the scanning line conversion processing shown in FIG. 7, and specifically operates as follows.

First, the control circuit 85b sets the coefficient setting circuit 8
8, the coefficient setting circuit 88 switches the filter coefficient of the coefficient unit 81a to the first filter coefficient k, and performs the same processing as the start line processing and the continuation line processing shown in FIGS. 4A and 4B. The processing is performed on the video signals i1 to i3 of the first to third lines, respectively, and the line memory 8
4 temporarily stores k1 · i1 + k2 · i2 + k3 · i3.

Next, the control circuit 85b controls the coefficient setting circuit 8
8 and the coefficient setting circuit 88 switches the filter coefficient of the coefficient unit 81a to the first filter coefficient k and the second filter coefficient k ′ in a time division manner, and outputs the video signal i4 of the fourth line.
On the other hand, the processing substantially the same as the processing of the end line and the start line shown in FIG. 8C is performed as follows.

First, as in the processing of the end line and start line shown in FIG.
When 4 is input to the coefficient unit 81a, the control circuit 85b switches the filter coefficient of the coefficient unit 81a to the first filter coefficient k4, and the coefficient unit 81a applies the first filter coefficient k4 to the video signal i4 of the fourth line. The result is multiplied and output to the adder 82. At this time, by the processing shown in FIG. 4B, k1 · i1 + k2 · i2 + k3 · i3 is stored in the line memory 84, and the adder 82 outputs k4 · i4 output from the coefficient unit 81a and the line memory K1 output from
i1 + k2 · i2 + k3 · i3 are added. At this time, the output switch 86 is controlled by the control circuit 85b, and the output k1 · i1 + k2 · i2 + k3 ·
Video signal o1 of the first line after converting i3 + k4 · i4
Output as

After switching the filter coefficient of the coefficient unit 81a to the first filter coefficient k4, the control circuit 85b further switches to the second filter coefficient k1.
a is a second filter coefficient k for the video signal i4 of the fourth line.
The value is multiplied by 1 and output to the selection circuit 83. The selection circuit 83 is controlled by the control circuit 85b to select the coefficient unit 81a, and the output of the coefficient unit 81a is temporarily stored in the line memory 84. That is, k1 is stored in the line memory 84.
I4 is stored.

FIG. 10 is a timing chart for explaining the operation of the coefficient unit 81a, the line memory 84, and the output switch 86 in the processing of the end line and the start line shown in FIG. 8C.

As shown in FIG. 10, pixels p0-p2,... Constituting the video signal i4 of the fourth line as input data are sequentially input to the coefficient unit 81a every two clock cycles in synchronization with a predetermined clock. You. At this time, the coefficient unit 81a
Are switched in time division into a first filter coefficient k and a second filter coefficient k ′ in synchronization with a clock. Therefore, the multiplied value k · p is delayed by one clock.
0, k'.p0, k.p1, k'.p1, k.p1,
k ′ · p2,.
Output from

At this time, data m0 to m2,... Are sequentially read from the line memory 84 in one clock period in synchronization with the multiplied output of the first filter coefficient k of the coefficient unit 81a.
Multiplied output k 'of second filter coefficient k' of coefficient unit 81a
.. P0, k'.p1, k'.p2,... Are selected by the selection circuit 83, and are sequentially written to the line memory 84 in the remaining one clock period. On the other hand, the multiplied outputs k · p0, k · p1, k · p of the first filter coefficient k of the coefficient unit 81a
2,... And read data m0 to m of the line memory 84
Are sequentially added by the adder 82, and the adder 82
Are output sequentially from the output switch 86 every two clock cycles.

As described above, switching between the first filter coefficient k and the second filter coefficient k 'of the coefficient unit 81a, reading and writing of data in the line memory 84, and the like are performed at appropriate timing. The processing of the end line and the start line shown in (c) is substantially executed.

Next, the control circuit 85b controls the coefficient setting circuit 8
8 and the coefficient setting circuit 88 switches the filter coefficient of the coefficient unit 81a to the first filter coefficient k, and shows the video signals i5 and i6 of the fifth and sixth lines as shown in FIG. The processing is executed.

Next, the control circuit 85b controls the coefficient setting circuit 8
8 and the coefficient setting circuit 88 switches the filter coefficient of the coefficient unit 81a to the first filter coefficient k and the second filter coefficient k ′ in a time-division manner, and outputs the video signal i7 of the seventh line.
Then, the processing shown in FIG. 8C is executed to generate the video signal o2 of the second line after the conversion from the video signals i4 to i7 of the fourth to seventh lines.

The above processing is repeated, and the video signal ix-1 of the line immediately before the last line is compared with the video signal ix-1 of FIG.
Are performed, the control circuit 85b controls the coefficient setting circuit 88, and the coefficient setting circuit 88
Is switched to the first filter coefficient k, and the processing of the last line shown in FIG. 8D is executed.

As described above, in this embodiment, when 1 / n compression processing is performed using one coefficient unit 81a, one line memory 84, one selection circuit 83, etc.
Since the video signal of n + 1 scanning lines can be converted into the video signal of one scanning line, the same effect as the vertical processing circuit shown in FIG. 6 can be obtained, and the circuit configuration can be further simplified. A scanning line conversion circuit that can further reduce circuit cost can be realized.

[0090]

According to the present invention, a video signal of n scanning lines is converted into a video signal of one scanning line by using one multiplication means, one line memory and one selection means. Therefore, it is possible to realize a scanning line conversion circuit that can simplify the circuit configuration and reduce the circuit cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving apparatus using a vertical processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a vertical processing circuit shown in FIG. 1;

FIG. 3 is a schematic diagram illustrating an example of a scanning line conversion process performed by the vertical processing circuit illustrated in FIG. 2;

FIG. 4 is a block diagram for explaining a specific operation of the vertical processing circuit shown in FIG. 2 in the scanning line conversion processing shown in FIG. 3;

FIG. 5 is a timing chart for explaining operations of a coefficient unit and a line memory in the processing of the continuation line shown in FIG. 4;

FIG. 6 is a block diagram showing a configuration of another embodiment of the vertical processing circuit shown in FIG. 1;

FIG. 7 is a schematic diagram illustrating an example of a scanning line conversion process performed by the vertical processing circuit illustrated in FIG. 6;

8 is a block diagram for explaining a specific operation of the vertical processing circuit shown in FIG. 6 in the scanning line conversion processing shown in FIG. 7;

FIG. 9 is a block diagram showing a configuration of still another embodiment of the vertical processing circuit shown in FIG. 1;

10 is a timing chart for explaining operations of a coefficient unit, a line memory, and an output switch in processing of an end line and a start line shown in FIG. 8;

FIG. 11 is a block diagram showing a configuration of a conventional scanning line conversion circuit.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 tuner section 3 AV decoder 4 image compression circuit 5, 6 AV output circuit 7 horizontal processing circuit 8 vertical processing circuit 81, 81a, 87 coefficient unit 82 adder 83, 83a selection circuit 84 line memory 85, 85a, 85b control Circuit 86 Output switch

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5C025 BA01 BA11 BA18 BA27 DA01 DA04 5C063 AA01 AA06 AA20 AB03 AC01 BA03 BA06 BA09 BA14 CA01 CA05 CA38

Claims (4)

[Claims] 1. A scanning line conversion circuit for converting the number of scanning lines of a video signal, comprising: multiplication means for multiplying an input video signal by a filter coefficient; and a line for storing an output of the multiplication means for each scanning line. A memory; an adding means for adding the output of the line memory to the output of the multiplying means; selecting one of the output of the multiplying means and the output of the adding means to output to the line memory And a control means for controlling a value of a filter coefficient multiplied by the multiplying means and controlling a selecting operation of the selecting means. 2. The multiplication means includes: first multiplication means for multiplying an input video signal by a first filter coefficient; and second multiplication means for multiplying an input video signal by a second filter coefficient. The control means controls values of first and second filter coefficients to be multiplied by the first and second multiplication means, respectively, and the addition means includes an output of the line memory and the second And an output of the multiplication means of the first multiplication means, and the selection means selects one of the output of the second multiplication means and the output of the addition means and outputs the selected output to the line memory. The scanning line conversion circuit according to claim 1. 3. The scanning apparatus according to claim 1, wherein said control means controls said multiplying means so as to switch said filter coefficient between a first filter coefficient and a second filter coefficient in a time division manner. Line conversion circuit. 4. A receiving means for receiving a first video signal having a first number of scanning lines, compressing the first video signal received by the receiving means in a horizontal direction, and Compression means for compressing in the vertical direction by the scanning line conversion circuit according to any one of the above, and converting the first video signal into a second video signal having a second number of scanning lines smaller than the first number of scanning lines; A receiving device comprising: