KR19990003971A - PDP driving device of PDP-TV - Google Patents

Abstract

The present invention relates to a screen output device having a PIP capability in a PDP television. The present invention relates to a method for implementing a PIP suitable for a PDP television because a signal processing method for PIP implementation of a general television and a PIP implementation signal processing method for a PDP-TV are different.

The present invention outputs independent resolutions by applying the video signal for the main picture and the video signal for the sub picture sent from a broadcasting station to two video decoders, and converts the output resolution of the video decoder to the resolution desired by the viewer. By providing the ability to watch a high-definition screen, the viewer can watch the television and change the resolution of the main screen independent of the sub-screen, or one side of the full screen The sub-screen resolution can also be converted to the size desired by the viewer independently of the main screen. Therefore, when watching two channels on one TV at the same time, it is possible to freely adjust the size of the sub-screen, and the PIP-TV function of the PDP-TV that can freely adjust the screen size for the main screen is proposed.

Description

An apparatus for driving PIP of PDP-TV

The present invention relates to a PDP television having a PIP function. More particularly, the present invention relates to a PDP television which implements a PIP for controlling a resolution of a main screen and a sub screen of a PDP television having a PIP function separately by a viewer. It's about TV.

In general, a television receives a broadcast signal transmitted from each broadcasting station through an antenna so that a broadcast corresponding to a screen is displayed. An image of an object photographed by a camera at the broadcasting station is converted into an image signal, and the image signal is a constant high frequency signal. It transmits through a transmit antenna. The high frequency transmitted through the transmitting antenna is received through a receiving antenna installed in each home and applied to the television. The high frequency received by the television is received through the tuner circuit and applied to the television. The high frequency received by the television is converted into a predetermined frequency through a tuner circuit, and then divided into an image signal and an audio signal, and after a predetermined step, the image signal is displayed on a screen, and the audio signal is output through a speaker. At this time, when the user selects a broadcast channel to receive through a television by using a channel conversion switch, a program of a corresponding broadcasting station is displayed on the screen.

Further, the tuner circuit connected to the receiving antenna is composed of two tuner circuits in the case of a television having a PIP function. That is, it is comprised of the main tuner circuit which receives the image signal displayed on the full screen of a television, and the sub tuner circuit which receives the image signal displayed on one side of a full screen. Therefore, the high frequency received through the receiving antenna is simultaneously applied to the main tuner circuit and the sub tuner circuit, the image signal received by the main tuner circuit is displayed on the entire screen, and the image signal received by the sub tuner circuit is selected by the PIP function. It is displayed on the small screen indicated by.

1 is a block diagram of a screen display device having a PIP function in a conventional digital television receiver.

As shown in FIG. 1, a video decoder 1 (10a) for restoring a compressed main picture video signal to an original video signal, and a variable length coded sub picture video signal shown in FIG. And a video decoder 2 (10b) which extracts data for a specific frame (I-frame), extracts digital values necessary for the main picture and the sub picture, and outputs the reduced picture data. Interpolation and attenuator 12 for receiving the reduced image data output from 2 (10b) and interpolating or attenuating the image data according to the screen size signal to restore the image data of the sub-screen to the enlarged or reduced image data; Memory 16 for storing the image data of the sub-screen output from the interpolation and attenuator 12, Image data of the main screen output from the image decoder 1 (10a) and the sub-screen output from the memory 16 Spirit of A switching unit 22 for synthesizing the phase data, a microcomputer 14 for outputting a screen size signal and a window pan for controlling the sub-screen, and effective sub-screen image data under the control of the window size signal. An address generator 18 for supplying an address to the memory 16, and a timing generator 20 for supplying a timing signal to the switching unit 22 and the address generator 18 under the control of the screen size signal. As described above, it will be described in detail with reference to FIGS. 3 and 4 attached to the operation and effect of the prior art configured as described above.

As shown in FIG. 1, it is assumed that the compressed video bit stream is simultaneously input to the A channel and the B channel. At this time, the video bitstreams of the A and B channels refer to only the result obtained by correcting the error information by demodulating the signal transmitted on the transmission line and extracting only information about the image from the transport bitstream. A main channel, that is, A channel, that is, a channel for a screen that the viewer wants to view on the main screen, and a B channel refers to a subchannel, that is, a channel for a screen that the viewer wants to view on the sub screen. Although the B channel is illustrated as one in FIG. 2, two or more channels may exist. If there is no PIP function and only the video of the main channel is to be viewed, only the A channel signal is restored to the original video signal through the video decoder 1 (10a). The image decoder 1 (10a) is a block for decoding an image compressed in a method such as MPEG, which can be replaced by any known decoder.

The video signal input through the subchannel, that is, the B channel, is a reduced type of the video decoder 1 (10a), and an embodiment thereof is shown in FIG. In FIG. 2, the video signal of the B channel is restored to a code of a constant length like the other decoders through the variable length decoder 24. If the video signal is encoded to compensate for motion, the variable length decoder At 24, only data for a frame without motion, i.e., an I-frame, is extracted. In other words, if multiple P-frames and B-frames (motion compensation frames) follow one I-frame as in the case of MPEG, all data for these frames are removed and only the data for the I-frame is extracted. The output signal of the variable length decoder 24 is supplied to the DC value corrector 26 to extract only the DC value necessary for the PIP from the data for the I-frame. In the case of MPEG, it means the DC value for 8 × 8 blocks. do. In this way, the variable length decoder 24 can be implemented with a simpler structure of ordinary image data, i.e., a circuit related to motion compensation is unnecessary, and a code table or the like generated therein is unnecessary. You only need a table that decodes the data in variable length code. The DC value is usually composed of a sign rather than a variable length, and the DC value is restored to the image data reduced by the DC value corrector 26, where the reduced image data is reduced by the horizontal and vertical size of the DCT block. In the case of MPEG, the image data is reduced by 1/8 horizontally and vertically.

The operation principle of the variable length decoder 24 is shown in FIG. 4, and this principle can be applied to any existing variable length decoder. That is, the picture header is checked to determine whether it is an I-frame, and if it is I-frame data, the variable length decoder is restored through the variable length decoder 24, or the next picture head is continuously checked to check the I-frame. Skip until a frame is detected. After the above-mentioned variable length decoding process, in order to extract only the DC value, it is checked whether it is a DC value.

The reduced image data output through the image decoder 2 (10b) is supplied to the interpolation and attenuation unit 12 to adjust the size of the sub picture. That is, when a large size screen is desired in the production process, the data reduced through interpolation is restored to a larger size image data, and when a small size screen is desired, it is attenuated again.

In this case, the interpolation may be calculated by simply using a zoom or a calculation process between adjacent pixels, and the interpolation and attenuation circuit applied at this time may be any known technique. When the image data of the desired size is made, it is stored in the memory 16. The small sized sub picture data stored in the memory is inputted from the image decoder 1 (10a) by the switching unit 22. And are synthesized.

At this time, the switching unit 22 is controlled by the timing signal output from the timing generator 20, the timing generator 20 determines the time of switching between the main screen video signal and the sub-screen video signal, At the same time, the address generator 18 determines the time of occurrence of the address to output the data of the memory 16.

The microcomputer 14 outputs a control signal for outputting the position and screen size of the sub-screen image, that is, the size and information of the sub-screen, to the timing generator 20. The timing generator 20 outputs a timing signal into which sub-screen image data is inserted. In addition, the microcomputer 14 outputs the window size information to the interpolation and attenuator 12 to generate sub-screen image data of a desired size, and also outputs the size information to the timing generator 20. The video data of the sub-screen valid in the memory 16 is outputted by the timing signal outputted from the timing generator.

If P-frames or B-frames follow consecutively after an I-frame such as MPEG, the P-frame or B-frame is removed, so the image with the reduced I-frame is next. The output is repeated until an I-frame is generated. At this time, since the data for the I-frame is already stored in the memory 16, it is possible to output as many frames as desired.

However, when the interpolation and attenuator 12 does not exist in FIG. 1, the output of the image decoder is recorded in a memory composed of RAM of a predetermined capacity as shown in FIG.

In the case of a 2x zoom image, the address generator 18 generates an address so that data of one address is repeatedly read, and when reduced to 1/2, the address generator 18 skips the addresses in the memory 16 one by one. Let's do it. This allows you to reduce or enlarge the screen twice.

However, PDP-TVs that have advantages over other flat panel devices such as larger size and color, more than 40 ″, and wide viewing angles are different from the conventional CRTs. Therefore, there is a problem in that the above PIP implementation method cannot be applied as it is. .

Therefore, in order to solve the above problems, the present invention was devised, and the present invention is to receive a video signal and an audio signal, which are high-frequency signals transmitted from a broadcasting station, by a main tuner and a sub-tuner provided in a television having a PIP function, respectively. By applying the main signal and the sub-signal to the video decoder unit, the picture quality of the main screen corresponding to the full screen of the PDP-TV and the sub-screen corresponding to one side of the full screen can be improved, and the main screen and the sub-sized part are respectively resized. The purpose is to provide a function that can independently adjust the resolution of the sub-screen.

1 is a schematic block diagram of a PIP implementation of a conventional digital television;

FIG. 2 is a detailed view of the second video decoder shown in FIG. 1. FIG.

3 is a flowchart illustrating the operation principle of the variable length decoder illustrated in FIG. 2.

4 is a schematic block diagram of a PIP implementation in a PDP television according to the present invention;

FIG. 5 is a detailed view of the data rearrangement unit shown in FIG. 4. FIG.

* Explanation of symbols for the main parts of the drawings

10: video decoder unit 20: signal switching unit

30: signal controller 32: frame buffer unit

34: data rearrangement unit 38: address generation unit

40: memory section 50: data interface section

60: PDP portion 70: shift resist portion

80: multiplexer 90: 3-state buffer

First, as shown in FIG. 1, the configuration of the present invention is a video decoder for outputting a constant resolution in an RGB format by using a signal for a main picture passed through a main tuner circuit and a signal for a sub picture passed through a sub tuner circuit as input signals. And the interlaced scanning mode, which is a signal scanning mode, is converted into a sequential scanning mode, which is connected to the video decoder unit and uses the output video signal of the video decoder unit for the main screen and the output video signal of the video decoder unit for the sub-screen as input signals. Signal cultivation unit for adjusting the resolution, the data cultivation having a data rearrangement function connected to the signal switching unit, and outputs the data serially input in parallel with the frame buffer unit for temporarily storing the output signal of the signal switching unit A signal controller comprising a column section and an address generator for providing address information for each video signal; A memory unit consisting of an A-memory and a B-memory connected to the signal control unit and alternately reading and writing an RGB image signal output from the signal control unit, and connected to the memo unit, and outputting data from the memory unit to the PDP The data interface unit 50 serves to provide data in the form of data required by the negative address drive IC, and the PDP unit 60 is connected to the data interface unit.

According to the present invention, when a viewer watches a PDP television having a PIP function and wants to adjust the resolution of the sub-screen independently of the main screen, for example, the resolution of the sub-screen to be viewed may be increased or lowered. You can do this, you can increase the horizontal or vertical resolution, and you can also adjust the resolution of the main screen independently of the subscreen.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a device capable of adjusting the resolution of a main screen and a sub-screen of a television having a PIP function according to the present invention.

As shown in Fig. 1, in the present invention, an analog TV signal transmitted from a television broadcasting station to a television having a PIP function, that is, a video signal of a main screen and a video signal of a sub-screen is fixed through a main tuner circuit portion and a sub tuner circuit portion. The signal is converted into a signal and applied to the video decoder unit 10. The main signal is applied to the first video decoder unit 12, and the sub-signal is applied to the second video decoder 14 to be converted into RGB format, respectively. Data such as 480 or 720x480 and 853x480 is stored in the first field memory 14, and the data of the sub-signals are stored in the second field memory 18 and then output to the signal switching unit.

The data of the main signal output from the video decoder unit is applied to the first signal switching unit, and the data of the sub signal is applied to the second signal switching unit. Each signal switching unit includes a line doubler unit and a resizing unit. First, the line doubler unit converts interlaced signals transmitted from broadcasting stations into sequential signals.

The reason why the interlaced signal is converted into the sequential signal as described above is that, unlike the cathode ray tube which is driven one pixel at a time, the PDP-TV gradation method uses red, green and blue (RGB) produced by the target image. This is because the three primary color light components are separated by lines for a certain period of time and converted into electrical signals in order to transmit and receive. On the other hand, since the video screen of the computer is also a sequential scanning method, it is compatible with a computer with a built-in multi-function.

In addition, the resizing units 22b and 24b of the signal switching unit 20 provide a function of converting a signal for a resolution applied from the video decoder unit 10 to a resolution desired by the viewer. That is, when the output resolution of the first video decoder unit 12 is 640 × 480, if the user wants to switch to 720 × 480, the button manipulation unit (not shown) can switch through the microcomputer (not shown).

In addition, since the resizing unit 24b of the second signal switching unit also provides a function of changing the size of the sub-screen viewed by the button operating unit (not shown), the resizing unit 22b of the first signal switching unit 22 is provided. Functions like In addition, the data of the converted signal is applied to the frame buffer unit 32.

The frame buffer unit 32 compensates for the difference in the flow rate of the signal applied from the signal switching unit 30 or when the information generation point is different, and temporarily stores the data in order to effectively transmit the information without losing data. The signal is applied to the data rearrangement unit 34 by the control signal.

As shown in FIG. 5, the data rearrangement unit 34 is composed of a shift resist 70, a D-FF (flip-flop) multiplexer 80, and a three-state buffer 90. The image data provided in parallel (MSB to LSB) at 32 is rearranged so as to be stored as bits having the same weight Weihgt at one address of the frame memory. That is, while the shift resist A loads 8 samples of image data, the shift register B sequentially shifts the image data of 8 samples previously loaded from the most significant bit (8 bits) to the least significant bit (8 bits). Is output.

Therefore, in order to continuously rearrange the image data provided by the frame buffer unit 32, two shift resists A and B are provided so that the load and shift operations are alternately repeated. The D-FF and the multiplexer selects the same weighted data (Reordered Data) output in the shift mode and supplies them to the 3-state buffer.

It also provides two frame memories 40 capable of storing a single piece of image data, and allows them to continuously store and display image data by alternately performing writing and reading operations in units of frames. Therefore, the tri-state buffers A and B serve to connect the rearranged image data provided from the D-FF and the multiplexer to the frame memory in the recording mode.

This system converts and displays video data input by interlacing in a sequential manner, so that the order of write addressing and read addressing is different. That is, the image data of one frame stored in the memory reads one line of odd line data and then repeats reading of even line data. Further, in the PDP gradation processing, one field is divided into several subfields, and image data corresponding to each subfield must be read in turn and provided to the data interface unit 50, so that the reading order is structurally very different from the recording order. Will have Therefore, an address generator consisting of a write generator and a read generator is required, and serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B.

The output signal of the data rearranging unit 30 by the addressing signal alternately writes and reads the frame memory A 42 and the frame memory B 44, and the data stored in the memory A and the memory B are the data interface. It is applied as a negative to temporarily store the RGB data, and serves to provide the data in the form of data required by the address drive IC (not shown) of the PDP unit 60.

The output signal of the data interface unit is applied to the PDP unit 60 as a data stream, and the PDP unit writes information data for one line stored in the address drive IC, and turns on the data alternately at a high frequency after writing. Create a main and subscreen.

As can be seen from the above description, the present invention independently determines the resolution of the video signal for the main signal and the sub-signal in each video decoder unit, and also independently switches the resolution of the video decoder unit using different resizing units. This enables the viewer to watch the television with PIP function while watching the current screen, and to select the resolution of the main screen independently of the subscreen at the resolution desired by the viewer, and the resolution of the subscreen as the main screen. The effect is to be able to adjust the resolution independently.

Claims (4)

The video decoder unit 10 for converting the main screen signal and the sub-screen signal transmitted from the tuner circuit unit into the RGB format and outputting the signal for the main screen and the sub-screen signal at independent resolutions, respectively, and the video decoder unit. A signal switching unit (20) comprising a line doubler unit for converting the interlaced signal applied from the sequential signal into a sequential signal, a resizing unit for converting the resolution determined by the video decoder unit into a desired resolution, and an output signal of the signal switching unit. The output signal of the frame rearrangement unit 34 and the data rearrangement unit which outputs the parallel data of the frame buffer unit serially and the frame buffer unit 40 which temporarily store the data to be transferred to the data rearrangement unit as a constant signal are output to the frame memory unit. It is composed of an address generator which serves to provide a corresponding address according to a recording mode and a reading mode. A memory unit 40 comprising two field memories for storing one piece of image data by alternately writing and reading data provided by the data control unit of the call control unit 30 and the data rearranging unit of the signal switching unit in a frame unit; PIP of the PDP-TV, which comprises a data interface unit 50 and a PDP unit which temporarily store RGB data output from the memory unit and provide the data in the form of data required by the address drive IC unit of the PDP unit. Implementation device. 2. The video decoder unit according to claim 1, wherein the video decoder unit receives a signal transmitted from the main tuner unit and a signal transmitted from a field memory and a subtuner circuit for storing the resolution determined by the first video decoder unit 12 and the first video decoder unit. And a field memory (2) for storing the resolution of the sub-screen determined by the second video decoder unit. The apparatus of claim 1, wherein the signal switching unit provides a line doubler unit 22a for converting the interlaced mode of the main signal output from the video decoder unit into a sequential mode and a function for converting the resolution output from the video decoder unit to a desired size. The first signal switching unit 22 comprising the resizing unit 22b and the line doubler unit 24a for switching the interlacing mode of the sub-signals output from the video decoder unit to the sequential mode and the video decoder unit of the sub-signal A PIP-TV implementation apparatus for a PDP-TV, comprising a second signal switching unit (24) consisting of a resizing unit (24b) for providing a function for converting a resolution to a size desired by a viewer. The frame buffer unit 32 and the frame buffer unit of claim 1, wherein the signal controller 30 outputs the output signals of the first signal switch unit and the second signal switch unit to the data rearrangement unit in accordance with a control signal of the data. A PDP comprising an address generator 38 which serves to provide an output signal of a data rearrangement unit for providing a parallel output signal in series to a memory unit according to a write mode and a read mode of a frame memory; -PIP implementation of TV.