JPS5968782A - Image display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an image display control system, and more specifically, to a case where image information is sequentially read out from a refresh memory and displayed on a cathode ray tube (ch'r) in a rask scan format. The present invention relates to an operation control method.

[Prior art]

As is well known, in the Rusk scan image display method, horizontal
! ! There are 8 scanning methods and progressive scanning methods. The interlaced scanning method is 1 screen IIl! 1 Image information is read out from the fresh memory in two parts, the odd number set line segment and the even number foot position line segment.
This method displays on RT, and has the advantage of being able to use general-purpose standard television equipment for CRT, but ■i[! I
It has the disadvantage that the frequency of light emission per element becomes low and flickering increases.The sequential scanning method sequentially outputs the image information of one screen from the refresh memory.
This method of displaying on FL'r allows display with very little flickering, but it has the drawback of high cost because general-purpose standard television equipment cannot be used.

Therefore, when the same image information is to be monitored on multiple CRTs, the advantages of both methods are taken advantage of, and the interlaced scanning method is adopted for monitors where image quality is not a major issue in order to reduce costs and require high image quality. It is common to use the progressive scanning method only for monitors that use 1~ Previously, the interlaced scanning system and the progressive scanning system had completely different configurations, including the refresh memory.
As image information increases, each system requires a large amount of refresh memory, and there is a problem in that the advantages of both systems cannot be fully utilized.

[Purpose of the invention]

The purpose of the present invention is to generate image data for sequential scanning and IIb+ data for interlaced scanning from one system of refresh memory [7, and to make it possible to perform both types of display at the same time (
~ta lI! [Structure of the Invention] FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 1 is a progressive scanning system, which includes a progressive scanning address counter 11, a progressive scanning synchronization signal generating circuit 12,
Progressive scanning image data shift register 13, progressive scanning C
Ri' consists of 14. Reference numeral 2 denotes an interlaced scanning Z [scanning line], which includes an interlaced scanning address counter 21, an interlaced scanning synchronization signal generation circuit 22, an interlaced scanning image data shift register 23, and an interlaced scanning CRl' (standard television device) 24. 4 is a refresh memory that stores CI (i' display data), and the refresh memory is shared by both systems 1.2 and the central processing unit (CPU) 3 in a time-sharing manner.5 is a clock signal a, b and switching A time division controller outputs an instruction signal C, etc. A multiplexer 6 switches refresh memory access operations of the progressive scanning system 1, interlaced scanning system 2, and CP IJ 3 in response to the switching instruction signal C.

A timing chart for explaining the operation of FIG. 1 is shown in FIG. In FIG. 2, when the tarok signal a is used as a reference, the period of the clock signal S is set to twice the period of the clock a, and the generation timing of the switching instruction signal C is set to four times the period of the clock signal a. Every time the multiplexer 6 is supplied with the switching instruction signal C, the multiplexer 6 sequentially switches the sequential scanning system L, interlaced scanning system 2 and CP IJ according to the instruction.
The access operation for the refresh memory 4 in step 3 is sequential scanning → interlaced scanning → sequential scanning → CPU U-+ sequential scanning →
Interlaced scanning → Switch as follows. As a result,
The sequential scan system 1 is assigned access operation to the refresh memory 4 once every two times, and the interlaced scan system 2 and C
Each PIJ3 is assigned an access operation once every four times. Hereinafter, the operation of FIG. 1 will be explained with reference to FIG. 2, but in FIG.
It is assumed that the access time is about four times the period of clock a, and that image data A, B, C, .

It is assumed that initially the progressive scanning address counter 11 and the progressive scanning image data shift register 13 are all cleared. When the switching instruction signal C specifies sequential scanning system 1 until the end of cycle t1, through multiplexer 6,
The upper bits of the sequential scan address counter 11 except for the lower 3 bits of fff are supplied to the refresh memory 4, and the refresh memory 4 is accessed. For this access operation, data reading of the refresh memory 4 is completed at the end of cycle t4, and the refresh memory 4
The image data A (8 bits) at address 0 is set in the 111th order phagocytosis image data shift register 13. The image data A of the shift register 13 is serially output one pit at a time from the next cycle t5 in synchronization with the clock signal a, and ends at some point in the cycle t1□.

During this time, the sequential scanning address counter 11 is counted in binary by the clock signal a, and in cycle t8, the lower 3 bits are removed (if we pay attention to the upper bits, the self-answer is updated from 0 to 1).

Around the time t9, the switching instruction signal C again specifies +[next scanning system 1, and the value of the sequential scanning address counter 11 (excluding the lower 3 bits) is supplied to the refresh memory 4. Data reading from the refresh memory 4 is completed at the end of cycle t1°, and image data B (8 bits) at address 1 is set in the sequential scanning image data shift register 13. The image data B set in the shift register]3 is serially output one bit at a time from the next cycle t13, and ends at cycle t20.

Similarly, in cycle t17, "25, . . . and clock signal aO"), the access operation of if system 1 is sequentially designated every 8 clocks, and correspondingly, the access operations of 2nd and 3rd locations in refresh memory 4 are sequentially designated every 8 clocks. Survey location...01IiI
I image data C11], ... are cycles t20 and t28
, . . . is set in the shift register 13.

Then, from t2° to t2R, data C is '29 to t3
7, data D is sent one bit at a time from the shift register 13 to the song ri14! Data is output serially.

On the other hand, the sequential antenatal synchronization signal generation circuit 12 manually inputs the contents of the sequential scanning address terminal 1 to create a horizontal synchronization signal and a vertical synchronization signal. The horizontal synchronizing signal and the vertical synchronizing signal are wire-ORed with the image data outputted from the progressive scanning image data shift register 13 and input to the progressive scanning CRT 14. Sequential scanning c tt r-: 4
The raster is scanned synchronously with the clock signal a and
First, human image data is displayed on the CRT 14 without flickering.

In this case, it is assumed that the interlaced scanning address counter 21 and the interlaced scanning (I!lI image data shift register B) are all cleared at the beginning.The access operation of the refresh memory 4 to the interlaced scanning system 2 is performed in cycle t5
, t2+ . . . are assigned every 16 clocks of the clock signal a (every 8 clocks of the clock signal a). When the switching instruction signal c specifies the interlaced scanning system 2 around cycle t5, the upper bits of the interlaced scanning address counter 21 excluding the lower three pits are supplied to the refresh memory 4 through the multiplexer 6, and the refresh memory 4 is accessed. be done. In response to this access operation, the data reading of the refresh memory 4 is completed at the end of cycle t8, and the image data A of the 0 scan area is set in the interlaced scan image data shift register. The image data A of the shift register B is serially output one bit at a time from cycle t9 in synchronization with the clock signal B, and ends in the first half of cycle -.

During this period, the interlaced scanning address counter 21 has already counted the binary clock signal, and in cycle t15, if we pay attention to the upper bits excluding the lower 3 bits, we can see that from 0 to 1.
and continues until cycle t30. At the end of cycle '21, the switching instruction signal C is again switched to the interlaced scanning system 2.
, the interlaced scan address counter 21 at that time
(excluding the lower three pits) are supplied to the refresh memory 4. Data reading from the refresh memory 4 for this is completed at the end of cycle t24, and the image data B of one scanning area is transferred to the interlaced scanning image data shift register 23.
is set to The image data B set in the shift register is serially output bit by bit from the next cycle '25.

On the other hand, the interlaced scanning synchronization signal generation circuit 22 inputs the contents of the interlaced scanning counter 21 and generates a horizontal synchronization signal and a vertical synchronization signal. The horizontal synchronization signal and the stationary synchronization signal are wired-ORed with one curved image data output from the interlaced scan image data shift registers', ), 3, and input to the interlaced scan CRT 24. Of course, the clock signal 1 is before the raster foot of this okekoshi foot shift C ke 1' 24.
] is synchronized.

In this way, the operation of the Sen'etsu prenatal system 2 is basically the same as that of the sequential prenatal system a+, except that the clock cycle is different. However, in interlaced scanning system 2, when displaying one screen of image data, the first time is the lI! of odd-numbered scanning lines.
Rather than displaying the Il image data and displaying the even-numbered scan line image data the second time, it is divided into two times and displayed. For this reason, a certain scarlet lI! Every time all II image data is read out from the refresh memory 4, the time division controller 5 outputs a signal 1'rM7] to the interlaced scanning counter 21'') R scanning line + Tj star address section \+
IL, image data reading of refresh memory 4 and CR
'1' Synchronizes with the force of 24 over scanning. In addition, in the interlaced scanning yarn #2, the sequential scanning system 11C:l'6
Since only the image data of odd or even scanning lines, which is half of the display period of one screen, is displayed, it is undeniable that there is flickering compared to the normal scanning.

Operation of the central processing unit In the timing chart of FIG. 2, the cycles t13 to t
16,'29~t3□, . . . are allocated for CPU3. Utilizing this period, C and P U 3 access the refresh memory 4 and perform changes such as changing the image data. At this time, multiplexer 6
3 is selected and supplied to the refresh memory 4. Image data is transferred through data line 9.

An embodiment of the present invention has been described above. By pulling out the signal line 8 from the input side of the interlaced scanning ct-t '1" 24 and connecting other standard video equipment to this, the interlaced scanning system 2 It is also important to provide the standard video signal obtained with the standard video signal to other standard video equipment.

Although it is assumed that image data of about 8 pixels is stored in each band of the refresh memory 4, this is, of course, only an example, and the same applies whether the number of pixels is more than 8 pixels or less.

〔Effect of the invention〕

(11) As explained above, according to the present invention, the data for sequential feeding bacteria and the image data for interlaced scanning are read out from one system of refresh memory, and both sequential scanning and interlacing scanning methods can be displayed at the same time. It is possible to construct a mixed display system of both types at a relatively low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram for explaining the operation shown in FIG. ■...Sequential scanning system, 2...Interlaced scanning system, 3...
・Central processing unit, 4... Refresh memory, 5...
・Time division controller, 6...Multiplexer, 11
... progressive scanning address counter, 12... progressive scanning synchronization signal generation circuit, 13...) Visceral rectangular scanning lI! II image data shift register, progressive scan CI-tT, 21.
...Interlaced scanning address counter, 22...Interlaced scanning synchronization signal generation circuit,...Interlaced scanning image data shift register,...Interlaced scanning C 几T0゜7...Papa

Claims (1)

[Claims] In a system for simultaneously displaying image information in a PI-IJ fresh memory on a sequential scanning type display device and an interlaced scanning type display device, the image information in the refresh memory is read out in a time-sharing manner at predetermined time intervals, and each The image information of the second register is read out pit serially in synchronization with the first clock and supplied to the progressive scan type display device, and the image information of the second register is stored in the second register. An image display control system characterized in that the data is read bit serially in synchronization with a second clock having a period twice that of the first clock and is supplied to the interlaced scanning type display device.