JPH0321919B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an image display control device.
The present invention relates to an image display control device for simultaneously displaying image information in a refresh memory on a progressive scanning type display device and an interlaced scanning type display device.

[Prior art]

As is well known, raster scan image display methods include interlaced scanning and progressive scanning. The interlaced scanning method is a method in which the image information for one screen is read out from the refresh memory twice, once for odd-numbered scanning lines and once for even-numbered scanning lines, and displayed on the CRT, and a general-purpose standard television device can be used for the CRT. Although it has advantages, the frequency of light emission per pixel is low,
It has the disadvantage of increased flickering. Progressive scanning is a method in which image information for one screen is sequentially read out from refresh memory and displayed on a cathode ray tube (CRT), which allows display with very little flickering, but uses general-purpose standard television equipment. This has the drawback of increasing costs.

Therefore, when the same image information is to be monitored on multiple CRTs, the advantages of both methods are taken advantage of, and for monitors where image quality is not a major issue, an interlaced scanning method is adopted to reduce costs and require high image quality. It is common to use the progressive scanning method only for monitors that use However, in the past, the interlaced scanning system and the sequential scanning system had completely separate configurations, including refresh memories.As image information increased, large capacity refresh memories were added to each system. The problem is that the advantages of both methods cannot be fully utilized.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image display control device that allows sequential scanning image data and interlaced scanning image data to be read out from a single system of refresh memory and displaying both types of data at the same time.

[Structure of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, 1 is a sequential scanning system;
It consists of a progressive scanning address counter 11, a progressive scanning synchronizing signal generation circuit 12, a progressive scanning image data shift register 13, and a progressive scanning CRT 14. 2 is an interlaced scanning system, which includes an interlaced scanning address counter 21, an interlaced scanning synchronization signal generation circuit 22, an interlaced scanning image data shift register 23, an interlaced scanning
Consists of 24 CRTs (standard television sets). 4
is a refresh memory for storing CRT display data, and the refresh memory is shared by both systems 1 and 2 and a central processing unit (CPU) 3 in a time-sharing manner.
Reference numeral 5 denotes a time division controller that outputs clock signals a, b, switching instruction signal c, and the like. 6 is a sequential scanning system 1 and an interlaced scanning system 2 according to a switching instruction signal c.
and a multiplexer for switching the refresh memory access operation of the CPU 3.

A timing chart for explaining the operation of FIG. 1 is shown in FIG. In FIG. 2, when clock signal a is used as a reference, the period of clock signal b is set to twice the period of clock a, and the generation timing of switching instruction signal c is set to four times that of clock signal a. Every time the multiplexer 6 receives the switching instruction signal c, the access operation for the refresh memory 4 of the progressive scanning system 1, the interlaced scanning system 2, and the CPU 3 is sequentially performed according to the instruction: sequential scanning→interlaced scanning→sequential scanning→CPU → sequential scanning → interlaced scanning → etc. As a result, the progressive scanning system 1 is assigned an access operation to the refresh memory 4 once every two times, and the interlaced scanning system 2 and the CPU 3 are each assigned an access operation once every four times. below,
The operation of FIG. 1 will be explained with reference to FIG. 2. In FIG. 2, for convenience, it is assumed that the access time of the refresh memory 4 is approximately four times the period of the clock a.
It is assumed that image data A, B, C, . . . are stored in units of 8 pixels each in order from address 40 of the refresh memory 4.

Operation of the progressive scanning system It is assumed that the progressive scanning address counter 11 and the progressive scanning image data shift register 13 are all cleared at first. When the switching instruction signal c specifies the sequential scanning system ₁ around cycle t1, the upper bits of the sequential scanning address counter 11 excluding the lower 3 bits are supplied to the refresh memory 4 through the multiplexer 6. 4 is accessed. For this access operation, reading data from the refresh memory 4 is completed at the end of cycle _t4 , and the refresh memory 4
Image data A (8 bits) at address 0 is set in the sequential scanning image data shift register 13. The image data A of the shift register 13 is serially output one bit at a time from the next cycle _t5 in synchronization with the clock signal a, and ends in the middle of the cycle _t12 .

During this period, the sequential scanning address counter 11 is also being counted in binary by the clock signal a, and in cycle _t8 , when paying attention to the upper bits excluding the lower 3 bits, the contents are updated from 0 to 1. The switching instruction signal c again specifies the sequential scanning system 1 until the time of _t9 , and the value of the sequential scanning address counter 11 (excluding the lower 3 bits) is supplied to the refresh memory 4. Data reading from the refresh memory 4 for this is completed at the end of cycle _t12 , and image data B (8 bits) at address 1 is read out.
is set in the sequential scanning image data shift register 13. The image data B set in the shift register 13 is serially output one bit at a time from the next cycle _t13 , and ends at cycle _t20 .

Similarly, the access operation of the sequential scanning system 1 is specified every eight clocks of the clock signal a in cycles t ₁₇ , t ₂₅ , . The image data C, D, . . . are set in the shift register 13 at the end of cycles t ₂₀ , t ₂₈ , . and,
Image data is serially output from the shift register 13 one bit at a time, such as data C from t ₂₁ to _{t 28} and data D from t ₂₉ to t ₃₇ .

On the other hand, the progressive scan synchronization signal generation circuit 12 inputs the contents of the progressive scan address counter 11 and generates a horizontal synchronization signal and a vertical synchronization signal. The horizontal synchronizing signal and the vertical synchronizing signal are wire-ORed with the image data output from the progressive scanning image data shift register 1 and input to the progressive scanning CRT 14. The raster of the progressive scanning CRT 14 is scanned in synchronization with the clock signal a, and the input image data is displayed on the CRT 14 without flickering.

Operation of the interlaced scanning system Also in this case, the first interlaced scanning address counter 21 and the interlaced scanning image data shift register 2
3 is all cleared. The refresh memory 4 accesses the interlaced scanning system 2 in cycles t ₅ , t ₂₁ . . . every 16 clocks of the clock signal a (8 cycles of the clock signal b).
(clockwise). When the switching instruction signal c specifies the interlaced scanning system 2 around cycle _t5 , the upper bits of the interlaced scanning address counter 21 excluding the lower 3 bits are supplied to the refresh memory 4 through the multiplexer 6. 4 is accessed. In response to this access operation, data reading from the refresh memory 4 is completed at the end of cycle _t8 , and image data A at address 0 is set in the interlaced scanning image data shift register 23. The image data A of the shift register 23 is serially output one bit at a time from cycle _t9 in synchronization with the clock signal b, and ends in the first half of cycle _t24 .

During this time, the interlaced scanning address counter 21 is also being counted in binary by the clock signal b, and the cycle
At t ₁₅ , if we look at the upper bits excluding the lower 3 bits, they are updated from 0 to 1, which is the cycle
Lasts until _t30 . When the switching instruction signal c again instructs the interlaced scanning system 2 around cycle _t21 , the value of the interlaced scanning address counter 21 at that time (excluding the lower 3 bits) is supplied to the refresh memory 4. Data reading from the refresh memory 4 is completed at the end of cycle _t24 , and image data B at address 1 is set in the interlaced scanning image data shift register 23. The shift register 23
The image data B set in
It is serially output one bit at a time from _t25 .

On the other hand, the interlaced scanning synchronization signal generation circuit 22 inputs the contents of the interlaced scanning counter 21 and generates a horizontal synchronization signal and a vertical synchronization signal. The horizontal synchronizing signal and the vertical synchronizing signal are wire-ORed with the image data output from the interlaced scanning image data shift register 23 and input to the interlaced scanning CRT 24. Naturally, this interlaced scanning CRT2
4 raster scanning is synchronized with clock signal b.

Thus, the operation of interlaced scanning system 2 is basically the same as that of progressive scanning system 1, except for the difference in clock period. However, in interlaced scanning system 2, to display one screen of image data,
The image data will be displayed twice, with the first time displaying the image data of odd-numbered scanning lines, and the second time displaying the image data of even-numbered scanning lines. Therefore, every time all the image data of a certain scanning line is read out from the refresh memory 4, the time division controller 5 sends the interlaced scanning counter 2 through the signal line 7.
The scanning line designation address section of 1 is incremented by 1 to synchronize reading of image data from the refresh memory 4 and interlaced scanning of the CRT 24. Note that in the interlaced scanning system 2, only the image data of odd or even scanning lines, which is half of the display period of one screen in the progressive scanning system 1, is displayed.
It is undeniable that "flickering" occurs compared to sequential scanning.

Operation of the central processing unit In the timing chart in Figure 2, the cycle
t ₁₃ to _{t 16} , t ₂₉ to t ₃₂ , . . . are allocated for the CPU3. Using this period, the CPU 3 accesses the refresh memory 4 and rewrites the image data. At this time, multiplexer 6
selects the memory address output from the CPU 3 and supplies it to the refresh memory 4. Image data is transferred through data line 9.

Although one embodiment of the present invention has been described above,
By pulling out the signal line 8 from the input side of the interlaced scanning CRT 24 and connecting other standard video equipment to it, it is also possible to give the standard video signal obtained by the interlaced scanning system 2 to other standard video equipment.

Although it is assumed that image data in units of 8 pixels is stored at each address in the refresh memory 4,
Of course, this is just an example, and the same applies to 8 or more pixels or less.

〔Effect of the invention〕

As explained above, according to the present invention, image data for sequential scanning and image data for interlaced scanning are read out from one system of refresh memory under the control of a common controller, Display can be performed simultaneously, making it possible to construct a mixed display system of both types at relatively low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a timing diagram for explaining the operation of FIG. 1. 1...sequential scanning system, 2...interlaced scanning system, 3
... Central processing unit, 4 ... Refresh memory,
5... Time division controller, 6... Multiplexer, 11... Sequential scanning address counter, 12...
...Progressive scanning synchronization signal generation circuit, 13...Progressive scanning image data shift register, progressive scanning CRT,
21... Interlaced scanning address counter, 22... Interlaced scanning synchronization signal generation circuit, 23... Interlaced scanning image data shift register, 24... Interlaced scanning
CRT.

Claims (1)

[Scope of Claims] 1. In an image display control device that simultaneously displays image information from the same refresh memory on a sequential scanning type display device and an interlaced scanning type display device, a first address counter updated by a first clock; , a first address counter that inputs the contents of the first address counter and generates a horizontal synchronization signal and a vertical synchronization signal.
It consists of a synchronization signal generation circuit, and a first shift register that stores the image information read out from the refresh memory and reads it bit serially in synchronization with the first clock, and generates the horizontal synchronization signal, the vertical synchronization signal, and the image information. a second address counter updated by a second clock; and a second address counter that inputs the contents of the second address counter to generate a horizontal synchronization signal and a vertical synchronization signal. 2
It consists of a synchronization signal generation circuit and a second shift register that stores the image information read out from the refresh memory and reads it bit serially in synchronization with a second clock. an interlaced scanning control system which provides an interlaced scanning type display device; and a switching control system that switches to the first address counter or the second address counter at predetermined time intervals, and controls the reflection according to the contents of the first address counter or the second address counter. a multiplexer that reads out image information from the storage memory and supplies it to the first shift register or the second shift register; a first clock, a second clock having a cycle twice that of the first clock, and a switching instruction signal; The first clock is connected to the progressive scan control system;
An image display control device comprising: a time division controller that applies a clock to the interlaced scanning control system and a switching instruction signal to the multiplexer.