KR930005808B1 - Display system - Google Patents

Abstract

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Description

Burn system

1 is a circuit diagram showing an essential part of an embodiment of a display control apparatus according to the present invention.

2 is a timing diagram showing an operation example of the apparatus shown in FIG.

3 is a block circuit diagram showing an example of use of the display control device according to the present invention.

4 is a circuit diagram showing another embodiment of the present invention.

5 is a detailed circuit block diagram of the phase difference detection circuit of FIG.

6 and 7 are timing diagrams showing an operating state in a part of the apparatus shown in FIG.

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a particularly effective technique applied to an imaging system, and furthermore to a control device for displaying digital image information. It is about.

For example, in order to display the image information written to the storage device by a computer or the like on the CRT display device, it is necessary to access the storage device to read the image information and to form a synchronization signal corresponding to the access interval. have. Since such a series of processing operations are executed in, for example, a CPU (central processing unit) of a computer system, the task of the CPU becomes large, and the overall processing capacity is significantly reduced. Thus, the present inventors have previously proposed a dedicated display control apparatus that independently executes the above-described processing operations, namely, management of the storage device, formation of a synchronization signal, and the like. Hitachi Seisakusho Festival).

This display control device, also called a CRTC, is used to display the image information stored in the storage device on a scanning type display device that constitutes a display screen by a horizontal scanning line and a vertical frame. And a scan counter which proceeds in a cycle according to the above and periodically counts the contents, and accesses the storage device by the address data formed in accordance with the count contents of the scan counter, Therefore, it has a function of generating a horizontal synchronizing signal and a vertical synchronizing signal in each. This CRTC is semiconductor integrated circuit and is used, for example, as a peripheral device connected to the system bus of the CPU. As a result, the CPU can be freed both hardware and software from tasks for complicated display control, thereby improving the processing capacity of the entire system.

By the way, the present inventors have considered using multiple CRTCs and superimposing the image information stored in each memory device managed by each CRTC on one display screen. However, it has been clarified by the present inventors that this is not sufficient by making the same basic clock to be given to each CRTC. That is, in the CRTC, for example, a horizontal synchronizing signal and a vertical synchronizing signal are formed in order to display on the CRT display device. This synchronization signal is generated by a scan counter that counts an externally provided basic clock. Here, even if several CRTCs each generate the same periodic signal with respect to the same basic clock, the phases of the synchronization signals are not necessarily identical. For example, if either of the count contents of the scan counters in one CRTC differs from that of the other CRTC, the other state appears as a difference in phase of the synchronization signal, and then the state continues without modification. Then, the positional relationship of the superimposed images is disturbed or the synchronization is disturbed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image system in which a plurality of image information managed by each CRTC can be superimposed on one display screen while maintaining a constant positional relationship with each other.

It is another object of the present invention to display image information displayed by a display system having an independent synchronization signal system such as a television system and image information managed by the CRTC superimposed on one display screen while maintaining a constant positional relationship with each other. To provide one imaging system.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative ones of the inventions disclosed herein are as follows.

That is, in order to achieve the above object of the present invention, the present invention represents first data for representing a first reference value, second data for representing a second reference value, and one of an internal and an external mode. Register means for storing third data for output, a horizontal counter means for incrementing in response to a clock signal and generating a count, and outputting a horizontal synchronizing signal when the count generated in the horizontal unter means matches the first data First means for comparing, a vertical counter means for increasing a count in response to the horizontal synchronizing signal, and a second for outputting a vertical synchronizing signal when the count generated in the vertical counting means coincides with the second data; A third data having address generating means for generating an address for accessing the memory means in response to the comparing means and the horizontal and vertical counter means; When the other indicates the internal mode, the horizontal counter means is set to an initial value according to the coincidence signal between the count generated by the horizontal counter means and the first data, and the vertical counter means is set to the second counter and the count generated by the vertical counter means. The initial value is set in accordance with the coincidence signal with the data, and when the third data indicates the external mode, each of the horizontal and vertical counter means is set with the initial value in accordance with the synchronization signal from the video signal generating means. It is to provide an image system having a.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings.

In addition, in drawing, the same or corresponding part is shown with the same code | symbol.

1 shows an embodiment of the main part of the display control device according to the present invention.

The display control apparatus 10 shown in the same drawing is also called a CRTC. First of all, the outline of the display control apparatus 10 is a display of a scanning method that forms a display screen by horizontal scanning lines and vertical frames. In order to display on the device, scan counters C ₁ and C ₂ are provided in the cycle according to the access timing of the storage device, and the count contents are periodically cycled. The storage device is accessed by the address data Ad created in accordance with the count contents D ₁ and D ₂ of the scan counters C ₁ and C ₂ . Along with this, the horizontal synchronizing signal Hs and the vertical synchronizing Vs are generated in accordance with the count contents D ₁ and D ₂ of the scanning counters C ₁ and C ₂ , respectively. The contents of the scan counters C ₁ and C ₂ are initialized to a constant value by a signal Ex supplied from the outside.

Here, the scanning counters C _1, C ₂ is formed of a scan counter C ₂ of the second to synchronize the first scan counter C ₁ and the vertical frame of the to synchronize the horizontal scanning line, the first, second Both scanning counters C ₁ and C ₂ are initialized to constant count contents by externally applied signals.

In addition, the display control device 10 is configured to be semiconductor integrated circuit (LSI) and to be used as a peripheral device, for example, as a peripheral device to a system bus of a CPU, as described in detail with reference to FIG. . As the display device, an interlace CRT display device of interlaced scanning method is used. The storage device is called a refresh memory or video RAM (VRAM) or the like, and RAM (random access memory) is usually used.

More specifically with reference to FIG. 1, the apparatus shown in the same drawing includes an access timing detection counter C ₀ , a data comparison circuit CP ₀ , CP ₁ , in addition to the first and second scan counters C ₁ , C ₂ described above. CP ₂ , addresser generation circuit 20, interlace control circuit 12, pulse cutting circuit 14, terminal switching circuit 16, AND gate G ₁ , and the like. In addition, an externally writeable control register group 22 is provided, and various operation modes of the display control apparatus 10 are set or selected according to the contents written in these resist groups. The control reference group 22 also sets the comparison reference values R ₁ , R _{2 of} the data comparison circuits CP ₁ , CP ₂ , and a control signal R ₄ for determining the switching position of the terminal switching circuit 16.

The control circuit 21 selects an address register (not shown) for selecting one register of the register group 22, a control signal (e.g., a read / write signal, a chip select signal, and an address register or a register group). Input control terminal CNL, data input terminal DB, and output terminals CL ₁ to CL _n that receive a register selection signal.

The control register group 22 includes a plurality of registers corresponding to output terminals R ₀ to R ₄ , output terminals R ₀ to R ₄ , bidirectional data terminals connected to the input terminal DB, and output terminals CL ₁ to ₁ of the control circuit 21. It has a control signal input terminal connected to CL _n .

In the CRT display device, the control input terminal CNL is connected to the address bus line of the CPU system, and the input terminal DB is connected to the data bus line of the CPU system. The control signal of the control terminal CPU is in the write state of the address register (chip select signal CS is the select level (i.e., low level), register select signal RS is the select level (i.e., low level) of address register, read / write signal R / The address register is selected when W is a write level (ie, low level).

Therefore, register selection data for selecting one register of the register group 22 is written to the address register via the input terminal DB. After the write operation is completed, the control signal is converted to the write state of the register group 22 (the register selection signal RS is converted to the selection level (that is, the high level) of the register group 22), and then one of the register groups is selected. Is selected according to the contents of the address register in the control circuit 21. Therefore, control data is written to the designated register of the register group 22 via the input terminal DB. The control data R ₀ to R ₄ are written to each register of the register group 22 by repetition of such an operation.

Since the pulse period of the pulse signal P _{1 and} the pulse period of the pulse signal P ₂ are determined by the data R ₁ and R ₂ , the display size (horizontal size and vertical size) of the display panel is determined by the data R ₁ and R ₂ . Is determined.

Here, the basic clock? Is first input to the display control device 10. This basic clock ø is, for example, synchronized with the clock of the system to which the display device 10 is connected. This basic clock ø becomes the count input of the access timing detection counter C ₀ . The counter C ₀ is advanced by the basic clock ø. When the count content D ₀ reaches the comparison reference value R ₀ of the data comparison circuit CP ₀ , the counter C ₀ is reset to restart the count at the initial value 0. In other words, the count content D ₀ is periodically cycled. Then, the pulse signal P ₀ output from the data comparison circuit CP ₀ is output to the outside as the access control signal CE of the storage device RAM that stores the image information for each cyclic period. As a result, the storage device is accessed every fixed period, and pixel information for one word (for example, 8 bits or 16 bits) is read at each access timing.

The pulse signal P ₀ is a count input of the _first scan counter C ₁ . The count C ₁ is advanced by the input pulse signal P ₀ , and when the count content D ₁ reaches the comparison reference value R ₁ of the data comparison circuit CP ₁ , the count is reset and the count is restarted from the initial value (0). have. That is, the count content D ₁ is cyclically cycled. The spread signal P ₁ output from the data comparison circuit CP ₁ is output to the outside as the horizontal synchronizing signal Hs of the CRT display device through the interlace control circuit 12 for each cycle. At this time, the cycle of the _first scanning counter C ₁ is assumed to correspond to a period in which the image information for one horizontal scan is read in the storage device. That is, the comparison reference value R ₁ is set so that the count content D ₁ of the first scanning counter C ₁ returns to the initial value 0 when the raster image information is read.

The pulse signal P ₁ generated for each cycle of the first scan counter C ₁ becomes the count input of the _second scan counter C ₂ . The counter C ₂ proceeds with the input pulse signal P ₁ , and when the count content D ₂ reaches the comparison reference value R ₂ of the data comparison circuit CP2, the counter C ₂ is reset to restart the count from the initial value 0. . In other words, the second scan counter C ₂ also periodically cycles the count contents D ₂ . Then, the pulse signal P ₂ output from the data comparison circuit CP ₂ is output to the outside as the vertical synchronization signal Vs of the CRT display device through the interlace control circuit 12 for each of the purifying cycles. At this time, the cycle period of the _second scanning counter C ₂ is assumed to correspond to a period in which one field of image information is read in the storage device. In other words, when the image information corresponding to 1/2 of the total number of rasters constituting the display screen is read, the comparison reference value R ₂ returns the count content D ₂ of the second scanning counter C ₂ back to the initial value (0). Is set. Each time the cycle period of the second scan counter C ₂ is repeated twice, image information of two fields, that is, one frame, is read and displayed on the CRT display device in an interlaced manner. For example, in the case of displaying on a conventional television type CRT display device, about 60 vertical synchronization signals Vs are formed every second, thereby forming a frame 30 seconds per second.

The count contents D ₁ and D ₂ of the first and second scan counters C ₁ and C ₂ are provided to the address generating circuit 20. The address generation circuit 20 forms address data Ad for accessing the storage device in accordance with the two count contents D ₁ and D ₂ . As a result, the image information stored in the storage device is read in synchronization with the synchronization signals Hs and Vs.

The interlace control circuit 12 inserts a dummy raster into the horizontal synchronizing signal Hs to perform so-called interlaced scanning, or performs a scan for shifting the phase of the vertical synchronizing signal Vs once by one half of the horizontal syringe. Run To this end, this interface control circuit 12 has a function of discriminating between odd-numbered field periods and even-numbered field periods. This function can be obtained simply by using a binary flip-flop, for example, driven by a vertical synchronization signal. Therefore, the interlace control circuit 12 can obtain, for example, an odd field (or even field) detection signal Vi that activates only an odd field period (or even field period) every frame.

Here, when the AND gate G ₁ takes a logical product of the odd field detection signal Vi obtained in the interlace control circuit 12 and the pulse signal P ₂ generated for each cycle period of the second scan counter C ₂ , the odd number is obtained. Only the first vertical sync signal is extracted. The odd-numbered vertical synchronizing signal extracted in this manner is led to the outside of the display control device 10 as an external synchronizing signal Ex via the terminal switching circuit 16.

As mentioned above, although the part which generate | occur | produces the synchronization signal Ex externally was demonstrated, the said display control circuit 10 is comprised also when receiving the external synchronization signal Ex. The external synchronization signal Ex is an odd (or even) only vertical synchronization signal similarly to the signal Ex outputted to the outside. The external synchronization signal Ex is input to the pulse cutting circuit 14 via the terminal switching circuit 16. In the pulse cutting circuit 14, a narrow pulse is cut by the external synchronization signal Ex. Then, the cut narrow pulses are distributed to each counter C ₀ , C ₁ , C ₂ as a clear signal (reset signal or initial value signal) CR. As a result, when the external synchronization signal Ex is input, is presented in synchronization with this, each counter C _0, C _1, the count content D _0, D _1, D ₂ are simultaneously initialized (reset to 0) of C _2. The binary flip flop FDFF in the interlace control circuit is initialized to its initial state in accordance with the reset signal CR output from the pulse cutting circuit 14. By doing so, when the external synchronization signal is input to the CRTC, the counters C ₀ to C ₁ are reset to their initial states, and the binary flip-flops are reset to their initial states where the FDFF becomes an even field (or odd field). .

This initialization is performed every frame, for example, if the external synchronization signal Ex is from the display control device 10 having the same configuration. Therefore, even if a count error or the like occurs in any of the counters C ₀ , C ₁ , and C ₂ , the error is automatically corrected at the start of the next frame period. As a result, the synchronization between the various display control devices can be reliably and continuously aligned, and the image information described in the various storage devices can always be polymerized and displayed in the correct positional relationship. As a result, for example, the composition of a plurality of images to form a complex or various images can be performed simply and at high speed.

Here, in the embodiment, whether to output the external synchronization signal Ex to the outside or to the outside is determined by the switching state of the terminal switching circuit 16. The switching state of the terminal switching circuit 16 is controlled by the control signal R ₄ set by the register group 22. Therefore, whether to use the display control device 10 as a master or as a slave can be freely selected by the setting operation to the resist group from the outside (not shown) which is executed at the time of use thereof. Along with this, only one signal terminal for synchronizing multiple display control devices can be completed.

2 is a timing diagram showing an operation example of the above-described display control device.

In the same figure, Ta denotes an access cycle of a storage device, Th denotes a horizontal scanning period, Tv denotes a field period, and Ts denotes a period of an external synchronization signal Ex generated every frame.

In the above description, the initial setting of the scan counter periodically by the synchronization signal Ex has been described. Here, such an initial setting simply resets the scan counter to 0, but also includes a method of forcing the scan counter to the state of the above-mentioned value. In the latter case, the addresses generated in one CRTC need not be the same as the address signals of other CRTCs that display the same data stored in different storage devices or overlap each other on the display device.

3 shows an example of use of the display control apparatus 10 described above.

In the use example shown in the same figure, two display control apparatuses 10A and 10B are used. Each of the display control devices 10A and 10B is connected to the address bus AB and the data bus DB of the computer system 100 so as to operate as a peripheral device of the computer system 100. The computer system 100 is comprised of CPU, ROM, RAM, I / O, etc., for example.

Each display control device (CRTC ₁ , CRTC ₂ ) 10A, 10B manages memory devices (RAM) 30A, 30B in which image information is stored, respectively. The image information read from each of the memory devices 30A and 30B is converted into serial image signals Sa and Sb by the parallel-serial conversion circuits (P / S conversion circuits) 32A and 32B. , Together with the vertical and horizontal synchronizing signals Hs and Vs output from the display control device 10A, they are input to the video controller 40. The video controller 40 creates an image signal Sab of the CRT display device 50 and a synchronization signal Ss in accordance with the input signal. As a result, the CRT display device 50 displays the image information Sa and Sb read from the two storage devices 30A and 30B in a state of mutual polymerization.

Here, one of the two display control devices 10A and 10B is set to generate the synchronization signal Ex to the outside every one frame period. In addition, the other device 10B is set to input an external synchronization signal Ex generated by one device 10A. That is, when using the display control device, the register therein is set so that the display control device 10A becomes the master by the computer system 100, and the register therein is set so that the display control device 10B becomes the slave. have. As a result, one display control device 10A acts as a master and the other display control device 10B operates as a slave, and the device 10B reliably follows and synchronizes with the device 10A. .

4 illustrates another embodiment of the present invention.

The embodiment shown in the same drawing uses the above-described display control device 10, and is used for the image information St and the display control device 10 displayed on a display system having an independent synchronization signal system, such as the television system 60. The image information Sc managed by the same is superimposed on one CRT display device 50 while maintaining a constant positional relationship.

As for the display control device 10, as described above, the display device of the interlaced scanning method that forms the display screen of the image information stored in the storage device 30 by horizontal scanning lines and vertical frames, that is, CRT display in this case. In order to display on the device 50, the scanning device is provided with a scanning counter which proceeds in a cycle according to the access timing of the storage device 30 and in which the count contents cyclically cycle. The memory device 30 is configured to access the storage device 30 by the address data Ad created in accordance with the count contents of the scan counter. In addition, horizontal and vertical synchronization signals are formed in accordance with the count contents of the scan counter.

The television system 60 causes the CRT display device 50 to display the image information St on the television system 60 side using a synchronization signal Ss formed independently.

Here, the display control device 10 is used together with a basic clock generation circuit 65 and the like which are configured by using a phase difference detection circuit 62, an AND gate G _{11, a} phase locked loop (PLL) 64, and the like.

The basic clock generation circuit 64 forms the basic clock? Of the display control device 10 in accordance with the horizontal synchronizing signal Hst generated by the television system 60. The display control device 10 forms the access control signal CE, the address data Ad, the vertical synchronization signal Vs, and the like of the storage device 30 in accordance with the basic clock _.

The phase difference detection circuit 62 also detects a phase difference between the vertical synchronization signal Vs generated by the display control device 10 and the vertical synchronization signal Vst generated by the television system 60. As shown in FIG. 5, this phase difference detecting circuit 62 is comprised of flip-flops DFF ₁ , DFF ₂ , a NAND gate circuit ND, and an inverter IV. This DFF ₁ is used to detect the phase difference between the external vertical synchronization signal Vst and the external horizontal synchronization signal Hst. As shown in Figs. 6A and 6B, in the even field, the leading edge (time: t ₂ ) is ahead of the leading edge (time: t ₃ ) of the horizontal synchronization signal Hst by half a period of the horizontal scanning period. On the other hand, in the odd field, the leading edge of the signal Vs and the leading edge (time: t ₆ ) of the signal Hst coincide with each other.

Flip-flop DFF ₁ receives signals Vst and Hst at data input terminal D and clock input terminal C, respectively. Therefore, the leading edge (time: t ₃ ) of the output Q ₁ of the flip-flop DFF ₁ is delayed by half a period with respect to the signal Vst in the even field, as shown in FIG. 6C. On the other hand, in the odd field, the leading edge of the signal Q _{2 and} the leading edge of the signal Vst coincide with each other.

The flip-flop operation of the DFF ₂ is the same as the operation of the flip-flop DFF _1. The timing diagram of the flip flop DFF ₂ is shown to 6d-g degrees. The period from time t ₂ to t ₆ indicates the even field of the television system 60 and the horse field for the CRTC 10, as shown in FIG. Is at a high level at time t ₄ , and output Q ₁ is at a low level at time t ₅ . According to this, the output PD of the inverter IV becomes a high level for a period of time t ₄ to t ₅ . In this case, as shown in FIG. 6I, the output Ex of the AND gate circuit G ₁₁ is kept at the low level because the external signal Vst falls to the low level at time t ₄ . Since rising at time t _6, the output Q ₁ to a high level output PD of the inverter IV rises at time t ₆ to the high level again, and is kept output Q ₂ is at a high level. Since the external signal Vst rises to the high level at time t6, the signal Ex rises to the high level. According to this, the counters C ₀ to C ₂ and the flip flop FDFF (see also FIG. 1) are reset to their initial state. The initial state of the flip-flop FDFF means an odd field. In this way, the odd field of the CRTC 10 is synchronized with the odd field of the television system 60 at time t ₆ .

According to the reset operation, the horizontal synchronizing signal Hs goes to a high level after one horizontal scanning period H for the time t ₆ (not one time for the horizontal scanning period H for the time t ₆ , but delayed time t ₇ ) (time: t ₈ ). To rise. Output of flip flop DFF ₂ Since the fall at time t ₈ to the low level and outputs Ex also falls to a low level. If the odd or even field of the CRTC 10 is synchronized with the odd or even field of the television system 60, the output Ex remains at a low level as shown in FIG.

As shown in FIG. 7, when the phase difference between Vst and Vs is large, the output Ex rises to high level in synchronization with the signal Vst of the odd field. Thus, the counter and flip flop of CRTC 10 are reset to their initial state at time t ₂₀ .

As shown in FIG. 6, in the phase difference detecting circuit 62, phase detection of the vertical synchronizing signal Vs generated by the display control device 10 and the vertical synchronizing signal Vst generated by the television system 60 is carried out between the vertical synchronizing signal. The comparison is performed while comparing the relationship between the two (the vertical synchronization signal is detected to be odd or even) and the comparison is performed. As a result, the AND gate G ₁₁ takes a logical product of the detection output of the phase detection circuit 62 and the vertical synchronizing signal Vs generated by the display control device 10, thereby synchronizing with the vertical synchronizing signal Vst. Output is obtained. By giving this pulse output to the display control device 10 as an external synchronization signal Ex, the initialization timing of the contents of each counter in the display control device 10 is set to an odd number (even number) on the television system 60 side. Can be periodically synchronized to the vertical synchronization signal of

In addition, the display control apparatus 10 in this case is previously set so that it may operate as a slave by the command in the computer system 100 side, for example.

As described above, the image information St displayed by the display system having an independent synchronization signal system such as the television system 60 and the image information Sc managed by the display control device 10 are maintained while maintaining a constant positional relationship with each other. The display screen can be overlaid.

Referring to the effects obtained by the representative of the invention disclosed in the present application are as follows.

(1) The storage device is accessed by address data formed in accordance with the count contents of the scan counter, and the horizontal sync signal and the vertical sync signal are generated respectively in accordance with the count contents of the scan counter. The count content of the scan counter is initialized to a constant value by an externally provided signal so that a plurality of image information managed by each CRTC are superimposed on one display screen while maintaining a constant positional relationship. Obtained with the effect that it can be displayed.

(2) The storage device is accessed by address data formed in accordance with the count contents of the scan counter, and the horizontal sync signal and the vertical sync signal are generated in accordance with the count contents of the scan counter. The interlaced scanning method while maintaining a constant positional relationship with a plurality of image information each managed by a plurality of CRTCs by externally outputting a signal synchronized with one vertical synchronizing signal, either odd or even The effect that it can display on the display device of superposition is acquired.

(3) The storage device is configured to access the storage device by address data formed in accordance with the count contents of the scan counter, and together with the horizontal synchronization signal and the vertical synchronization signal in an interlaced scanning display system having an independent synchronization signal system. And generating a clock for determining the access timing of the storage device according to the horizontal synchronizing signal, and detecting either the odd or even one vertical synchronizing signal from the vertical synchronizing signal, Therefore, by forcibly initializing the contents of the scanning counter to a constant value, a constant positional relationship is maintained between the image information displayed by a display system having an independent synchronization signal system such as a television system and the image information managed by the CRTC. While overlapping one display The effect that can be obtained.

According to the above (1) to (3), a synergistic effect that a plurality of images can be synthesized and complex or various images can be created simply and at high speed can be obtained.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary. For example, the CRT display may be a liquid crystal display or a plasma display. The interval of the external synchronization signal Ex may be an arbitrary time interval every few frames or more.

In the above description, the case where the invention made mainly by the present inventors is applied to the synchronization technology of the image system of the CRT display device, which is the background of the use, is not limited thereto. For example, the content of the image information is determined. The present invention can also be applied to a synchronization technique in an image system having intellectual processing functions such as rewriting. It can be applied to at least a condition that requires synchronization or alignment.

Claims (10)

Memory means for storing image data, video information to be displayed on a display device, video signal generating means for generating a synchronization signal, the video signal generating means and the memory means, and connected to a plurality of horizontal lines in accordance with a preselected timing An image system having a display control device that accesses the memory means to read the image data on a scanning line, wherein the display control device indicates first data for indicating a first reference value and second reference value. Register means for storing second data, third data for indicating one of internal and external modes, incremented in response to a clock signal, horizontal counter means for generating a count, generated in said horizontal counter means To output a horizontal synchronizing signal when the count coincides with the first data First comparing means, incremented in response to the horizontal synchronizing signal, vertical counter means for generating a count, and outputting a vertical synchronizing signal when the count generated by the vertical counter means coincides with the second data A second comparing means for generating said address generating means for generating an address for accessing said memory means in response to said horizontal and vertical counter means, when said third data indicates said internal mode; The initial value is set according to the coincidence signal between the count generated by the horizontal counter means and the first data, and the vertical counter means determines the count of the count generated by the vertical counter means and the second data. When the initial value is set according to the coincidence signal and the third data indicates the external mode, Horizontal and vertical counter means each has an image system in which the initial value set in accordance with the sync signal in the video unit signal is generated. 3. The method of claim 1, wherein the register means comprises: a first register for storing the first data, a second register for storing the second data, and a third for storing the third data Imaging system with registers. The imaging system of claim 2, wherein the initial value is zero. An image having a memory means for storing image data, and a display system coupled to the memory means, and displaying the image data stored in the memory means on a display device as an image display formed of a plurality of horizontal scanning lines in accordance with a preselected timing. A system, wherein the display system includes at least first and second display control devices, each of the first and second display control devices comprising terminal means for supplying a signal, a first reference value for indicating a first reference value. Register means for storing data of one, second data for representing a second reference value, third data for representing one of internal and external modes, incremented in response to a clock signal, for generating a count Horizontal synchronization means, when the count generated by the horizontal counter means coincides with the first data First comparing means for outputting a call, incremented in response to said horizontal synchronizing signal, vertical counter means for generating a count, and vertical when said count generated in said vertical counter means coincides with said second data Second comparing means for outputting a synchronous signal, address generating means for generating an address for accessing a memory means for storing image data in response to said horizontal and vertical counter means, and said terminal means for said horizontal and vertical counter means. Means for coupling to the said first display control device, said means for supplying a synchronizing signal synchronized with said vertical synchronizing signal to said terminal means in response to said third data indicating said internal mode; And the means of the second display control device is configured to cause the third data to enter the external mode. An image system for setting each of the counts of the horizontal and vertical counter means of the second display control device to an initial value in accordance with the synchronization signal at the terminal means of the first display control device in response to being shown. . 5. The method of claim 4, wherein the register means includes a first register for storing the first data, a second register for storing the second data, and a third for storing the third data. Imaging system with registers. 6. An imaging system according to claim 5, wherein the initial value is zero. An image system having a display device and display control means coupled to the display device, wherein the display control means generates video information to be displayed on the display device, a first horizontal synchronization signal, and a first vertical synchronization signal. And a display control device coupled to the video signal generating means, the display control device comprising: first data for indicating a first reference value, second data for indicating a second reference value, Register means for storing third data for indicating one of the internal and external modes, a horizontal counter means for incrementing in response to a clock signal, for generating a count, said count generated in said horizontal counter means being said first First comparing means for outputting a second horizontal synchronizing signal when coinciding with the data of said second, increasing in response to said horizontal synchronizing signal; And vertical counter means for generating a count, second comparing means for outputting a second vertical synchronizing signal when the count generated in the vertical counter means coincides with the second data, And the first horizontal synchronizing signal and the first vertical synchronizing signal are supplied to the display control device when the data of the third indicates the external mode. 8. The display control apparatus according to claim 7, wherein the display control device generates a first synchronization signal synchronized with the first horizontal synchronization signal and a second synchronization signal synchronized with the first vertical synchronization signal. An image system having a synchronization signal generating means for performing the The image system according to claim 8, wherein said clock signal is said first synchronization signal. 10. The image system according to claim 9, wherein when the third data indicates the external mode, the horizontal and vertical counter means are set to an initial value by supplying the second synchronization signal.