JPH02187790A - Display controller - Google Patents

Abstract

PURPOSE:To output signals to the display device of different performance by providing a display means, outputting a timing signal in synchronization with display speed and display resolution, and reading out a picture signal according to these. CONSTITUTION:A control signal generator 11 housed in a display device 101 outputs the timing signal 21 to a data transmission and output part 25 by making an oscillator 13 a signal source. The signal 21 is synchronized with the display speed and display resolution of an inputted picture. Besides, the inputted picture is displayed on a CRT 34 and stored in a video memory 29 at least one screen according to the control of the signal 21. Hereupon, the control part 25 generates a load signal 16 according to the above-mentioned signal 21 and loads a picture signal from the memory 29. Moreover, picture data is read out by a shift register 12. Besides, the picture data is outputted in a CRT driving part 14 and displayed on the CRT 34. Thus, even when the display speed and display resolution of the device 101 vary, the signal 21 is connected and outputted by synchronizing its timing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device that outputs and displays display data on a display device such as a CRT.

[Prior Art] FIG. 6 is a block diagram showing a schematic configuration of a conventional CRT display control device. In the figure, reference numeral 201 denotes a control signal generation unit which inputs the clock of the oscillator 206 and outputs a horizontal synchronization signal and a vertical synchronization signal for display, a load signal to the shift register 205, a hold signal, etc. 20
2 is a dual-port video memory, which inputs display data in parallel and transfers it to a shift register 205 using a serial signal.
It is output to. Note that the serial signal output from the video memory 202 is data consisting of multiple bits (16 bits) obtained by combining the serial signals output from the plurality of memory elements constituting the video memory 202. is input into parallel human power.

The data transfer control section 204 receives the control signal from the control signal generation section 201 and outputs the address of the video memory 202 and a data transfer request signal to the memory control section 203. In this way, the display data read out from the video memory 202 is loaded pixel by pixel into the shift register 205, and is serially outputted to the CRT drive section 207 in synchronization with the clock from the oscillator 206.

[Problems to be Solved by the Invention] However, in the conventional example described above, the display control section generates horizontal and vertical synchronization signals, and according to these signals image data is transmitted to the CRT drive section 207 for display. Even if you want to display image data on CRT display devices with different speeds, it is impossible to display it on CRTs with different display speeds and resolutions because the horizontal and vertical synchronization signals and pixel clock speeds are constant. there were.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a display control device that can display images even when connected to display devices having different display speeds and resolutions.

[Means for Solving the Problems] In order to achieve the above object, a display control device of the present invention has the following configuration. That is, a display means for inputting and displaying an image signal and outputting a timing signal synchronized with the display speed and display resolution, and a memory for storing at least one screen worth of image data corresponding to the display of the display means. reading means for reading image data from the storage means in response to the timing signal; and output means for serially outputting the image data to the display means in synchronization with the timing signal.

[Operation] In the above configuration, the display means inputs and displays an image signal, and outputs a timing signal synchronized with the display speed and display resolution. In response to this timing signal, the image data is read from the storage means that stores the image data, and the image data is serially outputted to the display means in synchronization with this timing signal.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Display Control Circuit (FIGS. 1 and 2) FIG. 1 is a block configuration diagram showing a schematic configuration of a display device 101 and a display control section 102 according to an embodiment.

In the figure, 11 is a control signal generator, and a display device 101
It generates various timing signals necessary for display scanning in the display device 101 using the oscillator 13 as a reference clock signal source. These various timing signals include, for example, a horizontal synchronizing signal 19 . A vertical synchronization signal 20, and a control signal for the display control unit 102, such as a timing signal 21. Horizontal scanning start signal 22. There is a vertical scanning start signal 23, etc.

Reference numeral 12 denotes a shift register that loads a 16-bit image signal from the video memory 29 in response to a load signal 16 from the data transfer control section 25, and serially transmits image data 24 to the CRT drive section 14 in synchronization with the clock signal 15. It is outputting. A video memory (VRAM) 29 stores image data input in parallel from random ports. This video memory 29 is, for example, a dual port RAM equipped with a random access port and a serial access port. Reference numeral 25 denotes a data transfer control unit whose details are shown in FIG. 12 clock signals 15
．． Load signal 16. A hold signal 17 is output.

Further, 28 is a memory control unit which inputs the data transfer address 27 and the data transfer request signal 26 from the data transfer control unit 25, and inputs the address 31 of the video memory 29, the refresh signal (RAS, CAS) of the video memory 29, and the video memory 29. It outputs 29 shift clock signals, etc.

FIG. 2 is a timing chart showing the signal timing of each part of the display control circuit of FIG. 1.

Vertical scanning start signal 23 at timing T1 in FIG. 2(A)
When rising, the data transfer control unit 25 initializes the data transfer address and sets it to the transfer start address of the first row of the video memory 29.

From then on, after the vertical scanning start signal 23 falls, the data transfer request signal 26 is output in synchronization with the horizontal scanning start signal 22, and the data transfer request signal 26 is output in synchronization with the fall of the data transfer request signal 26. 27 is updated. In this way, image data for one screen is output, and when the vertical scanning start signal 23 rises again at timing T2,
The data transfer start address 27 is again set to the start address of the first row.

FIG. 5 shows the structure of the image data in the video memory 29 at this time. The maximum capacity of video memory 29 is 1
024x1024 dots, 50 is 640x400
Shows the display data area of the dot, 51 is 729x540
A display data area 52 indicates a display data area of 1024x768 dots. And now for example 640X
When displaying 400 dots, display data is stored according to the area gso, and each time the horizontal scanning start signal 22 is input, the address in the X direction of the video memory 29 is changed to 5.
The position indicated by 3 is changed to "0" at the beginning of the line, and the address in the X direction is incremented by +1.

Reference numeral 33 in FIG. 2(A) shows an enlarged view of the time of one cycle of the data transfer request signal 26, and here shows the time from the third line to the fourth line.

The memory control unit 28 controls the video memory 2 in synchronization with the timing signal 21 while the data transfer request signal 26 is at a low level.
It outputs 9 serial clock signals. The video memory 29 outputs one pixel of image data 18 from the serial port to the shift register 12 in synchronization with this serial clock. This image data 18. (16 bits), the data transfer control unit 25 outputs the load signal 1.
6 is output, and the fall of this load signal 16 causes the shift register 12 to receive 16-bit image data 1.
8 is loaded.

This operation is repeated for one line. For example, if the display area of the CRT 34 is 640 x 400 dots, 16-bit pixels are transferred to the 400-pixel CRT drive unit 14, and when the transfer of the image data 18 for one line is completed, A horizontal scanning start signal 22 is input from the control signal generator 11, and a data transfer request signal 26 rises. Note that the hold signal 17 is sent to the data transfer control unit 2 in synchronization with the data transfer request signal 26.
5 to the shift register 12, and while this hold signal 27 is output, the shift register 1
2 image output operation is prohibited.

Figure 2 (B) shows the image data (a) and (b) of Figure 2 (A).
) and (c) are further enlarged views showing the timing of output from the shift register 12. After one pixel (16 bits) of image data is latched into the shift register 12 due to the fall of the load signal 16, Data transfer control unit 2
This shows the timing at which 16-bit one pixel data is output in synchronization with the shift clock 15 from 5.

In this way, in the circuit of this embodiment, the data transfer control section 25 generates the data transfer request signal 26 every time the CRT 34 performs horizontal scanning. This is video memory 29
If the size of one line is different from the size of one line displayed on the display device 101, for example, the video memory 29 is 1024×1024 pixels as shown in FIG.
When the display device is 640×400 pixels, the display device 10
The last part of one row of 1 and the first part of the next row do not have consecutive addresses on the video memory 29, so these rows can be accessed continuously.

For example, in a display device 101 that displays 640×400 pixels, the horizontal scanning start signal 22 is generated once every time the data transfer request signal 26 is generated the number of times (40 times) corresponding to 640 pixels, and After the scanning start signal 22 has been generated 400 times, the vertical scanning start signal 23 is generated. Similarly, in a display device that displays 720 x 540 pixels,
The horizontal scanning start signal 22 is generated once every time the data transfer request signal 26 corresponding to 720 pixels (45 times) is generated, and every time the horizontal scanning start signal 22 is generated 540 times,
The vertical scanning start signal 23 is generated once.

[Description of data transfer control unit 25 (Fig. 3)] Fig. 3 (
A) and FIG. 3(B) show the data transfer control unit 25 of the embodiment.
This is a diagram showing a schematic configuration of , and the same parts as those in the above-described drawings are designated by the same numbers.

FIG. 3A shows a phase comparison between a signal obtained by dividing the shift clock 15 generated by a VCO (voltage controlled oscillator) 41 by 16 and a timing signal 21 from the control signal generator 11. Then, the phase shift is transmitted to the charge pump 44, and a voltage for controlling the frequency is applied to the VCO 41 through an LPF (low pass filter) 43.
It constitutes a LL (phase lock loop).

The address counter 46 outputs a data transfer address 27, is reset at the rise of the vertical scan start signal 23, and is counted up at the fall of the horizontal scan start signal 22 when the vertical scan start signal 23 is at a low level.

The clock of this address counter 46 (output of the gate 49) is sent to the memory control unit 2 as a data transfer request signal 26.
8 is output. The load signal 16 is output from the gate 47, and is output in synchronization with the timing signal 21 when both the horizontal scan start signal 22 and the vertical scan start signal 23 are at low level.

FIG. 3(B) is a diagram showing the configuration of the data transfer control unit 28 when the frequency of the shift clock 15 is relatively low.
Here, there is no PLL configuration, and the shift clock 1
5, the output clock 32 of the oscillator 13 transmitted from the display device 101 to the display control unit 102 is used.

As explained above, the display control unit 102 transfers image data to the display device 101 according to control signals from the display device 101.
Since the image data is sent to the 01 side, the image data can be output and displayed on display devices 101 that have different display speeds with different synchronizing signal frequencies or timings. Furthermore, for display devices 101 with different display resolutions, that is, different numbers of display pixels,
It becomes possible to connect and display using the same display control unit without any changes.

[Other Embodiments (Figure 4)] When interlaced scanning is performed, a signal indicating whether it is an even field (only even rows are scanned) or an odd field (only odd fields are scanned) is used. can be set and reflected in the data transfer address 27. For this reason, field information can be transmitted to the display control unit 102 by only slightly changing the vertical scanning start signal 23 and the horizontal scanning start signal 22, without increasing the number of signals. For example, as shown in FIG. 4, when the vertical scanning start signal 23 is at a high level, if there is no horizontal scanning start signal 22, it may be an odd field, and if the horizontal scanning start signal 22 is present, it may be an even field. Further, the horizontal scanning start signal 22 and the vertical scanning start signal 23 are made into one signal as a decoded signal and sent from the display device 101 to the display control unit 102, and the display control unit 102 separates them into horizontal and vertical components and uses them. Another possible method is to do so.

As described above, according to this embodiment, the same display control unit can connect and display on display devices with different display speeds.

Further, there is an effect that it becomes possible to connect and display on display devices having different display resolutions.

[Effects of the Invention] As explained above, according to the present invention, there is an effect that display can be performed even when display devices having different display speeds and resolutions are connected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of the display device and display control unit of the embodiment, FIGS. 2(A) and (B) are timing charts for explaining the operation of the embodiment, and FIG. 3(A) ( B) is a block diagram showing the schematic configuration of the data transfer control unit, FIG. 4 is a timing chart showing field discrimination in the interlaced system, FIG. 5 is a diagram explaining the video memory area and display area, and FIG. 6 is the conventional FIG. 2 is a block diagram showing a schematic configuration of an image processing device according to the present invention. In the figure, 11... Control signal generator, 12... Shift register, 13... Oscillator, 14... CRT drive section, 15... Shift clock, 16... Load signal, 17... - Hold signal, 21... Timing signal, 22... Horizontal scanning start signal, 23... Vertical scanning start signal, 25... Data transfer control section, 26... Data TNSO request signal, 27. ...Data transfer address, 28...Memory control unit, 29...Video memory,
34...CRT. 1...Display device, O2...Display control unit

Claims (2)

[Claims] (1) A display means for inputting and displaying an image signal and outputting a timing signal synchronized with the display speed and display resolution, and storing at least one screen worth of image data corresponding to the display of the display means. It is characterized by comprising a storage means, a reading means for reading image data from the storage means in accordance with the timing signal, and an output means for serially outputting the image data to the display means in synchronization with the timing signal. display control device. (2) The timing signal includes horizontal and vertical scanning signals and a pixel clock signal, and the output means stores the image data in a shift register at every predetermined period of the pixel clock, and synchronizes with the pixel clock from the shift register. 2. The display control device according to claim 1, wherein the image data is serially outputted.