JPS61161877A - Video signal processing device - Google Patents

Abstract

PURPOSE:To display plural pictures in division on the displaying screen by writing the primary and secondary digital video signals in alternate addresses of the line memory to read them alternately and display. CONSTITUTION:The primary-color signals supplied to input terminals 1-3 and 4-6 are supplied alternately to an A/D converting circuit 8 by the switching of switches 7a-7c, and is written in the line memory 9 by the write address signal given through a memory control circuit 70. In the mean time, a write- address counter 11 is sequentially generating the address signals. The data correspondent to the picture A is written in the addresses of the line memory by the address signals in the even number of order and that correspondent to the picture B is by ones in the odd number of order. The data written in the line memory 9 is read out by the read-address signals which the memory control circuit 10 controls to supply, and is outputted through a D/A converting circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing device suitable for use when displaying a plurality of screens on a single display.

[Conventional technology]

Conventional video signals are rarely synchronized, and therefore field memory or frame memory is required to display two screens on a cathode ray tube.

[Problem that the invention seeks to solve]

However, if such a field memory or frame memory is used, the configuration becomes complicated and the cost becomes expensive. Furthermore, in order to arrange two nine screens side by side, the memory structure becomes large-scale.

The present invention has been made in view of the above, and an object thereof is to provide an inexpensive video signal processing device that can display a plurality of screens on the same display with a simple configuration.

[Means for solving problems]

The video signal processing device according to the present invention provides a synchronized first
and the second analog video signal to an A/D conversion circuit (s)
(20) In addition to supplying the A/D conversion circuit to (21), a switch means (7) is provided before or after this A/D conversion circuit.
The first and second digital video signals obtained by the D conversion circuit are written to alternate addresses of the line memo (January 9), and in a predetermined period of one horizontal period, the first digital video signal is written from the line memory (9). The video signal is read out, and in periods other than the predetermined period of one horizontal period, the line memory (9)
The second digital video signal is read out from the D/A converter, and the read first and second digital video signals are
The signal is supplied to the display means via a conversion circuit (15), and the screen of the first and second analog video signals is divided and displayed on the display surface of the display means.

[Effect]

Synchronized first and second analog video signals are supplied to the A/D conversion circuit (8) via the switch means (7) to obtain first and second digital video signals, and the first and second analog video signals are The second digital video signal is supplied to the line memo (January 9), or the synchronized first and second analog video signals are supplied to the A/D conversion circuits (20) and (21). A second digital video signal is obtained and the first and second digitally processed signals are supplied to the line memory (9) via the switch means (7). In the line memo (January 9), the supplied first and second digital video signals are written to alternate addresses, that is, even address signals and odd address addresses. Read out the digital video signal of 1,
During a period other than the above-mentioned predetermined period of one horizontal period, for example, in the second half'
reads the second digital video signal, the read first and second digital video signals are supplied to the display means via the D/A conversion circuit (15), and the first and second digital video signals are displayed on the display surface of the display means. A screen based on the second analog video signal is divided and displayed.

〔Example〕

Hereinafter, various embodiments of the present invention will be described in detail based on FIGS. 1 to 5.

FIG. 1 shows a first embodiment of the present invention. In the same figure, (1), 12), and (3) are, for example, three primary color signals (R, G, B) constituting the A screen. Input terminals (4, (6), (6
) are, for example, three primary color signals (R.

These are input terminals to which G, B) (analog video signals) are respectively supplied. It is assumed that the primary color signals supplied to the input terminals (1) to (3) and the primary color signals supplied to the input terminals (4 to (6)) are synchronized. Considerable examples include text signals and video signals in teletext broadcasting, applied signals and output signals in a VTR with a cinerator lock, etc. (7) is a switch circuit as an analog multiplexer, and includes three switches (7a).
, (7b) and (7c), and has a switch (7a
) is connected to the input terminal (1), the contact a is connected to the input terminal (4), the contact a of the switch (7b) is connected to the input terminal (2), and the contact ), the contact a of the switch (7c) is connected to the input terminal (3), and the contact S is connected to the input terminal (6).

(8) is an A/
The D conversion circuit (9) is a line memory provided on the output side of the A/D conversion circuit (8). αl is line memory (
(11) is a write address counter, (12) is a read address counter, and is an address counter (11).

The address signal from (12) is supplied to the line memory (9) via the memory control circuit αe. (13) is a clock input terminal to which a clock signal is supplied,
The clock signal from this clock input terminal (13) is supplied to the address counters (11) and (12), and is also supplied to the D/A converter circuit (8) and the D/A provided on the output side of the line memory (9). It is supplied to a conversion circuit (15). The clock signal frequency is divided by 172 by the clock signal frequency divider (14) and then supplied to the switch circuit (7) as a switching signal. Switches (7a) to (7c) of switch circuit (7)
) is on the contact a side, the data of the A screen is written to the even address address of the line memory (January 9), and when the contact is on the contact side, the data of the 8th screen is written to the odd address address of the line memory (9). written. In addition, the D/A conversion circuit (
Output terminal (16) for obtaining three primary color signals from the output side of 15).

(17) and (18) are taken out.

Now, when the switches (7a) to (7c) are on the contact a side, the primary color signals from the input terminals (1) to (3) are supplied to the A/D conversion circuit (8), which converts them from the analog signals. converted into a digital signal. This converted digital signal is supplied to the line memory (9), and the memory control circuit Q
Data is written to even address addresses based on the even number address signals from the write address counter (11) via the write address counter (11).

On the other hand, when the switches (7a) to (7c) are on the contact side, the primary color signals from the input terminals (4) to (6) are supplied to the A/D conversion circuit (8), which converts them from the analog signals. converted into a digital signal. This converted digital signal is supplied to the line memory (9), and the memory control circuit (
write address counter (1
1) is written to an odd address address based on the odd address signal from 1).

The write address counter (11) sequentially generates address signals as shown by the broken lines in FIG. The odd-numbered data of the address signal corresponding to eight screens is written to the odd-numbered address of the line memory (9). Figure 3 shows the line memory written in this way (9)
This shows part of the content.

The data written in the line memory (9) is sequentially read out based on address signals from the read address counter (12) supplied via the memory control circuit Ql. The read address counter (12) reads data written in even address addresses in the first half of one horizontal period, as shown by the solid line a in FIG.
The one that does not have a triangular shape is A, which determines the size of the eight screens. That is, the reason why there is a slight margin between the start and end of the address in the address counter (12) is to prevent blanking from occurring on the screen.

The data read from the line memory (9) is supplied to the D/A conversion circuit (15), where the digital signal is converted into an analog signal, and output terminals (16) to (18)
The signal is extracted as three primary color signals.

This signal is supplied to a display means (not shown), and the A screen and 8 screens are divided and displayed on the display screen as schematically shown in FIG. 4.

In this way, in this embodiment, two screens can be displayed side by side on the same display screen.

FIG. 5 shows a second embodiment of the present invention. In this figure, parts corresponding to those in FIG.

While the first embodiment described above supplies the input primary color signals to the A/D conversion circuit (8) via the switch circuit (η), this embodiment attempts to change this order. Therefore, A/D conversion circuits (20), (21
), and input terminals (1) to (3) are connected to an A/D conversion circuit (
20), and connect the input terminals (4) to (6) to the A
Connect to the input side of the /D conversion circuit (21).

Then, the output side of the A/D conversion circuit (20) is connected to a switch (
The output side of the A/D conversion circuit (21) is connected to the contact a side of the switches (7a) to (7C). Therefore, a switch circuit to which a digital signal is supplied (in this case, it functions as a digital multiplexer), and the other configuration is the same as that in FIG.

□The circuit operation of FIG. 5 is also substantially the same as the circuit operation of FIG. 1, and therefore the explanation thereof will be omitted here.

In addition, in each of the above-mentioned embodiments, by changing the speed of the read address counter, it is possible to obtain a high-quality double-speed 2m1 surface.Also, by fixing the multiplexer to one of the contact points, the address of the read address counter can be easily changed. It is also possible to double the normal speed by forming two triangular shapes.

At this time, only one screen is displayed.

〔Effect of the invention〕

As described above, according to the present invention, the first and second digital video signals are written to alternate addresses of the line memory, the first digital video signal is read out from the line memory during a predetermined period of one horizontal period, and the first digital video signal is written to alternate addresses of the line memory. During periods other than the above-mentioned predetermined period, the second digital video signal is read from the line memory, converted from D/A and supplied to the display means, so that a plurality of screens can be divided and displayed on the display surface. . Since such a function can be performed using a line memory, the configuration can be simplified and the cost can be lower than when using a conventional field memory or frame memory.

[Brief explanation of the drawing]

Figure 1 is the fruit of this invention! ! Block diagram showing an example, 2nd
4 to 4 are diagrams for explaining the operation of FIG. 1, and FIG. 5 is a block diagram showing another embodiment of the present invention. (7) is a switch circuit, (8), (20),
(21) is the A/D conversion circuit, (9) is the line memory, α
l is a memory control circuit, (11) is a write address counter, (12) is a read address counter, (15)
is a D/A conversion circuit. Figure 3 Figure 4

Claims (1)

[Claims] Synchronized first and second analog video signals are A/D
A switch means is provided before or after the A/D conversion circuit to supply the signal to the conversion circuit, and writes the first and second digital video signals obtained by the A/D conversion circuit to alternate addresses of the line memory; During a predetermined period of one horizontal period, the first digital video signal is read from the line memory, and during a period other than the predetermined period of one horizontal period, the second digital video signal is read from the line memory. The first and second digital video signals obtained are supplied to a display means through a D/A conversion circuit, and a screen formed by the first and second analog video signals is divided on a display surface of the display means. A video signal processing device characterized in that it displays a video signal.