JPH05268539A - Picture display device - Google Patents

Abstract

PURPOSE:To provide the picture display device able to solve a problem of interleaved data or occurrence of after-image even when a fetched video signal is a non-interlace display signal and a problem of non-display of a picture entirely in the case of reduction display. CONSTITUTION:A video signal and a signal V corresponding to a vertical period of the video signal are at a different level at 1st and 2nd fields in the case of interlace display, the video signal in the interlace display is in phase with a field identification signal FI based on the field identification signal FI fixed to one level in the case of the non-interlace display, a control signal NFI whose level is inverted for a vertical period of the video signal is generated when the video signal is in the non-interlace display and a write address of a memory is generated based on the control signal NFI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention takes in, for example, an NTSC video signal, writes it in a memory, then reads it out, performs various processing such as composition with other screens and reduced display, and displays an image by double scanning. To improve the image display device.

[0002]

2. Description of the Related Art As is well known, there is a high captain terminal as one of the devices used by connecting to an ISDN line.
Some of the high captain terminals have a function of displaying the image sent from the outside, in addition to displaying the image of the data sent through the ISDN line. This is for converting video signals, RGB signals, etc. supplied from the outside into A / D (analog /
Digital) conversion and write it once in the memory and read it out, and after performing various digital processing such as composition with other planes and reduced display, D / A (digital / analog) conversion and CRT (cathode ray tube) etc. The image is displayed in.

In this case, the above-mentioned video signal is an NTSC system signal (line frequency is about 15.75 kHz, field frequency is about 60 Hz), and the image display of the high captain terminal is so-called double scan display (line frequency is about 31.5kHz, field frequency is about 60Hz)
Is. For this reason, in the high captain terminal, as shown in FIG. 3, the first field and the second field of the video signal of the NTSC system are added together and displayed on the screen.

FIG. 4 shows the structure of such a conventional image display apparatus from the capturing of a video signal to the writing and reading of the signal into a memory. That is, the video signal supplied to the input terminal 11 is converted into three types of color signals R, G, B by the video-RGB conversion circuit 12 (in the case of RGB input, the video-RGB conversion circuit 12 is unnecessary. ). These color signals R, G, B are, for example, 8 in the A / D conversion circuit 13.
Each bit is sampled into digital data,
It is written in the memories 14, 15 and 16.

When writing data in the memories 14, 15 and 16, address information indicating the writing destination is required. In this case, the horizontal address is the horizontal counter 1.
The vertical address obtained from 7 is the vertical counter 18
Obtained from An FI (field index) signal for identifying the first field and the second field is obtained from the sync separation circuit 19. Further, from the sync separation circuit 19, an H (horizontal sync) signal and a V (vertical sync) signal are also obtained, which are the horizontal and vertical counters 1.
It is used as a reset signal for 7 and 18 and a clock signal. A sampling clock is supplied as a clock signal to the horizontal counter 17 through the input terminal 20.

Then, the horizontal address, vertical address and FI signal are supplied to the address control circuit 21 to generate a write address. A read address generated by a read control circuit (not shown) is supplied to the address control circuit 21 via an input terminal 22. Then, the write address and the read address are sent to the memories 14, 15, and 16 in a time division manner, so that the digitized color signals R, G, and
Writing to and reading from the B memories 14, 15, and 16 are performed.

Here, the NTSC system video signal is generally interlaced display, and in this case, the FI for identifying the first field and the second field.
The signal is obtained. However, some captain terminals such as teletext receivers and analog telephone lines output non-interlaced video signals in order to prevent vertical fluctuations of displayed characters and the like. Some still cameras output a non-interlaced display video signal in order to reduce the amount of data. And for the video signal of non-interlaced display,
Since there is no concept of field, the FI signal is usually fixed at either H level or L level. For this reason, only half of the data in the case of interlaced display is written in the memory, and when the image is displayed by double scanning, it is displayed in a thinned state. In addition, when a video signal for non-interlaced display is captured after a video signal for interlaced display is captured, there is also an inconvenience that an afterimage phenomenon in which half of the previous data remains is generated.

Further, the high captain is provided with a function of reducing the captured video signal to 1/2 in the vertical and horizontal directions and displaying the image. The reduction in the vertical direction can be realized by displaying only one of the first field and the second field. At this time, in the case of a non-interlaced display video signal, the FI signal is H or L.
Since the level is fixed, the write address and the read address do not match (for example, when writing is performed in the memory area of the first field and reading is performed in the memory area of the second field, and vice versa). In the case of), there is a problem that the image is not displayed at all.

[0009]

As described above, in the conventional image display device which takes in a video signal from the outside, digitizes it, once writes it in the memory, then reads it, performs various data processing, and displays an image by double scanning. In the case of non-interlaced display of a video signal, there are problems that data is thinned out or an afterimage phenomenon occurs, and that in the case of reduced display, no image is displayed at all.

Therefore, the present invention has been made in consideration of the above-mentioned circumstances. Even when the captured video signal is a non-interlaced display, a problem that data is thinned or an afterimage phenomenon occurs, or a reduced display is performed. It is an object of the present invention to provide an extremely good image display device capable of solving the problem that no image is displayed at all.

[0011]

SUMMARY OF THE INVENTION An image display device according to the present invention is intended for displaying a digitized video signal in a memory, then reading the digitized video signal, and performing predetermined data processing to display the image. When the signal corresponding to the vertical cycle of the video signal and the video signal are interlaced display, the first field and the second field have different levels, and when the video signal is non-interlaced display, they are fixed at one level. Based on the field identification signal, when the video signal is in interlaced display, it has the same phase as the field identification signal, and when the video signal is in non-interlaced display, a control signal whose level is inverted in the vertical cycle of the video signal is generated. The memory write address is generated based on the control signal.

[0012]

According to the above configuration, even when the video signal is non-interlaced display, the memory write address is generated based on the control signal whose level is inverted in the vertical cycle of the video signal. The problem that the image is thinned out or the afterimage phenomenon occurs, and the problem that the image is not displayed at all in the case of the reduced display is solved, and a good image can be displayed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, reference numerals 23 and 24
Are input terminals to which the FI signal and the V signal output from the sync separation circuit 19 are supplied. FI
The signal is a signal for identifying the field, and the level is changed corresponding to the first field and the second field at the time of interlacing as shown in FIG. 2A, and at the time of non-interlacing as shown in FIG. 2B. As shown, it is fixed at the H or L level. Also, the V signal is
It is a vertical synchronizing signal and a pulse signal with a vertical cycle.

In FIG. 1, the D-FF (D type-flip-flop) circuits 25 and 26 constitute a 2-bit shift register which receives the V signal as a clock and the FI signal as an input. Therefore, the D-FF circuits 25 and 26
Q output of H, L or L, when interlaced
It becomes H and becomes L, L or H, H at the time of non-interlace. That is, the EX OR (exclusive OR) circuit 27 to which each Q output of the D-FF circuits 25 and 26 is input.
The output of is always H level during interlace,
It is always at the L level during non-interlace.

Further, in FIG. 1, a switch circuit 28 is provided.
Operates so that the B input is selected when the select terminal S is at the H level and the A input is selected when the select terminal S is at the L level. Then, the inverted output Q of the D-FF circuit 29 is supplied to the A input of the switch circuit 28, and B
The FI signal is supplied to the input. Therefore, DF
The NFI signal which is the Q output of the F circuit 29 becomes a signal having the same phase as the FI signal at the time of interlacing, and is taken out from the output terminal 30 as a toggle signal which repeats H and L in the vertical cycle at the time of non-interlacing.

The NFI signal is supplied to the address control circuit 21 instead of the FI signal so as to generate a write address, so that the video signal taken from the outside is either interlaced display or non-interlaced display. However, the data for two fields is always written in the memories 14, 15 and 16, and the data is not thinned out even when the image is displayed by double scanning. Also, when the video signal is switched from interlaced display to non-interlaced display,
The afterimage phenomenon does not occur. Further, even in the case of reduced display, image display is always performed. The present invention is not limited to the above embodiment,
In addition, various modifications can be made without departing from the scope of the invention.

[0017]

As described in detail above, according to the present invention,
A very good image display device capable of solving the problem that data is thinned out or the afterimage phenomenon occurs even when the captured video signal is non-interlaced display, and the problem that no image is displayed at reduced display. Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image display device according to the present invention.

FIG. 2 is a diagram for explaining a difference in FI signal between interlaced and non-interlaced.

FIG. 3 is a diagram shown for explaining the relationship between rasters in the NTSC system and double scan display.

FIG. 4 is a block configuration diagram showing a conventional image display device.

[Explanation of symbols]

11 ... Input terminal, 12 ... Video-RGB conversion circuit, 13
... A / D conversion circuit, 14 to 16 ... Memory, 17 ... Horizontal counter, 18 ... Vertical counter, 19 ... Sync separation circuit, 2
0 ... Input terminal, 21 ... Address control circuit, 22-24 ...
Input terminals, 25, 26 ... D-FF circuit, 27 ... EX OR circuit, 28 ... Switch circuit, 29 ... D-FF circuit, 30
… Output terminal.

Claims (1)

[Claims] 1. An image display device for temporarily writing a digitized video signal into a memory, reading the digitized video signal, performing predetermined data processing to display an image, and a signal corresponding to a vertical cycle of the video signal and the video signal. In the interlaced display, the first field and the second field have different levels, and in the non-interlaced display, the video signal is interlaced based on the field identification signal fixed at one level. In the case of, the control signal has the same phase as the field identification signal, and when the video signal is a non-interlaced display, a control signal whose level is inverted in the vertical cycle of the video signal is generated, and based on this control signal, a write address of the memory Image display device characterized by being configured to generate Place