JPS6042551Y2 - data storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data storage device, and more particularly to a device for storing input information transmitted at regular intervals for a fixed period of time.

For example, the present invention relates to a data storage device suitable for a video receiver that stores image information transmitted using the vertical retrace interval of teletext broadcasting.

BACKGROUND ART Normally, in a data storage device, one piece of data is composed of a plurality of bits, and input/output operations can be easily performed by specifying a corresponding address for each piece of data.

However, if the input information exceeds one piece of data, or if it is insufficient, it is difficult to process with conventional data storage devices.

For example, such problems arise when storing H signals that are multiplexed during the retrace period of teletext radio waves and displaying them on a cathode ray tube of a video receiver.

Here, the H signal refers to a signal for horizontal scrolling display of one line that moves horizontally at a predetermined speed on the cathode ray tube surface.

In addition to this, there are C signals (signals for full fixed display) and S signals (signals for super fixed display) as teletext broadcasts, but these are 8 bits per data, and 1
Since the data is transmitted during the vertical retrace period without any irregular numbers, it can be processed by a conventional data storage device.

The H signal is sent every 12 fields using an empty vertical retrace period during which no C signal or S signal is transmitted.

One field means one screen, and the signal of one field includes a video signal for scanning one screen and one vertical blanking period.

The H signal transmitted every 12 fields is transmitted through 18 (vertical) x 12 (horizontal) 216 pits.

The transmission system in which the H signal is transmitted every 12 fields and has a horizontal 12-bit structure is closely related to the horizontal flow of characters on the surface of the cathode ray tube.

In other words, since each field is scanned vertically one column (18 bits in the vertical direction of the H signal) and projected on the screen, in order to transmit every 12 fields, it is necessary to transmit all 12 columns. .

The transmitted H signal is temporarily stored in a buffer memory in a data storage device consisting of 18 (114) x 12 (horizontal) bits.

However, the data processing of the central processing unit (CPU) is usually 8
Since processing is done in units of bits, if each data in the data storage device is processed in units of 8 bits, the number of horizontal bits will be insufficient, and if characters are displayed as is, the characters in the blank areas will line up on the CRT screen. This is extremely inconvenient.

DISCLOSURE OF THE INVENTION The present invention provides a data storage device that allows data to be processed in units of data even when input information does not match the number of bits constituting each data unit. The purpose is to

To this end, the configuration of the present invention includes a first memory that stores an AXB bit configuration for one transmission unit (A vertically and B horizontally);
A second memory is provided in which information stored in the first memory is transferred in response to a control signal given from a control circuit, and is read out in an input/output unit having an N-bit configuration by accumulating the information,
The first memory is divided into eight areas equal to B/R at the time of reading so that the greatest common divisor (R bits) of the horizontal bit number B and the output unit bit number N is read out sequentially in the vertical direction as one unit. The second memory is configured to have T independent memory areas equal to N/R of each (AXR) bit configuration, and during the above transfer, R bits are transferred from the first memory as one unit. The stored data is sequentially read in the vertical direction and transferred in association with each divided area of the first memory and each independent memory area of the second memory, and when reading accumulated data from the second memory, the addresses of each of the T independent areas are It is provided with a central processing unit that generates a control signal that makes it possible to read out the output unit of the second memory in N bits by specifying the same at the same time.

This allows the present invention to write one line of characters into memory, transfer them, and then display them while horizontally scrolling them evenly.

As a result, the present invention can not only display input information in a fixed manner over the entire screen or in a super fixed manner, but also display it in horizontal scrolling with a simple configuration and number of elements.

The best form for implementing ideas Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram schematically showing a signal format in television multiplex teletext broadcasting.

Figure 1a shows a pattern line in C or S display that is sent after transmission of a control line (not shown).
The figure shows the H display line for H display.
The signal contains 12 columns of one character divided vertically into one example (18 bits), and is composed of 216 bits.

FIG. 2 is a diagram schematically showing an embodiment of the present invention applied to a television multiplex teletext receiver.

In the figure, when the pattern signal shown in FIG. 1A is input to the television receiver, the pattern signal is temporarily stored in the horizontal scanning signal buffer memory 10.

Since the device of this embodiment is an 8-bit machine that processes data in units of 8 bits, the central processing unit (CPU)
14, the data (pattern signal) stored in the buffer memory is sequentially written into the pattern memory 16 in 8-bit units using a conventionally known method.

On the other hand, in the H display mode, it is inappropriate to write the H signal to the pattern memory 16 in units of 8 bits because the signal has the above-described form.

In short, when processing is performed in units of 8 bits, blank areas of 4 bits inevitably occur periodically on the display screen when displaying characters.

Now, FIG. 2 shows a vertical scanning signal pattern memory constituting the present invention, which will be explained.

When the signal shown in FIG.
. . . In the direction indicated by al2, addresses are sequentially specified, written, and temporarily stored.

The buffer memory is 18 in the vertical direction as shown in the figure.
Three storage areas of 4 bits in the horizontal direction (B?C9
D).

The value 4 for 4 bits is the greatest common divisor of the number of horizontal bits of input information, 12, and the number of bits processed per data by the CPU, in this case 8.

The data written in the buffer memory 12 in this way is transferred to the pattern memory 12 before the next H signal is transmitted.
Must be transferred to 6.

In this case, since the H signal is transmitted every 12 fields, it is sufficient to complete the transfer during that period.

Transfer is performed in units of 4 bits.

In the embodiment, one field is stored in the buffer memory 12 for every four fields.
Transfer the segment and transfer all 3 segments with 12 fields.

Transfer within one section is 4 bits per scanning beam line in a certain field, B1...
This is performed by shifting in the vertical direction such as B18 and scanning 18 times.

In such a case, conventionally known techniques require the use of a 4-bit machine for the pattern memory 16, but the present invention allows the use of an 8-bit machine.

That is, in the present invention, the pattern memory 16 is configured with an appropriate number of mutually independent memory areas, and a write address is specified when writing an H signal to the pattern memory 16 using a conventionally known method. The above-mentioned problem is distantly solved by supplying a chip select signal to the memory device which specifies which memory area the divided memory area in the buffer memory 12 corresponds to and to which data is written.

Next, the apparatus of this embodiment will be further explained with reference to FIGS. 3 and 4.

FIG. 3 is a diagram showing in detail a part of the device shown in FIG. This is the number obtained by dividing the number of processing bits (8) by the number of read bits (4) of the buffer memory 12, that is, two.

FIG. 4 is an explanatory diagram showing an example of write address designation when transferring an H signal from the buffer memory 12 to the pattern memory 16.

Now, as mentioned above, in the H display mode, in a certain field (this is called the first field), the first 216 bits of data (this is (216) 1
) are transmitted and written into the buffer memory 12 in the direction of al, . . . , a12 (see FIG. 1).

In this embodiment, the 216-bit data transmitted in each transfer field is written into the pattern memory 16 as shown in FIG.

In other words, for example, the 4 bits indicated by Dl of the transmitted in the first field (this is set as (DI) 1) and 1
Of the data transmitted in the first field after two fields, 4 bits (Bl) 13 indicated by B1 are stored as the upper 4 bits (upper bit memory 18) and lower 4 bits at the same location in the pattern memory 16, respectively. Write to the bit (lower bit memory 20).

The data written in the pattern memory 16 is read out in relation to the scanning beam position using a conventionally known method.
For example, the X address at the start of reading is updated by 1 bit each time for each field, and displayed in horizontal scroll.

In other words, (Bl) 1 of the H signal is stored in the upper bit pattern memory (shaded area in Figure 4) 18
Write (CI) 1 to the address (1, 1) of the lower bit pattern memory 20, that is, the address where the X address is 1 and the Y address is 1, and (DI) 1 to the upper bit. Write to address (2, 1) of pattern memory 18.

The actual transfer order of the H signal is (Bl)1 as described above.
......, (818) After 1 is transferred, (C
I) 1, ......, (C18') 1 is transferred, then (DI) 1, ...... (Dl8)
1 is transferred.

Next, the structure and operation of the embodiment shown in FIG. 3 will be explained in more detail.

In the figure, pattern memory 16 includes memory area 18.
The memory area 18 is for storing the upper 4 bits of the 8-bit configuration data, while the memory area 2o is for storing the lower 4 bits.

The memory area 18 is connected to the upper bit data bus of the buffer memory 10.12 via the upper bit data bus connected to the CPU 14, while the memory area 2
0 is likewise connected to the lower bit data bus of the buffer memory 10.20.

Further, an address bus is connected to each memory area 18, 20, and an addressing signal from the CPU 14 is applied thereto.

Further, a write pulse signal, a chip select signal, and an 8-bit mode signal from the CPU 14 are applied.

In this embodiment, when a signal is transmitted to the television receiver, it is first determined whether it is in the H display mode or not. If it is not in the H display mode, the 8-bit mode signal becomes low and all memory areas can be used. state, and both memory areas 18 and 20 are input/output operated simultaneously based on the write pulse signal.

On the other hand, if the H display mode is identified, the 8-bit mode signal goes high.

The chip select signal is a rectangular pulse that repeats rising and falling in a four-field period, and the write pulse signal is synchronized with this.

Therefore, when the CPU 14 issues a write pulse signal and enters the transfer mode, a chip select signal for transferring the data stored in the buffer memory 12 to a predetermined memory area of the pattern memory 16 is simultaneously issued.

In the H display mode, the 8-bit mode signal is in a high state.

When the chip select signal is low, the output of the AND circuit 24 connected to the lower bit memory area 20 becomes low, while the output of the AND circuit 22 connected to the upper bit memory area 18 is connected to the inverter 26. Since the chip select signal is applied through the circuit 22, the output of the circuit 22 becomes high.

Therefore, in the H display mode, when a write pulse is applied from the CPU 14, the upper bit memory area 18 or the lower bit memory area 20 is selected, and at the same time the CPU
14 specifies a predetermined address in the memory area 20, and writes the data stored in the buffer memory 12 in units of 4 bits.

In the above embodiment, when data consisting of 216 bits is transmitted every 12 fields, it is temporarily stored in the buffer memory on the receiving side, and data is stored in the pattern memory 1 every 4 fields.
An example of transferring 4 bits at a time to 6 is shown.

In addition, one character in TV multiplex teletext is 18 bits high x 16 bits wide, and in H signal, 37 bits are divided into every 12 fields.
4, 216 bits are transmitted, and two characters are sent in three transmissions.

Of course, the present invention can be applied to other applications than TV multiplex teletext receivers.

Conventionally, various devices have been designed by taking into consideration how many bits the data storage device used therein is, that is, how many bits are input/output in units.

However, as with the above-mentioned TV multiplex teletext broadcasting, there is a restriction imposed on data processing on the data transmission side or receiver that the data unit must have a bit structure that would result in fractions using normal data processing methods. is possible.

According to the present invention, even if there are such restrictions, various devices can be designed flexibly, so it is extremely useful.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a signal format in television multiplex teletext broadcasting. FIG. 2 is a schematic diagram showing an embodiment of the present invention. 3 and 4 are partial schematic diagrams showing in more detail a part of the embodiment apparatus shown in FIG. 2. FIG. 10...Horizontal scanning signal buffer memory (second memory), 12...Vertical scanning signal buffer memory (second memory), 14...Central processing unit (CPU)
, 16... Pattern memory (first memory), 1
8... Upper bit pattern memory area, 20.
...lower bit pattern memory area, 22.24
......Logic product circuit, 26...Inverter.

Claims (2)

[Scope of utility model registration request] (1) A first memory that stores information for K'LA and B horizontal AXB bit configuration transmission units;
a second memory that stores information transferred from the memory and whose input/output unit has an N-bit configuration, the first memory has a horizontal bit number B of the first memory and the It has a divided area that is divided into five areas equal to B/R at the time of reading so that the greatest common divisor (R bit) of the output unit bit number N of the second memory is read out sequentially in the vertical direction as one unit. and the second memory has N/N bits each having an (AXR) bit configuration.
having T independent memory areas equal to R, and during the transfer, R bits are set to 1 from the first memory;
The unit is sequentially read in the vertical direction and transferred in association with each divided area of the first memory and each independent memory area of the second memory, and when outputting stored data from the second memory, each independent memory area is By simultaneously specifying predetermined addresses of T areas, the output unit of the second memory can be set to N.
A data storage device equipped with a central processing unit that generates control signals that can be read in bits. (2) The data storage device is a data storage device of a video receiver for television teletext broadcasting, and the first memory is a data storage device for a video receiver for television teletext broadcasting, and the first memory is a data storage device for a video teletext broadcast video receiver. A buffer memory that temporarily stores image information in units of transmission, and the second memory rearranges the image information stored in the first memory in order to display it on the screen of the video receiver in a desired format. 2. The data storage device according to claim 1, wherein the data storage device is a pattern memory for storing data.