RU2101781C1 - Device which stores and displays information - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has pulse generator 1, line counter 2, synchronization counter 3, column counter 4, scanning unit 5, matrix display 6, line register 7, memory unit 8, digital comparator 9, calculation unit 10, microprogram control unit 11. EFFECT: increased brightness, increased reliability and even brightness distribution. 1 tbl, 5 dwg

Description

 The invention relates to automation and computer engineering and can be used in a network for displaying information on matrix indicators.

 Known technical solutions (Yablonsky F.M. Troitsky Yu.V. Means of information display. M. Higher school. 1985, p.162, Fig.5.34), including asynchronous sequential in time methods of recording and displaying information using eight-bit address codes for the account of switching addressing with arbitrary sampling and sampling by linear addressing, a method for dynamically displaying information in the field of a two-coordinate matrix with linear addressing by address line scanning pulses. The device contains blocks of memory, synchronization, dynamic scan, address switch and a matrix indicator.

 The disadvantages of these technical solutions are low brightness at a low scanning frequency, low reliability due to asynchronous information switching and limited functionality determined by the rigid structure of the device.

 It is also known a device for displaying information (a. S. USSR N 1571645, class G 09 G 3/00, 1990), which implements a method for recording and displaying sign information with the combination of several lines in time depending on the configuration, as well as dynamic indication matrices with information output synchronously to address scanning pulses of strings. The device contains address and sign registers, algorithm and sweep blocks, a character generator and a matrix indicator.

 The disadvantages of these solutions include narrow specialization due to the rigid operation algorithm, low brightness due to the indication with high duty cycle, relatively low reliability, determined by the complex structure of the device.

 The prototype is a device for displaying information (AS USSR N 1566404, class G 09 G 3/28, 1990), based on the method of recording and displaying information, including the formation of current display addresses by clock pulses, recording information in the code by to an external address with an arbitrary selection in the field of spatial coordinates sequentially in time with a dynamic indication in each cycle by interruption, a dynamic indication with linear addressing by pulses generated from the digits of the reference address by multiplying clock. The method of dynamic indication in the field of a two-coordinate matrix with linear addressing consists in each address cycle from scanning columns and rows of the matrix by pulses generated from the upper and lower digits of the reference address, in proportion to the last output of the bitwise information at the time the current address is generated. The device for recording and displaying information contains a memory unit, the output of which is connected to the information input of the register, the outputs of which are bitwise combined with the horizontal bus of the matrix indicator, the vertical buses of which are bitwise connected with the output of the scan unit, the information inputs of which are connected to the address outputs of the column counter and through the switch channels to the same inputs of the higher bits of the memory block, the lower bits of the address of the memory block are connected through a channel switch with address outputs tchika lines associated with the clock input of the output burst controlled oscillator clock synchronization unit associated switch through channels with address inputs of the device through control inputs of the last sync block entry associated with the memory block MSB.

 The prototype has the following disadvantages: relatively low reliability and brightness, uneven display of information and narrow specialization. The first group of drawbacks is determined by the time switching of various addressing methods: with sequential and random sampling of information, moreover, recording is made from an external device, and information is read in a display device. Other disadvantages are associated with the presence of two modes of reading information and tight centralization of the structure of the device from an external system. The rigid algorithm of the device does not allow individual use, and the presence of two reading modes leads to flickering of the display. In the prototype, the column scan time is ineffectively used to indicate in which a sample of information occupies from 20 to 40% and the brightness and quality of information display is reduced by the same amount.

 The aim of the package of proposals is to increase the brightness and reliability of recording and display, as well as to increase the uniformity of the display in the process of dynamic display and expand the functionality of the device.

This goal is achieved by the fact that:
in a method of recording and displaying information, including generating a display address code with a period of clock pulses, registering information by an address code in a spatial coordinate field with a potential of a logical level and copying recorded information into a two-coordinate matrix field by means of a dynamic indication with linear addressing by pulses generated from code bits the reference address, in contrast to the known solutions, the display address code is organized from pulse characters of pairs of positions of the mantissa number carry out program control of the display address code according to the number of possible combinations defined by the sign pulses of the order of the same number, compare the display address codes and the reference address, at the moment of coincidence of which the logic level potential is recorded in accordance with the program pulse of the sign of the order of the number, and the clock frequency of the output of the recorded information organize from pulses of the highest digits of the reference address code;
in a method for dynamically displaying information in a field of a two-coordinate matrix with linear addressing, which includes, in each address cycle, scanning columns and rows of the matrix by pulses generated respectively from the highest and lowest bits of the reference address code, by which bitwise recorded information is output over the duration of the pulses of the senior discharge, in in contrast to the prototype, additional pulses of equal duration form the number of rows, forming the pulse width of the address cycle of the column from which ydelyayut first additional pulse, the duration of which is composed of a sequence of pulse durations scanning rows of the matrix;
to a device for recording and displaying information with dynamic indication, comprising a memory unit, the output of which is connected to the register information input, the outputs of which are bitwise integrated with the horizontal matrix indicator bus, the vertical buses of which are bitwise connected with the outputs of the scan unit, whose information inputs are connected to address outputs a column counter and the inputs of the higher bits of the memory block of the same name, the lower bits of the address of which are connected to the address outputs of the row counter associated with a clock input with the first output of the pulse generator, in contrast to the prototype, a micro calculator, a microprogram control unit, a comparator and a synchronization counter included between row and column counters are introduced, and a synchronization output connected to the inputs of the calculator and register of the same name, whose clock input is connected to the first output of the generator pulses connected to the phase bus of the microcalculator, the inputs of which are information, dialogue and address inputs of the device, and the information bus integrates it is connected with the comparator and microprogram control unit with the same name, connected by a clock input to the synchronization output of the microcalculator, and the control outputs, respectively, with the comparator chip selection inputs and the memory unit information, the recording input of the latter is connected to the comparator output, the address inputs of which are combined with the same bits of the memory unit.

 When analyzing well-known technical solutions, no solutions were found that have features similar to the set of distinctive features of the claimed solutions.

 In FIG. 1.2 is a timing chart explaining the essence of the method of recording and displaying information, as well as dynamic indication; figure 3 is a structural diagram of a device.

 The device consists of sequentially turning on the pulse generator 1, row counter 2, synchronization 3, columns 4, scanner 5, matrix indicator 6, and a register of 7 lines (horizontal buses). In addition to them, the device includes a memory unit 8, a digital comparator 9, a microcalculator 10, and a microprogram control unit 11. Block 11 is made on the circular inclusion of the register of signs and read-only memory managed at low addresses by a counter that is synchronized by a zero decoder. The information inputs of the register and decoder of block 11 are combined with the outputs of the microcalculator of the same name, the synchronization output of which is connected to the counting input of the counter of block 11. The control outputs of block 11 are the outputs of the permanent storage device in which the code of the sign code of the sequence number is “flashed”. The number of programs is determined by the number of possible combinations of positions of the address of the mantissa number. For example, a programmable calculator "Electronics MK-46" operates with a number with a mantissa of eight decades and an order sign indicator of two decades. The eight-decad mantissa of a number is divided into four pairs of positions making up four two-decad addresses A = Y, X} Turning the address on or off is specified by the sign of the order of the number. The sign of the order of the number is changed programmatically or online by the operator in the range 00-15, which corresponds to the number of combinations for four positions or a four-input truth table for 16 states. The unit and zero terms are mapped to the indication and blanking of the address of the indicated familiarity in the mantissa of the number. For definiteness by the value of the order sign 00} (code 0000), all addresses recorded from 1 to 4 are blanked; 05} (code 1010) the first and third pairs are turned on, and the second and fourth are blanked; 10} (code 0101) - the addresses of the second are indicated and the fourth pair, and the first and third are turned off; 15} (code 1111) the addresses of all four familiarities of the mantissa of the number are displayed on the matrix indicator.

 Information is input into the device through the microcalculator 10 in automatic and interactive modes by controlling the address 12, dialog 13 and information 14 inputs. The information input 14 is combined with the information line of the microcalculator 10 through a multiplexer, switched by address inputs 12 from the central network console. The exchange of information is carried out with direct access to the operating memory ring of the microcalculator and does not exceed, for example, 0.02 s for the MK-46, which is four orders of magnitude less than the time for information to be output from the microcalculator. In the dialogue mode, the information in the calculator 10 is changed by the operator on the bus 13 through a contracture controlled by a digital indicator. The presence in the device of the microcalculator 10 allows you to solve independent problems by modifying the addresses according to algorithmic programs and to carry out cyclic polls of the address bank without the "shallow custody" of the central network console.

 Information from the microcalculator 10 is synchronously outputted by a pulse from the output of counter 3 to the corresponding input connected to the K145IK1801 interface circuit and appears at its output in binary decimal code. To organize the on-off address from the information bus of the microcalculator 10, information on bytes is entered into blocks 9 and 11. To do this, in block 11, the register is two-decad, and the conversion at the first inputs of the comparator is carried out by an additional buffer register controlled by pulses from block 11 at the pre-recording input. When the addresses are modified with the calculator 10 according to the program, the clock pulses from the synchronization input are blocked, and the information on no output. Information from the microcalculator 10 is displayed cyclically for 14 cycles, corresponding to 12 cycles of the number and 2 cycles of service information. Significant of the service codes is the order setting code (1111), resetting the counter of the microprogram control unit 11 through the decoder. The number from the microcalculator 10 arrives sequentially in time, starting from the order sign and ending with the lowest position of the mantissa. Block 11 is engaged in the distribution of significant information in the program. The current program is given by a sign of the order of the number, the code of which is loaded into the registers of block 11 at the beginning of each cycle. A complete code is generated at the address inputs of the ROM, consisting of the lowest counter addresses and the highest register of block 11. In accordance with the selected program, control pulses are generated at the outputs of the ROM of block 11, which determine the operation algorithm of blocks 8 and 9. Following the order sign, the output of the microcalculator 10 addresses indicated in the mantissa numbers.

 In FIG. 1a, a fragment of the address record in the memory unit 8 is shown on the example of the mantissa 99 46 73 28 with a sign of order 10. The current display address code in FIG. 1a is shown in the form of steps, since the weight of the code, which changes at the output of the calculator 10 with each clock pulse, is plotted along the ordinate axis. The same time diagram shows the change in the code of the reference address in the form of a saw, which affects the address inputs of the memory unit 8, as well as the second inputs of the digital comparator 9. The comparator 9 is initiated by pulses from block 11 when a display address code byte is generated on its information inputs. Comparator 9 compares the current display address code with a reference address code that varies cyclically in a linear fashion. When the address codes match, a pulse appears at the output of the comparator (Fig. 1b), which acts on the “record” input of block 8 in the memory. At the same time, its information input is affected by the potentials of an impulse of the order sign (Fig. 1c), in the given example the code (0101). If there is a zero potential at the number address in the memory block 8, a logical zero is registered, otherwise a logical unit (Fig. 1d). For example, in the first state, logic zero is fixed at address 99, in the second state, logical unit is registered at address 46, address 73 is reset to zero, and in the fourth state, the logical unit is copied to address 28. The display address code is converted in phase-pulse form synchronously with outputting information from the calculator 10 and copying information to the matrix indicator 6. The information recorded in the memory unit 8 is copied to indicator 6 in each cycle, and changes when the current code address display at the outputs of the calculator 10. Galvanic isolation between the current and reference address codes increases the reliability of copying and software combining various methods of addressing information.

и строк

матрицы 6 импульсами, формируемыми из IJ-тых разрядов кода эталонного адреса. Блок 5 развертки инициирует включение J-го столбца (фиг. 2а) матрицы 6 посредством преобразования в позиционный двоично-десятичного кода на выходе счетчика 4. Блок 5 развертки состоит из дешифратора столбцов и токовых ключей. Импульсы сканирования столбцов генерируются из кодов старшего адреса Y, составляющих цикл индикации информации. Адресный цикл столбца составляют импульсы синхронизации (фиг.2б), поступающие на вход счетчика 4 столбцов с выхода счетчика 3. На другом выходе счетчика 3 формируется в каждом J цикле знакоместо первого импульса (фиг. 2в) длительностью T/nm. Эти импульсы используются для синхронизации вывода информации из микрокалькулятора для перезаписи информации из блока 8 памяти в регистр 7 строк. За время воздействия синхронизирующего импульса тактовыми импульсами по входу 15 в регистр 7 загружается регистрируемая информация о выходе блока 8 за счет структурного сдвига. Таким образом, информация на горизонтальных шинах индикатора 6 появляется в знакоместе первого импульса синхронизации адресного цикла столбцов, причем загрузка регистра 7 строк осуществляется синхронно адресным импульсам сканирования строк (фиг. 2г-ж) счетчика 2. Индикация информации на матрице 6 происходит в течение всего адресного цикла столбца за вычетом времени первого знакоместа, это исключает неравномерность отображения информации как при записи, так и при копировании. На индикатор 6 информация выводится по столбцам с разверткой изображения блоком 5.Information is copied to the field of the two-coordinate matrix 6 by means of a dynamic indication with linear addressing by pulses generated from the reference address code at the outputs of the line 2, synchronization 3, and column 4 counters. The dynamic indication method includes column scanning in each address cycle T tm ² n

and lines

matrix 6 pulses generated from the IJ-th bits of the code reference address. The scan unit 5 initiates the inclusion of the J-th column (Fig. 2a) of the matrix 6 by converting it into a binary positional decimal code at the output of the counter 4. The scan unit 5 consists of a column decoder and current keys. Column scan pulses are generated from the high address codes Y that make up the information display cycle. The address cycle of the column is composed of synchronization pulses (Fig.2b), which are received at the input of the counter 4 columns from the output of counter 3. At the other output of the counter 3, a familiarity of the first pulse (Fig. 2c) with a duration T / nm is formed in each J cycle. These pulses are used to synchronize the output of information from the microcalculator to overwrite information from block 8 of the memory in the register of 7 lines. During the exposure of the synchronizing pulse clock pulses at the input 15 in the register 7 is loaded with the recorded information about the output of block 8 due to the structural shift. Thus, the information on the horizontal buses of indicator 6 appears in the familiarity of the first pulse of synchronization of the address cycle of the columns, and the register of 7 lines is loaded synchronously to the address pulse of scanning rows (Fig. 2d-g) of counter 2. The information on the matrix 6 is displayed throughout the address a column cycle minus the time of the first familiarity, this eliminates the uneven display of information both during recording and during copying. On indicator 6, information is displayed in columns with an image scan of block 5.

 We show the effectiveness of the proposed technical solutions in relation to the prototype.

Поделив t₂ на t₁, определим эффективность η по времени индикации и яркости:
h = (m-1/2)/k.
Для прототипа k=6-8 и для m=10 видно, что предлагаемое решение в 1,2-1,6 раза индицирует ярче прототипа.1. The display time of the column in the prototype and in the proposed solutions, respectively, is t _1i kT / mn and t _2i (i / nm ² + (m-1) / nm) T. Given that the display time of m lines is defined as

Dividing t ₂ by t ₁ , we determine the efficiency η by the display time and brightness:
h = (m-1/2) / k.
For the prototype k = 6-8 and for m = 10 it can be seen that the proposed solution 1.2-1.6 times indicates brighter than the prototype.

и остается постоянным в каждом цикле на интервале 0,09T, что на практике соответствует равномерной яркости.2. Because of the two addressing modes in the prototype, “k” takes a value of 8 for linear addressing and 6 for addressing with random sampling, while the brightness from mode to mode changes by 1.3 times. In the proposed solution, the indication time t _2i lies in the range (9.0-9.9) • 0.01 T, since

and remains constant in each cycle in the range of 0.09T, which in practice corresponds to uniform brightness.

3. The reliability of the prototype is lower than the reliability of the proposed solutions due to the presence of two addressing modes in the prototype: according to the linear law and with arbitrary sampling, which are changed by the address switch 9. Considering that reliability is determined by the number of address positions (n + m) and the number of addressing modes, we find P ₁ = P for the proposed solution $\genfrac{}{}{0ex}{}{\text{(m + n)}}{\text{o}}$ and the prototype P ₂ = P $\genfrac{}{}{0ex}{}{\text{2 (m + n)}}{\text{o}}$ then
η _p = P ₁ / P ₂ = P $\genfrac{}{}{0ex}{}{\text{- (m + n)}}{\text{o}}$
Thus, the reliability of the prototype in P $\genfrac{}{}{0ex}{}{\text{(m + n)}}{\text{o}}$ times lower than the proposed solution, which corresponds to a decrease in the reliability of the prototype by 2% for a square matrix m = n = 10.

 4. The flexibility and autonomy of the proposed solutions is higher than the prototype due to the introduction of a microcalculator into the device, which decentralizes the display device from the central network console. In addition to automatic mode, interactive mode is added, which greatly expands the functionality. Program control allows you to modify information according to specified algorithms, and the use of a character generator in the device organizes the running line mode. In this case, the central console can serve an additional number of peripheral devices.

We consider the software of the device using an example of an algorithmic sign-synthesizing program, the TEMP mimic diagram is shown in Fig. 4, and Fig. 5 shows a block diagram of the program. The program allows you to simulate the letters of the Russian and Latin alphabets, Roman and Arabic numerals. The algorithm of the program consists of six blocks, the first half of which includes the addresses of character indicators sequentially in time, and the second half of their inclusion in the same sequence. Each half includes three blocks organizing vertical, diagonal and horizontal coordinate management. The control vector is specified by the initial coordinates N _ij , the increment ΔN _i and the final address N _0j . In the cycle of the subprogram, the coordinates N _{ij are} modified by the increment by means of the algebraic addition of N _ij : N _ij + ΔN _i . The increment for each type of control is stored in the glass memory S _i , and the reference coordinates of the vector are loaded in pairs in the register memory P _i (see table).

In each cycle of the subroutine, the modified N _ij and reference N _Oi addresses are compared. Until N _Oi > N _{ij the} addresses of the modified coordinates are displayed on the matrix indicator, otherwise the next control cycle ends and after loading other values of N _Oj and N _ij with N _i , the next stage continues. The inclusion of coordinates is carried out according to code (1111), which corresponds to the number 92 82 12 02 • 10 ⁴⁷ , while the sign of the order corresponds to 54 degrees. Shutdown occurs by code (0000) when modifying the degree of the number by 10, i.e. the sign of order is 55 degrees. For example, the letter T begins to be entered from coordinates 92 82 12 02 with an increment of 01 01 01 01 to the level of 91 81 11 01, which corresponds to the organization of the ends of the upper crossbar. At the second stage, the upper crossbar of the letter is constructed from the coordinates 90 91 00 01 to 50 51 40 41 with a step of 10 09 89 90. The third stage constructs a vertical bar of the letter from the coordinates 50 51 40 41 to 58 59 48 49 with the modification of each address by 2 units, respectively the number 02 02 02 02. In the next three steps, as described above, the same coordinates are turned off sequentially in time and the process starts again. For four devices connected to the central console in the network, the panel displays a TEMP banner sequentially in time (Fig. 4).

 The proposed technical solutions are implemented in the calculator class TEMP-091. The display devices are based on the Electronics MK-46 microcalculators using integrated circuits of the K564 series, the matrix indicators are made in 10 • 10 bits on MTX-90 thyratrons to the size of a standard sheet of A1 format. The indicator panel consists of four matrix indicators driven by autonomous peripheral devices included in the class network. The indicator panel is located above the writing board and allows you to visually display processes and objects on mnemonic diagrams in the field of spatial, temporal and functional coordinates.

 The TEMP-091 calculator class was introduced at the Tambov School No. 13 in the TIHM branch to study the basics of cybernetics.

 Thus, software control of the display address code, including the positions of the mantissa of the number, by means of potentials of the order sign pulses, copying of the recorded information at the moment of the first familiarity of the column address, the use of a calculator, a microprogram control unit and a comparator, in contrast to the known solutions, increases the brightness, reliability and uniformity display, expands the functionality of the device and the autonomy of the periphery due to unloading and decentralization of the information network. This allows you to create calculator video classes for collective and individual training in the basics of the humanities, natural and technical disciplines.

Claims (1)

 A device for recording and displaying information containing a memory unit, the output of which is connected to the register information input, the outputs of which are bitwise combined with the horizontal bus of the matrix indicator, the vertical buses of which are bitwise connected with the outputs of the scan unit, the information inputs of which are connected to the address inputs of the column counter and the same name the inputs of the upper bits of the address of the memory block, the input of the lower bits of the address of which is connected to the address outputs of the line counter associated with the clock input with the first output of the pulse generator, characterized in that a micro calculator, a microprogram control unit, a comparator and a synchronization counter are inserted into it, the counting input of which is connected to the output of the line counter transfer, the address output of the synchronization counter is connected to the address input of the column counter, the overflow output of the synchronization counter is connected to the synchronization inputs of the calculator and the register, the clock input of which is connected to the first output of the pulse generator, the second output of which is connected to the phase bus an calculator, the first to third inputs of which are information, dialog and address inputs of the device, respectively, the information output bus of the microcalculator is combined with the same bus of the comparator and the microprogram control unit, the clock input of which is connected to the synchronization output of the microcalculator, the first and second outputs of the microprogram control unit are connected respectively with the input of the choice of the crystal of the comparator and the information input of the memory unit, the recording input of which is connected to the course of the comparator, the control inputs of which are combined with the address inputs of the memory block.

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