SU634322A1 - Information display - Google Patents

Description

The proposed device relates to the field of automation and computer technology and can be used in the construction of a display device, for example, on the screen of a cathode ray tube. A device for displaying information is known, comprising a clock generator, a symbol memory block, integrators of horizontal and vertical components of a sign sweep, a code-voltage converter, a storage register 1 The device can generate various signs by a functional method, and the functional sign-sweep voltage has seven gradients of slope due to a change in its formation rate over a constant time interval. The disadvantages of the known device include: high requirements for the sign amplifier and the deflection system of a CRT, since both the maximum and the minimum vector are formed in an equally short time; impossibility of use in a composition with radar radar review indicators, since their video amplifiers have a logarithmic characteristic, and in the device to achieve a constant brightness of the displayed vectors, the amplitude of the backlight pulse of characters is varied, which is directly proportional to the length of the vector; the impossibility of using them in a composition with indicators that use the projection of the displayed information on a larger scale, as in such indicators, to ensure the normal projection brightness, the CRT video amplifier works in a key mode, where the backlight is not modulated. The closest in technical essence to the proposed device is a device for displaying information comprising a memory block connected to a register, a function voltage generator connected to a register, a code-time converter connected to a pulse generator and a register connected to a beam illumination unit. . However, this device has significant drawbacks. The first drawback is the poor visibility of special characters, which is determined by the maximum number of segments (vectors) of which the symbol consists. For writing complex configurations

characters cannot increase the number of segments that make up a character without doubling the capacity of these characters. This follows from the organization of the survey block of these characters. The address of the character storage unit is determined by the states of the character code register and the vector counter. With such an organization, an increase in the code length of the characters entails a decrease in the size of the counter of vectors and vice versa, and since the number of segments the symbol consists of is equal to the number of all states of the vector counter, the number of vectors with a different memory block capacity characters back is proportional to the number of characters generated. In the general case, the number of generated symbols is Q 1, and the maximum number of segments that make up a symbol is:

N,

where n is the size of the memory block of characters at the input;

HI is the character code length.

So, for example, with n 10, the values of N and Q for two different values of P are

p, b, N 16, Q 63

p 7, N 8, Q 127

The second disadvantage of the prototype is the poor use of the block of characters or symbols. This is due to the fact that the device incorporates a small number of gradations of the vector for the length of the error. The maximum vector in the prototype is three times the minimum. At the same time, when forming maximum vectors, which refer to the minimum vector as 5: 1.7: 1, two sets should be made to the symbol memory, since such vectors are obtained as a result of summation of vectors having a common slope, and related to the minimum vector in length as 1: 1, 2: 1, 3: 1. The code-time transducer size affecting the number of gradations of the vector in the prototype cannot be increased, since the code-time input 1 transducer code is generated by a magnetic unit from a two-digit code of vectors.

In the formation of the maximum vectors, which refer to the minimum vector as 5: 1, 7: 1, each additional address to the block and these characters is associated with the occupation of new memory cells. In addition, the same number of words of a block and of these characters is assigned to each character, and the number of words is chosen equal to the number of segments in the complex symbol itself. As a rule, an information screen on a CRT screen is displayed in the form of formulas, in which 20% is complex, and 80% is occupied by simpler 3fiaKH (numbers and letters), which are formed from a smaller number of segments than the most southern symbol. Therefore, in the prototype, with vfjopMHpoBaHHH simple characters (numbers and letters), a significant part of the capacity of the character storage unit is used idle.

The consequence of the inefficient use of a block of characters is the reduction in the number of generated symbols.

The aim of the invention is to improve the quality of the display.

The goal is achieved by the fact that an address counter, a logic block and a pulse shaper are entered into the device, connected to a pulse generator, a code-time converter, a function voltage generator, a pa.ti block, an address meter and a logic block connected to the block a memory and an address counter connected by an encoder in time and a memory unit.

FIG. 1 shows a block diagram of the device; FIG. 2 and 3 is a timing diagram of the main signals of the device; FIG. 4 - type of formatted symbol.

The device contains a pulse generator 1, a pulse driver 2, a memory block 3, an address counter 4, a logic unit 5, a code-time converter 6, a micro command register 7, a generator of 8 function voltages, a beam illumination unit 9, block inputs and outputs and devices 10-30.

The device works as follows. The initial time ment t) at the inputs 18 of the device receives the character code. When a sync pulse arrives at ti at input 10 of the pulses 11 and 12 of the generator 1, a push-pull pulse sequence is formed. Moreover, the beginning of the clock pulses at the output 11 coincides with the leading edge of the sync pulse, and the sequence of pulses at the output 12 of the pulse generator 1 is shifted in phase and half of the period relative to the first pulse sequence. Both of these sequences of pulses are fed to the inputs of the imaging unit 2 pulses and to the inputs of the converter 6 code-time.

The shaper 2 pulses at the moment of time generates at the output 23 a signal to write the character code, according to which the character code from the output 19 of logic unit 5 (“2I-ILP) is fed to the information inputs of the counter 4 addresses. The output number from the output 20 of the counter 4 addresses goes to the address inputs of the memory block 3. At the same time, the driver 2 of the pulses at the output 25 generates a polling signal of the memory block 3.

At time tj, at outputs 13 and 15 of block 3, a 10-bit microprogram word of the initial symbol address is formed, which goes to the second and third group of information inputs of logic block 5 and simultaneously to the imiuls driver 2. code-time converter 6, register 7.

In momeit time 1h, the pulse former 2 generates at output 24 a signal for setting the address counter 4 to zero, and at time t at output 22 it is a signal to write the initial address code, according to which the initial address code from output 19 of the logical1 () block arrives on the information inputs of the counter 4 addresses. At the same time, the code of the starting address of the symbol is written into the counter 4 of the address, and into the 2 pulse shaper, the code-time converter B and the register 7 the code of the starting address is not recorded, because at this time the write enable signal is not received on these blocks. In addition, at time t (at the output 25 of the pulse driver 2, the interrogation signal of the memory block 3 is detected.

At time tj, the output signal 26 of the pulse driver 2 generates a signal that the memory 3 is set to zero, and the output 25 receives the next interrogation signal of the memory 3.

At time ij, at outputs 13 and 15 of memory 3, the first 10-bit word of the symbol sweep microprogram is formed, the first three bits of which, from output 13, go to the inputs of converter 6 code-time to form the vector length and to driver 2 pulses to form the end of a signal.

From output 15, seven bits of the microprogram word sweep of the character go to the information inputs of register 7, four bits of which determine the slope of the functional voltages X and Y, two indicate its sign, and the seventh bit determines the vector illumination. Simultaneously, from the outputs 13 and 15, the microprogram code of the signal sweep enters the second and third information inputs of the logic unit 5. However, the number is not recorded in the counter 4 addresses, because during all subsequent time intervals the output 22 of the code does not generate a signal to write the code in the counter 4 addresses .

At time t / converter 6, the code-time at output 14 generates a signal to start recording the first word of the symbol sweep microprogram, which is fed to the control input of register 7, as well as to the input of the pulse generator 2 pulses and the counting input of the counter 4 addresses. At the same time, at the output 25 of the imaging unit 2, the interrogation signal of the character memory unit 3 is removed, at the output 20 of the address counter 4, the code of the initial address is increased by one younger digit, and the code of the character sweep firmware is written to register 7.

At time i, from outputs 16 and 17 of register 7, the code of the first vector of the symbol is fed to the information inputs of the generator 8 functional voltages X and Y and to the beam illumination unit 9, and from output 27 of the driver 2. pulses to the control input of the generator 8 functional voltages a signal is received to enable the generator of 8 functional voltages, which begins to generate the sweep signals of the first symbol vector.

The length of the formed vector is proportional to the time code received by the code-time converter 6 from memory block 3.

At time tg, the shaper 2 HMiiy.ibcoB generates the output 26 of the next signal. setting the block of 3 memory to zero, and output 25 a new polling signal.

At time tg block 3 at the outputs

13 and 15 forms the next word of the character sweep firmware, which is stored in the output register of the memory block 3. After three periods of the clock frequency at the time moment it, the converter 6 is in time, generates a signal for the end of vector formation, while the converter rewrites the new code of the output number from memory block 3 to converter 6, register 7 and increases the address code at output 20 of counter 4 of address by one unit.

From time tio exit code 16

register 7 controls the operation of the function voltage generator 8, which generates the sweep signals of the second symbol vector, and the code-time converter 6 determines its length.

At time tn shaper 2

Immediately, at the outputs 25 and 26, new polling signals and setting the memory block 3 to zero form, and at time 1, g, at the outputs 13 and 15 of block 3, a new microprogram word of the third vector appears,

which, according to the signal of the end of the second vector, is again recorded in code-time converter 6 and register 7.

As can be seen, from the time t, the character memory block 3 is transferred to the sequential polling mode of the memory cells, in which the code of the input address at the output 20 of the address counter 4 is incremented by the least significant bit of each vector end signal.

All subsequent vectors constituting

the outline of the symbol of FIG. 4 are formed in a similar manner.

At time 1; e, the code-time and register 7 are recorded in the converter 6, the code of the last fifth vector and the addresses at the output of counter 4 change, and at time 1оo, memory block 3 generates an output number containing zeros in all bits. Under this condition, the driver 2 pulses at the output 21 of the signal of the end of the last vector generates a signal of

forming a symbol with which all nodes of the device are set to zero.

The signal generation of the end of a symbol by the losh does not require an increase in the size of the character storage unit.

Claims (2)

In relation to the prototype, the claimed device has the following advantages. 1. At a constant capacity of block 3 of memory, the maximum number of vectors from which the most complex symbol is formed does not depend on the width of the character code and, in principle, any number of vectors can be laid into a complex symbol. Thereby, the visibility of the symbols is increased, which is the higher, the greater the number of elements of the symbol decomposition (in the television method) or the greater the number of vectors that fit into the outline of the symbol (in the functional method). 2. The number of memory cells for each symbol is proportional to the number of vectors constituting the symbol. 3. Since the vectors have a gradation in length from 1 to 7, then all the characters are formed after a small number of calls to the fleas of the 3 character memories and thus saving memory. 4. In view of paragraphs. 2 and 3, as well as taking into account the redirection of the character memory block 3, the memory for symbols is very economical, which allows to increase the range of generated symbols. An apparatus for displaying information comprising a memory unit connected to a register, a function voltage generator connected to a register, a code-time converter connected to a pulse generator and a register connected to a beam illumination unit, characterized in that increase the display quality; an address counter, a logic block and a pulse shaper are connected to the pulse generator, a code-time converter, a function voltage generator, a memory block and, an address counter and a logic unit connected to the memory unit and an address counter connected to the time converter and the memory unit. Sources of information taken into account in the examination: 1.Anofreenko G. T. High-speed sign generator for the ECM indicator. "Automation of design in electronics, Kiev," Technique, 1972,, Yo 5. 2. USSR author's certificate number 484539, cl. G 06 K 15/20, 1973. Inputs, JS tj („