SU1626160A1 - Multi channel indicator with ability to store signal in digital form - Google Patents

Abstract

The invention relates to a measurement technique and can be used in oscilloscopes, indicators of radar geophysical, medical and other equipment. The purpose of the invention is to reduce the frequency range of the studied signals. The goal is achieved by the accumulation of information in the memory block 5 of information received during the flyback time of the line 8 counter elements of the line. Switch 3 sequentially selects the channels of information. In addition, the indicator contains amplifiers 2, analog-to-digital converter 4, cathode-ray tube 6, clock generator 7, 9 rows counter, sweep generation unit 10, second switch 11, second clock generator 12, counter 13 of a channel, counter 14 time and block 15 comparison. 1 il.

Description

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The invention relates to a measurement technique and can be used in oscilloscopes, data indicators of radar, geophysical, medical and other equipment.

The purpose of the invention is to reduce the frequency range of the investigated signals of a multi-channel indicator by introducing different write and read speeds. The drawing shows a block diagram of a multi-channel indicator with digital waveform memory.

The circuit contains input terminals 1.1-1.p, amplifiers 2.1-2.P, first switch 3, analog-digital converter 4, memory block 5, cathode-ray tube 6, first clock generator, counter 8 line elements, counter 9 lines, block 10 of the formation of sweeps, the second switch 11, the second generator 12 clock pulses, the counter 13 of the channel, the counter 14 of time, the block 15 comparison codes.

Moreover, n inputs of signals 1.1-1.P are connected to the inputs of amplifiers 2.1-2.P, the outputs of which are connected to the information input of the first switch 3, the output of which is connected to the input of the analog-digital converter 4, the S-bit output of which is connected to the information inputs D memory block 5. The cathode ray tube 6 has two pairs of deflection plates and a modulator. The output of the first generator 7 clock pulses is connected to the clock input of the counter 8 line elements, the first output of which is connected to the clock input of the row counter 9, to the first input of the sweep generation unit 10 and to the control input W of the second switch 11. The second group of outputs is k counter bits elements 8 lines connected to the first group of inputs (bits from the 1st to the k-th) of the second switch 11. The first output of row counter 9 (output CG I) is connected to the second input of the scanner forming unit 10. The output of the second generator 12 clock pulses is connected to the clock input of the counter 13 of the channel number, the first group of outputs of which is connected to the control inputs of the first switch 3 and to the second group of inputs (bits from k + 1 th to k + m-th) of the second switch 11 and the transfer output is connected to the clock input of the counter 14 of the time reference, the k-bit output of which is connected to the second group of inputs of the switch 11 (bits 1 through k). The output of the second switch 11 (k + m bits) is connected to the address inputs of the memory block 5, the first output of the counter 8 line elements is connected to the write-read control input.

The output of the memory unit 5 (S bits) is connected to the second input of the code comparison unit 15. The second group of outputs (S bits) of the 9-row counter is connected to the first input of the code comparison unit 15, and a third group of 9-row line outputs (t bits) is connected to the first group of inputs of the second switch 11 (bits from k + 1-th to k + mth). Output AB block 15 comparison

The 0 codes are connected to the modulator of the cathode ray tube 6, and the outputs of the scanner forming unit 10 are connected to the deflection plates of the cathode ray tube 6.

5 Multichannel indicator with digital memory waveform works as follows.

At the terminals 1.1 -1.h are given h signals that need to be displayed on the screen

0 indicator so that there is a fixed non-blinking image. These n signals are amplified in amplifiers 2.1-2.P and are fed to the n inputs of the first switch 3. Switching the first switch 3

5 is implemented by the counter code 13 of the channel number, the width of which is m Iog2n. The switching frequency of the switch 3 Tzp is determined by the second generator of 12 clock pulses and is determined by the character of the signals at the inputs 1.1-1.p. For example, if the signals at these inputs are periodic with a period of Tsignn and on the period it is enough to display 10 points, then fzap 10 h / Tsignn. From the output of the first switch 3

5, the signal is fed to the input of the analog-digital converter 4, and from its output the S-bit digital code is fed to the information inputs D of the memory block 5. The process of writing to memory block 5 is as follows. Let at the output of analog-digital converter 4 there is an S-bit information word characterizing the amplitude of the signal of the 1st channel at a given moment in time (signal counting). The closest line quench pulse (SGI) from the first output of the element counter on line 8 turns on memory block 5 at the WR input for recording. At the same time, the same pulse arriving at the control input

0 W of the second switch 11, connects the address from the second input B to the output. At the second entrance B, there is an m-bit number, denoting the number of the channel being polled, which is currently equal to I-bit and K-bit

5 is the number indicating the time point number - the first one is taken from counter 13, the second from counter 14 (equal to the moment d). At address i, d, the signal is recorded, replacing the one previously recorded at that address. With the following

a clock pulse generator 12 at the output of the counter 13 is formed address 1 + 1. the switch 3 connects the output of the I + 1-channel signal, the analog-digital converter 4 converts the amplitude of the 1 + 1-channel signal into a digital code. this code is recorded in memory block 5 by the closest GIS pulse at address I + 1, d. After iterating through all the n channels, switch 3 sets address d + 1 on counter 14, and so on. Gradually, the information is updated at all time points.

During the forward run of the line scan (OTG is absent) in the second switch 11, numbers from the first input A are connected to the output. To the first input A of the switch 11, a k-bit word is connected to the bits of the counter 8, all values of which are sorted. the horizontal sweep and each value corresponds to a certain time point of the signal, and the m-bit word from the upper bits of counter 9, which indicates the number of the zone in which the signal of a certain channel is indicated. Each zone occupies l / n scan lines and, while these l / n rows unfold on the screen, memory block 5 is polled 1 / n times at time sample addresses of this memory zone, i.e. information on the output of memory block 5 is repeated on each line. The low bits of counter 9 are fed to the first input A of block 15 of the code comparison, and to the second input of this circuit, the S-assignment of the information words are received from memory block 5. If the signal level is equal to j and takes place at a time point with address d, then on the J-th line at this time point the values will coincide and at the output AB of the block 15 there will be a pulse, which, arriving at the cathode-ray modulator 6, light a point with coordinates: horizontally - d, vertically - zone i, line J. For each of the 2 words appearing during the forward sweep along the line at the output of memory block 5, there is such a line, where lit up point. The combination of these points forms an oscillogram in the i-th zone of the screen for the 1st channel signal. The process of recording new information is visually observed as a gradual replacement of old oscillograms with new ones at the rate specified by generator 12.

Claims (1)

Invention Formula A multichannel indicator with digital waveform memory, containing a set of n amplifiers whose outputs are connected to the information inputs of the first switch, the output of the first switch is connected to the input of an analog-digital converter, the outputs of which are connected to the information inputs of the memory block, the scanner shaping unit, the outputs of which connected to deflection plates of the cathode ray tube, characterized in that, in order to reduce the frequency range of the signals under study, the first gene is introduced into it clock pulse generator, row element counter, row counter, second clock generator, channel counter, time counter, second switch and code comparison unit, the output of the first clock generator connected to the clock input of the row element counter, the first output of which is connected to the first input sweep forming unit, with a clock input of a row counter, with a control input of a second switch and with a memory control read / write control input, the second group of outputs of the counter ki is connected to the first group of inputs of the second switch, the first output of the row counter is connected to the second input of the scanner generation unit, the second group of outputs of the row counter is connected to the first group of inputs of the code comparison circuit, the third group of outputs of the row counter is connected to the first group of inputs of the second switch, the output of the second clock generator is connected to the clock input of the channel counter, the first group of outputs of which of m bits is connected to the control input of the first switch and the second group of inputs to of the switch, the transfer output of the channel counter is connected to the clock input of the time counter, the outputs of which are connected to the second group of inputs of the second switch, the outputs of the second switch are connected to the address input of the memory unit, the output of which is connected to the second group of inputs of the code comparison circuit, the output of which is connected to modulator cathode ray tube.