RU1803878C - Multichannel indicator with digital memorizing form of signals - Google Patents

Abstract

Usage: the invention relates to measuring equipment and can be used in oscilloscopes and data indicators. The aim of the invention is to improve image quality by increasing the light output of the image by illuminating the column of dots vertically from zero

Description

1-1

".

with

o stock xj stock

Fig L

level to the amplitude value of the displayed signal. The inventive device contains n amplifiers 2 input signals connected to the first switch 3, the output of which through an analog-to-digital converter 4 is connected to the information inputs of the memory unit 5. The first clock generator 7, the counter of elements of line 8 and the counter of lines 9 a read address is generated, a second clock generator 12, a channel 13 counter and a time counter 14 form a write address. Address switching is accomplished by the second switch 11. The outputs of the line element counter 8 and the line counter 9 are connected to the scanning unit 10, the outputs of which are subcirculated to the deflecting plates of the cathode ray tube. Low-level outputs

The invention relates to measuring equipment and can be used in oscilloscopes, data indicators of radar, geophysical and other equipment.

The purpose of the invention is to improve image quality by increasing the luminous efficiency of the image by illuminating the column of dots vertically from zero to the amplitude value of the displayed signal.

Figure 1 is a functional diagram of a multi-channel indicator; Fig. 2 is a diagram explaining the principle of operation; in Fig.Z - indicator screen.

The essence of the operation of the device is as follows. The invention on the television indicator screen, which has a first scan of the I line scan, is divided into n tracks, each of which displays one of n input signals. In the prototype device, the digital signal code is compared with the line number on the track, if it matches, a dot is displayed on the screen, the set of points forms an oscillogram. In the described indicator, instead of one point, d points are displayed, arranged one after another in the column and in the interval between the point of coincidence of the line number and signal code and the conditional zero signal level. By such a zero level we mean a line within a single track located at a countdown from above in the middle of the track. If the track occupies l / n lines, then, obviously, this is the line with the number / 2l. If (see FIG. 2) the signal level is equal to the line number, then the light tc points on all lines from

a 9 line counter is connected to the first inputs of the first 15 and second 16 code comparison circuits. The output of the sign bit of the memory block is connected to the control input of the arithmetic-logic device 17, as well as to the inputs of the element 18 2 x ZI-OR (including through the inverter 19), the outputs of the remaining bits of the memory block through arithmetic the logic device 17 is connected to the second input of the first code comparison circuit 15. The code input l / 2n (I is the total number of vertical lines) is connected to the arithmetic logic device 17 and to the second input of the second code comparison circuit 16. In two code comparison circuits and a 2 x Y-OR element, a video signal is generated by which a histogram type image is generated on the cathode ray tube screen. 3 ill.

this number to the line with the number l / 2n. Thus, the waveform is not obtained in the form of points, but in the form of columns (like a histogram). On Fig.3 shows a view of the waveforms with this presentation of information.

A feature of such an indication is that, for a signal of positive polarity, the bar of dots above lights up.

0 of the conditional zero line (line with the number 1 / 2n), and for a signal of negative polarity it is below this line. As shown in Fig. 2, for the positive half-wave of the signal, it is necessary to subtract the level of the signal R from the number 1/2 n, and for the negative the adder (counting the lines from top to bottom). For this, an arithmetic logic unit (ALU) is provided in the indicator circuit, controlled by the sign bit of information from the output of the memory unit. With a positive sign, the ALU works as a subtractor, with a negative sign - as an adder. The output ALU code is supplied to the second input of the first code comparison circuit.

5

If we denote the line number on which the point is illuminated as J, then we can write the following inequalities: for a positive signal polarity

- R j at negative,,, I

2p

signal polarity

2p

 J

first case inequality

2 p

+ R. In

-R j

and I UVJ I 1W f -

O i

implemented in the first move comparison scheme (output A B); to realize the second inequality, a second comparison scheme is needed

codes where but the string j is compared with the constant -k- (output AB is used). In the second case, the inequality j -J- + R is realized in the first code comparison scheme (output), and the inequality j. I

2 p

in the second code comparison scheme

(exit A B). Thus, two code comparison schemes having four outputs are used. To combine them, a 2x3-OR element is used, which has two matching schemes for three inputs, the output A is connected to the first matching circuit A In the first code comparison circuit and the second code comparison circuit, the second matching circuit is {vice versa: A In the first code comparison circuit and And B is the second. The operation of the first coincidence circuit is permitted by the sign bit information, the work of the second by inversion of the sign bit. Due to this, an indication is formed (see Fig. 3), the luminosity of which is many times higher than in the prototype device.

In FIG. 1 is a functional diagram of a multi-channel indicator; Fig. 2 is a diagram explaining the principle of operation; in Fig.Z - indicator screen.

The multi-channel indicator with digital z-reference of the waveform contains n inputs 1.1-1. P signals that are connected through the amplifiers 2.1-2. P to the inputs of the first switch 3, the output of which is connected via an analog-to-digital converter 4 to the information input of the memory unit type 5, a cathode ray tube (CRT) 6. The first clock pulse generator 7 is connected to the input of a line element counter 8, the output of which is connected to the input of a line counter 9 and a scan forming unit 10, the outputs of which are connected to CRT deflecting plates 6. Outputs counters 8 and 9 are connected to the first group of inputs of the second switch 11. The second clock pulse generator 12 is connected to the input of the channel counter 13, the bit outputs of which are connected to the control input of the first switch 3, and the transfer output to the input of the time counter 14. The first inputs of the first 15 and second 16 code comparison circuits are connected to the first input of a 9 line counter. The output of the arithmetic-logic device 17 is connected to the second input of the first code comparison circuit 15. The outputs of the code comparison circuits 15 and 16 are connected to the inputs of the 2x3-OR 18 element, to the input group of which the output of the sign bit of the memory unit 5 is directly connected. and to the other group of inputs, the sign output is connected through the inverter 19. The code 1 / 2p 20 input is connected to the first input of the arithmetic-logic device 17 and the second input of the code comparison circuit 16. The output of information bits of the memory unit 5 is connected to. the second output of the arithmetic-logic device 17, and the output of the sign bit - with the control input of the arithmetic-logic device 17. The output of the 2x3-OR 18 element is connected to the CRT modulator 6.

Claims (1)

SUMMARY OF THE INVENTION Multichannel indicator with digital; memory waveform containing n input terminals connected by n amplifiers, the outputs of which are connected to the inputs of the first switch, the output of which, through an analog-to-digital converter, is connected to the information input of the memory unit, a scan forming unit, the outputs of which are connected to the deflecting plates electronically -radiation tube, the first clock generator, the output of which is connected to the clock input of the line element counter, the first output of which is connected to the first input of the forming unit to, with the clock input of the line counter, with the control input of the second switch and with the write-read control input of the memory unit, the second group of outputs of the element counter. The line is connected to the first group of inputs of the second switch, the first output of the line counter is connected to the second input of the forming unit second scan, the group of outputs of the line counter is connected to the first group of inputs of the first block of code comparison, the third group of outputs of the line counter is connected to the first group of inputs of the second switch, the output of the second generator a clock coupled to takto-. the input of the channel counter, the first group of outputs of which from m bits is connected to the control input of the first switch and the second group of inputs of the second switch, the transfer output of the channel counter is connected to the clock input of the time counter, the outputs of which are connected to the second group of inputs of the second switch, the outputs of the second switch are connected to the address input of the memory unit, characterized in that, in order to improve image quality by illuminating the column of dots vertically from the amplitude value of the displayed signal to the zero level, a second code comparison unit, an arithmetic-logic unit, a 2хЗИ-OR element and an inverter are introduced into it, while the first output of the first code comparison unit is connected to the first input of the 2xPIN element. the second output of the first code comparison unit is to its fourth input, the output of the 2хЗИ-OR element is connected to the cathode ray tube modulator, the sign bit of the output of the memory block is connected to the control input of the arithmetic-logical block, the remaining bits of the output of the memory block connected to the second input of the arithmetic-logical block, the output is connected to the second input of the first block code, the first group of outputs of the line counter is connected to the first input of the second code comparison unit, the first output of which is connected to the sixth input of the 2x3-OR element, and the second output is connected to the third input of this element, the sign bit of the memory block output is connected to the fifth the input of this element, the input of the code is connected to the first input of the arithmetic-logic-log block and to the second input of the second block of code comparison.