SU1038965A1 - Data display device - Google Patents

Abstract

A DEVICE FOR DISPLAYING INFORMATION containing a memory block, the address input of which is connected to the output of the first counter, and output to the input of the comparison element, the second input of which is connected to the output of the synchronization and control unit, and the output of the comparison element connected to the input of the signal generator of the brightness marks output which is connected to the input of the cathode-ray tube, the control inputs of the memory unit, the input register, the first counter and the signal- former: Nsshov RC: to the marks are connected to the corresponding Ions of the synchronization and control unit, characterized in that, in order to expand the field of application of the device by displaying graphs, the ordinate codes of which arrive at the input of the device with a frequency randomly varying in time, it contains the second and third counters, the first and second blocks of the buffer the memory and the switch, the information inputs of the first and second blocks of the buffer memory are connected to the output of the input register, the address inputs are connected to the information outputs of the second and third counters but, and the outputs are with the inputs of the switch (the output of which is connected to the information input of the memory unit, the second and third counters are connected to the control inputs of the sync and control unit, the control outputs of which are connected to the control inputs of the second and the third counter, the first and second blocks of the buffer with eo: about the memory and the switch. 35 bp

Description

The invention relates to computing and can be used to display digital ones. data in the form of graphs in display devices based on a raster imaging method. A device for moving images of graphs on a screen is known, in which it is necessary to preliminarily set the speed of movement by writing the speed attribute in a special register. ID The device does not allow displaying graphs whose ordinate codes arrive at the device input with a frequency randomly varying in time from zero to some final value. This is required, for example, when displaying electrocardiograms and other curves reflecting non-solid processes in real time. Closest to the present invention is a device containing a memory block, whose address input is connected to the output of the graph ordinate counter, and the output to the first input of the comparison circuit, the second input of which is connected to the output of the synchronization and control unit, the output of the comparison circuit is connected to the input shaper markers, the output of which is connected to a CRT, and the control inputs of the memory unit, the input register of the ordinates of graphs, the ordinate counter of graphs and the shaper of the signals of the viscosity marks are connected to the output and synchronization control unit 2. The lack of devices is the impossibility of displaying graphs whose ordinate codes arrive at the input of the device with a frequency randomly varying in time from zero to some final value. The purpose of the invention is to expand the field of application of the device by: displaying graphs whose ordinate code arrives at the input of the device with a frequency that varies randomly in time. The goal is achieved that the device contains a memory block whose address input is connected to the output of the first counter, and the output to the first input of the reference element, the second input of which is connected to the output of the synchronization and control unit, and the output of the comparison element is connected to the input of the rotator the luminance level signal whose output is connected to the CRT input, the control inputs of the memory unit of the input register and the luminance level signal generator are connected to the corresponding outputs of the synchronization and control unit additionally contains the second and third counters, the first and second blocks of the buffer memory, the switch, the information inputs of the first and second blocks of the buffer memory are connected to the output of the input register, the address inputs are connected to the information outputs of the second and third counters, respectively, and the outputs from the inputs of the switch, the output of which is connected to the information input of the memory unit, the control outputs of the second and third counters are connected to the control inputs of the synchronization and control unit, and the control panel the ports of which are connected to the control inputs of the second and third counters, the first and second blocks of the buffer memory, and the switch ... The drawing shows a block diagram of the device. The device contains a synchronization and control unit 1, an input register 2, a second counter 3, a third counter 4, a first buffer memory block 5, a second buffer memory block b, a switch-7, a first counter 8, a memory block 9, a comparison element 10 , shaper 11 signals of brightness marks, CRT 12. Memory block 9 can be manufactured on K 565RU2 microcircuits, and the remaining units of the device can be manufactured on K155 series microcircuits. The device works as follows. The display of graphs, the ordinate codes of which are fed to the input of the device with a frequency randomly varying in time, is carried out by continuously moving the image of the graphs on the screen from left to right. When moving, the graph points located on the right side of the screen are lost. Plot points, the ordinates of which are input to the device, are displayed in the free space on the left side of the screen. Memory block 9 contains m AND-bit cells, where m is a quantity. The points of the graphs displayed on the screen during one frame, and the resolution of the codes of the ordinates of the graphs. The first block 5 and the second block 6 of the buffer memory contain kn across a number of consecutive cells, where k is the greatest number of ordinates of the graphs arriving at the device input during the time of one frame. Information in the form of ordinate codes of graphs through the input register 2 enters the information inputs of the first block 5 and the second block 6 of the buffer memory. During the even

frame information is stored in the first buffer memory block 5, and the information contained in the second block b of the buffer memory is copied through the switch 7 into memory block 9. During the odd-numbered frame, the information is entered into the second block 6 of the buffer memory, and the information contained in the first block 5 of the buffer memory is copied through the switch 7 into the block 9 of the memory.

Moreover, the entry of information into the memory block 9 occurs during the flyback of the vertical sweep.

The write and read addresses of the first block 5 and the second block 6 of the buffer memory form the corresponding information outputs of the second counter 3 and the third counter 4.

When information is recorded in the first block 5 or the second block 6 of the buffer memory, with each new code of the graph's ordinate entering the device, the contents of the second counter 3 or the third counter 4 are increased by one. Recording information into memory block 9 from the first block 5 or the second block 6 of the buffer memory after recording each new graph ordinate code. the content of the second counter 3 or the third counter 4, respectively, is reduced by one until one of them goes to the zero state. Thus, the content of the second counter 3 and the third counter 4 at any given time determines the number of codes of the ordinates of the graphs contained respectively in the first block 5 and the second block b of the buffer memory;

The write and read addresses of memory block 9 form the first counter of 8 ordinates of graphs. Bringing information into memory block 9, the contents of the counter 8 ordinates of graphs. decreases by one synchronously. with decreasing by one the contents of the second counter 3 or the third counter 4 of the control, until one of them converts to the zero state.

After switching to the zero state of the second counter 3 or the third control counter 4, the output code of the first ordinate readable for displaying the point of the graph in the next frame is found at the output of the first counter 8 of the graph ordinates.

During the direct frame scan xojga, information is read from memory block 9 to display it on the screen of the CRT 12. The first counter of the 8 ordinates of the graphs has a conversion factor equal to the number of graph points displayed on the screen during one pick-up. From block 1 of synchronization and control, counting pulses are received to the input of the first counter of 8 ordinates of the graphs, increasing its content by one. Thus, from block 9 of the memory, reading the codes of the ordinates of the graphs to the first input of the element 10 will be compared. neither At the moments of equality of codes of graphs to codes received

0, from the synchronization and control unit 1 to the second input of the comparison element 10, signals are generated that are fed to the input of the former 11 of the luminance signals. The shaper of 11 signals: luminance ot5 marks provides display of points of schedules on a CRT 12 according to television scanning.

Thus, the device allows receiving on the screen of a CRT as

0 static and dynamic image of graphs J The speed of continuous movement of the image of graphs depends on the frequency of receipt of ordinate codes of graphs to the input of the device, on the number of displayed points on the screen and on the screen size.

If M is the number of codes of the ordinates of the graphs arriving at the input of the device | unit in a unit of time; ot - linear size of the screen (raster) horizontally; p is the number of elements of the decomposition of the raster horizontally, then the speed of movement of the images is.

5, the graphics on the screen will be expressed by the following formula.

-). M UNITS f units. of time

0 For example, if the CC is cm; / 5 400 points; M CO-400) points / s, then S) (0-10) cm / s.

The device allows you to display graphs whose ordinate codes arrive at the device input at a frequency that varies arbitrarily from zero to some final value. The speed of movement of the graphs on the screen is set automatically by analyzing the number of codes of the ordinates of the graphs entering the device during the time of one sadra. Auto sko task (Rosti of movement of graphs provided).

5, simplifies the control of the device / and improves the usability of its operation in comparison with the known display devices.

The proposed device can be used in the oscillographic technique when displaying electrocardiograms and other curves reflecting continuous processes in real time.

Claims (1)

A device for displaying information, comprising a memory unit, the address input of which is connected to the output of the first counter, and an output with the first input of the comparison element, the second input of which is connected to the output of the synchronization and control unit, and the output of the comparison element is connected to the input of the shaper of luminance marks, output which is connected to the input of the cathode ray tube, the control inputs of the memory unit, the input register, the first counter and the shaper of the brightness markers are connected to the corresponding outputs b synchronization and control eye, characterized in that, in order to expand the scope of the device by displaying graphs, the ordinate codes of which are input to the device with a frequency arbitrarily changing in time, it contains the second and third counters, the first and second blocks of buffer memory and a switch, and the information inputs of the first and second blocks of buffer memory are connected to the output of the input register, the address inputs are connected to the information outputs of the second and third counters, respectively, and the output from odes switch, • whose output is connected to an information input of the storage unit, the control output of the second and third counters are connected to the control inputs of the synchronization and control unit, the control outputs of which are connected to control inputs of the second and third counters, the first and second blocks and the buffer memory switch.