SU1635251A1 - Digital filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve the fidelity accuracy of the input signal pulses. The digital filter contains comparator 1, elements AND 2, 3, and 6, element OR 4, RS-flip-flop 5, counter 8, generator 7, D-flip-flop 9, and source 10 of the reference voltage. The input of the comparator 1 receives a video signal distorted by interference. If the signal level at the filter output does not correspond to the input signal level, then the output of the OR 4 element is a high level signal that sets the short-circuit flip-flop 5 to 1 and allows the operation to count: a 8. At a specified time interval, counter 8 will generate an overflow signal, which will write the value of the input signal to the D-flip-flop 9 and reset the RS-grigger 5 and the counter 8. 1 Il. " (ABOUT

Description

The invention relates to radio engineering and can be used in digital signal processing.

The purpose of the invention is to improve the accuracy of reproduction of the duration of the input pulse.

The drawing shows an electrical circuit diagram of a digital filter.

The digital filter contains a comparator 1, the first and second elements AND 2 and 3, the element OR 4, the RS flip-flop 5, the third element AND 6, the generator 7 clock pulses, the counter 8, the D-flip-flop 9 and the source 10 of the reference voltage.

The digital filter works as follows.

When power is turned on, D-flip-flop 9 is set to an arbitrary state. If the output level of the digital filter does not match the level of the input signal (log.1m output of the digital filter and log.O at the input or vice versa) at the output of the first And 2 element or the second And 3 element (depending on the signal levels at the output and at the input) A log is generated. H, which sets the RS-trigger 5. Log. 1 at the output of the RS flip-flop allows the passage of counting pulses from the generator 7 clock pulses through the third element I 6 to the clock input of the counter 8. The counter 8 for-.

Digital filter delay interval is equal to

t (K) tZ F

where n is the counter size;

K is a constant number proportional to the delay} F is the generator frequency of 7 clock pulses.

When the counter reaches 8 K, an impulse fcnor is formed at its output. 1), which arrives at the clock input of the D-flip-flop 9 and switches it to the state corresponding to the signal level at its information input.

Thus, delayed signals are formed at the output of the digital filter corresponding to the pulses of the video signal at its input.

When interference occurs (a pulse in the pause of a video signal or inset when there is a video signal) with a duration of C - “g tz, at the output of the And 2 or 3 elements (in the first case, at the output of the And 2 element, in the second case, at the output of the And 3 element) a signal of ps. 1, which, through the OR element 4, coaxes the RS-flip-flop 5, which provides the formation of a clock pulse for the D-flip-flop 9. Since the state at the output of the D-flip-flop 9 changes only when the signal levels at its information input and output do not match the arrival time of a clock pulse is interfering with the duration and does not cause a change in the output signal level.

If a frame appears in the time interval from the front of the video signal pulse, there is a decrease in the digital filter delay time tz

five

pulse generated at the output of the digital filter does not occur, because the delay time t of the digital filter starts counting from the front of the video signal pulse tq). The P-flip-flop 9 switches to the state corresponding to the signal level at the input at the moment of time (t + fz).

Thus, the introduction of the RS-flip-flop, the third element of the AND, D-flip-flop and new connections allows one to achieve the goal - to improve the fidelity of the input signal duration.

Claims (1)

Invention Formula five A digital filter containing a series-connected voltage source, a comparator, the first AND element and the OR element, and a second AND element connected between the inverse output of the Comparator and the second input of the OR element, a clock generator and a series-connected counter and trigger, inverse, and so on. my outputs of which are connected to the second inputs of the first and second elements AND, characterized in that, in order to improve the accuracy of reproduction of the duration of the input pulse, entered in series are connected Trigger and the third element And, the second input and output of which is connected to the clock pulse generator and the clock input of the counter, and the trigger is designed as a D-flip-flop, whose information input is connected to the direct output of the comparator, and the output of the OR element is connected to the RS setting input - trigger, the reset input of which is connected to the reset input and the counter output.