SU1239704A1 - Digital function generator - Google Patents

Abstract

The invention relates to automation and computing and is intended to reproduce slashes functional dependencies. The aim of the invention is to increase the efficiency of using memory devices, increasing the number of replicable splines for a given amount of memory and expanding the class generated by. given set of approximate splines. Introduction of a digital generator of functions, two switches h of the element NOT allowed to increase the number of splines obtained for a given amount of memory, to expand the class of reproducible functions when specifying the first spline ffloins. The system contains a pulse generator, a frequency divider, two memory blocks, a switch core, a counter, two reversible counters, two AND elements, and an NOT element. 4 il. go with (

Description

bit and ending with the extreme right bit. With values of r 0 and uj 1, at step i of program i, counter 7 is working. The purpose of the invention is to increase the numbers. 5 in subtraction mode (at its input / up.

and computer science and is intended to reproduce functional dependencies.

and reproducible splines with a given amount of memory.

Figure 1 shows the block diagram of the proposed device; Fig. 2 shows a family of splines obtained by using the same and the same row of the memory block, and the corresponding code sequences; FIG. 3 is an example of the formation of splines of complex shape using the same line of the memory block (meaning the line with the information previously recorded in it); Fig. 4-- is an example of a piecewise approximated dependence being reproduced using only one line of the memory block (with information previously stored in it.

Digital gene; raTRP functions (CGF) contains a pulse generator, frequency divider 2, counter 3, block 4, memory, reversible counter 5, digital-to-analog converter 6, reverse, counter 7, elements 8 and 9, memory block 10, digital output of generator 11, analog output, generator 12, switches. 13. and 14, item NOT 1 5.

The device works as follows.

At each step i, the programs from the sixth and seventh outputs of memory block 4, respectively, to the control input of the switch 13, connected to the control input of the counter 7, and the control input to the switch. 14 arrive, respectively logical level rj and logical level i-. When specifying the uj value at all steps i. g 1 the state of the first input of the AND 9 connected to the input of the counter 3 repeats the state of the overflow (transfer) output of the counter 7, and the state of the second input of the AND 8 element repeats the state of the output of the block 10 memory . In this case, if in step i a line is selected containing a functional sequence of zeros and ones, then in the code of the GFR either the spline s () or

j-s f. 1: g7

s- (jpi 0), and the sequence

enters the second input element

There is a level zero), sequentially the address of the columns of the selected row of memory block 10 from the last to zero, and the transition to the next program step occurs upon arrival, to the second information input of the switch 13 and, accordingly, to the input of the counter 3 impulses from the zero reset (loan a) counter 7.

The second input element And 8 receives the sequence s. (Fig. 2) obtained from the sequence s by changing the reading direction and starting to read it (not the 0th bit of the 31st bit, but from the 31st to the 0th bit. The S / s spline is reproduced at the output of the GHF (with PI, O), a symmetric spline s with respect to the point C (Fig.2, the NC of the CC, the segment AK is equal to the number of units in S (in s), and AB is the number of bits in the sequence s. If s was reproduced on the iM step, and on (i + l) -M - s (Fig. 2, the division factor of the divider is 2 K | Kl), then they are symmetric about the point K. The view of s depends on the type of s, and it is unique, for example, if s isright positive

branch of a cubic parabola (figure 2),

then s is the left (negative) branch. cubic parabola. In the general case, s is a segment of a function negative with respect to a function

the segment of which is .s. There is a one-to-one correspondence such that for each s there is an s. the beginning and end of which coincide with the beginning and end of s, and

the points belonging to s are symmetric to the points belonging to s relative to the center of the segment that stretches the beginning: and the end of s (s) (Figures 2 and 3) are the splines stf and s, where

splines of a more complex shape than a segment of a cubic parabola are segments of polynomials of the sixth degree, and the tact j is the number of pulses arriving at the counting input of counter 7.

since the start of this step i of the program.

On program steps i from j: transition, to step i + 1, occurs on arrival

3. 1239704

to the input of the counter 3 pulses from the output of the overflow of the counter 7 (in this case

in block 10, the last column is addressed), and in steps i from r /, - 0, transition to step i + 1 is carried out on arrival at the input of counter 3 of the pulse from the zero output of counter 7 (in addition, in block 10 of memory addressed to zero

column J, which is provided by the operation of the switch 13, which connects to the 10 input of the counter 3, either the overflow output of the counter 7 (with r 1), or the output of zeroing the counter 7 (with) During playback of the complex dependence (Fig 4) when r changes with 15 I on О the sequence of numbers of addressed columns of block 10 of memory is next {for example, when the number of columns is:, .. 30,31,30 ..., and when r changes from O to 1 -, .. 1,0,1. . . . 20 If at the next steps of the program r- 0, then the following: the addressability of the numbers of the addressed columns of the memory block 10 is as follows: ... 2,1,0,21,30 .... Tawa About me

on but in AK

like

In this way, the spline s can be reproduced at any step of the program, regardless of the value of r at the previous steps.

With r ,, 1 and the second input of the element And 8, the following sequence of bone S, obtained by inverting

the states of each bit are in sequence s, since the output state of the element is NOT 15 and the output state of switch 14 is the same (the output state of switch 14 repeats the output state of element 15). This plays the spline s

and s (figure 2). The kind of spline s can. 40

be defined as follows. For

different from s

but

equalities 3 are satisfied

not

+

WITH;

th

,,,. 3

n

e

and n

one

respectively, the number of ones and zeros in the sequence s;

- respectively, the number of ones and zeros in the sequence is the number of bits in the sequence, (columns in the row of the block 0). what is equality

n ej + hj c

J

hb

Hj ej.

are executed for any Su /, where C, t, e. any time point t (any measure j, fig. 3) during the approximation section (program step) i (figure 2),

For the spline S (and for any spline defined by a sequence of zeros and ones), the number of ones in its corresponding sequence S determines the increment of the ordinate per section (AK, Figures 2 and 3, and the number of zeros in S determines AK, where AB - increment of the ordinate for the spline, which has all units in the defining sequence.It is obvious that for each t on segment i (i.e. for each vertical recovered from this point) the difference of the ordinates of the point on s and on the line is equal to the number of units , and the difference of the ordinates of a point on the line НВ and a point on s is the number lu zeros in that part of the sequence s

which is read from the beginning of plot i. The same is true for s. For the vertical AB, the following equalities are satisfied:

AK

five

0

five

0

five

Similarly, for a vertical reconstructed from an arbitrary point of cutter HA (for any t), the difference of the ordinates of a point by s and a point of a NP is equal to the difference of the ordinates of the same point of the NP and the point of s, where the NP is the segment connecting the origin of the spline s (coincides from the beginning, m of the spline s) and the middle of the vertical recovered from a point whose ordinate is equal to the ordinate of the start of the spline, and the abscissa is abc with the end of the spline, with the length of the vertices, ticked equal to C (the number of bits in the sequence defining s).

Hence the conclusion: .dl of any spline s t, -. Defined by a sequence of zeros and ones s, there is a uniquely defined spline s,. the determining sequence s. which is obtained by inverting the state of each bit in the sequence s, with s being the ratio

and s st s -f- t - s

where s. -functions from t, definite

s and pj values; K; C is the number of .bits .in the sequence. i; - time 5 starting from the beginning of step i.

With g ;; 0 and the proposed CFG reproduces the spline (Fig. 2), in which the determining sequence § is obtained from the sequence s by inverting its state. of each bit, or (which is the same) from the sequence s by changing-. the beginning and direction of its reading. (i.e., reverse of the sequence), because there is a one-to-one correspondence between s, s,, s and s (and, therefore, between s 5 s, s and defined by these sequences).

When Р (, 0 to each of the splines s,; ss and s, there is a spline, symmetric about the line ON, respectively, s, s, s and s (Fig. 2) which is defined by the same sequence of zeros and ones, but at this program step output reversing. counter 5 works in subtracting mode .1e

Figure 5 in more detail under the order

-, „2

forming four splines s, s,

s and s based on a single-row memory in block 10 with the sequence back.

Thus, at any step i of the program with the selected one by number - NJ; line of block 10 with a sequence of zeros of p {units (for example, s) pre-entered into it, the proposed GHF is capable of reproducing one of the eight slips, which is defined by the set of r, and Pi of the headquarters in fig.2j.

F o rm u l a and 3 o b e t. E to i

Digital-generator funktsrsh, sszder-: a pulse generator, frequency divider, counter, two reversible counters, two memory blocks, two elements And, the output of the pulse generator is connected to the information input of the frequency divider which is connected to the information input of the first reversible counter and first entry first element

This AND, the OUTPUT of which is connected to the counting input of the second reversible counter, the clock input of which is connected to the output of the second element I, the outputs of the bits of the first reversible counter are connected to the group of high-order bits of the address input of the first memory block, to the group of lower bits - the address input is connected to the outputs of the bits of the field of the rewriting address of the second memory block, the output of which is the field of the division factor of which is connected to the control input of the frequency divider, the output of the second reversible counter is connected to the address input of the second memory block, the output of which data field is connected. to the information input of the second reversible c-meter, the control input of which is connected to the output of the discharge field of the control field. The purpose of the function of the second memory unit, output. The control field for writing the second reversible counter is under the first input of the second And element, the output of the second reversing counter is connected to the output of the generator, characterized in that, in order to increase the number of PLAYBACK1- 1 splines for a given amount of memory, two com- maters, a mutator and an element are NOT entered, the first and second information inputs of the first switch are connected to the overflow output and the zero reset output of the first counter, respectively, output The first switch is connected to the first input of the second element I and the information input of the second reversible counter, the output of the bit of the address control field of the second memory block is connected to the control input 1 of the first reversible counter control and control inputs

the first switch-g the output of the first reversible memory block is connected to the first information one and through the element NOT to the second information inputs of the second switch, the control of which input is connected to the discharge output of the control field of the signal of the second memory block j the output of the second switch connected to the second input of the first element I.

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Editor E. Papp

Compiled by S. Kurosh Tehred L, Oleiik

Order 3397/49

Circulation 671

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, W-ZZ, Raushsk nab 4/5

Production and printing company, Uzhgorod, Project St., 4

Proofreader 0. Lugov

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Claims (1)

Claim A digital function generator comprising a pulse generator., A frequency divider, a counter, two reversible counters, two memory blocks, two AND elements, the output of the pulse generator being connected to the information input of the frequency divider, the output of which is connected to the information input of the first reversible counter and the first input of the first element And, the output of which is connected to the counting input of the second reversible counter, the clock input of which is connected to the output of the second element And, the outputs of the discharges of the first reversible counter are connected s to the group of high order bits of the address input of the first memory block, to the group of low order bits of the address input one, of which the outputs of the bits of the field of the rewrite address field of the second memory block are connected, the output of the • digit of the division ratio field is connected to the control input of the frequency divider, the output of the second 'reverse counter is connected to the address input of the second memory block, the output of the data field of which is connected to the information input of the second reversible counter, the reverse control input of which is connected to the output of the field discharge the board by incrementing the function of the second memory block, the output of the bit of the recording control field of the second reverse counter of which is connected to the first input of the second element AND, the output of the second reverse counter is connected to the output of the generator, characterized in that, in order to increase the number of reproduced splines for a given amount of memory, two commutators, a mutator, and an element NOT are introduced into it, and the first and second information inputs of the first switch are connected to the overflow output and the zeroing output of the first counter, respectively oh exit. the first switch is connected to the first input of the second AND element and the information input of the second reversible counter, the discharge output of the address control field of the second memory block is connected to the control input direction of the account of the first reversible counter and the control inputs of the first switch ^ the output of the first reversible memory block is connected to the first information and through the element NOT to the second information inputs of the second switch, the control input of which is connected to the discharge output of the polarity control field signal of the second memory unit, the output of the second switch is connected about to the second input of the first element I. 1 S ': 000000001001101 101 111 11111111111 S ² : Π 1111 f 11111/11011 oil 001 OOOOOCOO s': 11 f I 1 II 10 110010010000 000 000 oo 000 S *: oo000 00000000 ^ 01 00 100 1 10111 11 1 1 1. Fi & .2 Ν (κοβ) _ (Beat) s, ’: ΰ о о о s г о ϊ tioaoooo'oooooeooooiotio sf-.o ϊ icioaocfisocooooooeo? τ ι! ο i o o o o o o o S ?: f ϊ 1 IS J O O O o 1 1? 1 1 1 1) 1 ?! ί ί 1 1 1 О 1 О О 1 s *: 1 в О 1 1 1 J 1 1 ΐ? ί ί ί ί ί 1 ί! ! ? ? ! 8 t S f? f? ? .. Fall 3.