SU1374269A1 - Data transmitting and receiving apparatus - Google Patents

Abstract

The invention relates to the field of automation and can be used for the exchange of discrete information between asynchronous devices. The purpose of the invention is to increase the reliability of information transmission over a single bus by synchronizing the operation of the transmitting and receiving sides of the device from a single clock source, as well as by ensuring that the synchronization process of the logic circuits of the device is started only on the leading edge of the synchronization pulse. The principle of operation of the device is based on the fact that when writing to the counter 4 of the next information word on the information bus 2, it is allowed to pass such a number of clock pulses, which corresponds to the binary number recorded in the counter 4. Counter 12 counts the number of clock pulses passed on the data bus, and In this way, the code of the information word originally recorded in the counter 4 is formed in it. 2 Il. with S (L

Description

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The invention relates to automation and can be used to exchange discrete information between asynchronous devices.

The purpose of the invention is to increase the reliability of the transmitted information.

Figure 1 shows the functional diagram of the device for transmitting and receiving information; FIG. 2 shows an example of a realization of amplifiers of receiving and transmitting parties connected by an information bus.

The device for transmitting and receiving information contains (FIG. 1) the transmitting side 1, the information bus 2, the receiving side 3. The device on the transmitting side 1 contains the counter 4, the element NOT 5, the amplifier 6, the information inputs 7, the control 20 input 8, control output 9, on the receiving side - amplifier 10, pulse generator 11, counter 12, trigger 13, element OR 14, element 15,

The principle of operation of the device is based on the fact that when writing to the counter 4 of the next information word on bus 2, the number of clock pulses is allowed, which corresponds to the binary number recorded in counter 4. Counter 1 counts the number of pulses passed by W 2 clock pulses, and thus it forms the code of the information word originally recorded in counter 4.

The device works the next time.

In the initial state, the counters 4 and 12 are in the zero state from the output of the counter 4 by the level signal O through the element NOT 5, at the output 9 of the device, a clear information word is formed. In addition, at the same signal, through a cable 6 on bus 2, the lowest signal level is established. At the same time

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information inputs 16, which control 25 from the output of the element OR 14 by signal input 17, control output 18. Amplifier 6 contains an AND 19 element with a detector 20, and the amplifier 10 contains elements AND 21, OR-HE 22 and a resistor 23.

The counter 4 is intended to record the DA from the control signal from input 8 of the code of the information word coming from information inputs 7, decreasing it to zero by bitwise subtracting from the original value of the information word when a sequence of clock signals arrives from bus 2 and spinning the control signal to the input element NOT 5 and to the second input of the amplifier 6 when the code stored in the counter 4 reaches zero.

The pulse generator 11 is designed to output a sequence of clock pulses to the second input of the amplifier 10. The pulse generator 11 is triggered when there is a high level signal at the output of the And 15 element. If the output of the And 15 element has a low level signal, the operation of the pulse generator 11 is blocked completing the formation of the back front of the next sync pulse.

Counter 12 is designed to receive clock pulses from the data bus 2 and output a binary code of the number of received clock pulses to the outputs 16 of the device.

The level through the element AND 15 of the generator of the 11 pulses stops at the stage of completion of the formation of the trailing edge of the sync pulse

(at the output of the element OR NOT 22 - the front of the front clock),

When writing to the counter 4 by the input 7 of the information word, the control signal is removed under the control signal O, outputted by the input 8, the control signal is removed from the output of the counter 4, and when the control signal of input 8 is removed, the blocking low level is removed from the output of amplifier 6 As a result, the bus 2 produces a level 1 signal, on the front side of which the counter 12 is triggered from the output of the OR 14 element, and hence the low level stop signal disappears from the output of the AND 15 element, and the pulse generator 11 begins to generate string sequence sov. The sync pulses from the output of the generator 11 pulses through the amplifier 10 and bus 2 arrive at an input signal by subtracting counter 4, where on the falling front of each clock pulse the value of the stored code decreases. Simultaneously, from the bus 2, the sync pulses arrive at the input of the folded counter 12, where one is added to the front of the next clock pulse when the counter 12 is added to when the counters 4 and 12 arrive

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The principle of operation of the device is based on the fact that when writing to the counter 4 of the next information word on bus 2, it is allowed to pass such a number of clock pulses, which corresponds to the binary number recorded in counter 4. Counter 12 counts the number of bus pulses passed on the bus 2, and thus it forms the code of the information word originally recorded in counter 4.

The device works as follows.

In the initial state, the counters 4 and 12 are in the zero state; from the output of the counter 4, a level signal O via the element NOT 5 forms the request for the next information word on the device output 9. In addition, the lowest signal level is established via the signal 6 on bus 2 via the same signal. At the same time.

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25 from the output of the element OR 14 signal

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level through the element 15 and the operation of the pulse generator 11 stops at the stage of completion of the formation. no trailing edge

(at the output of the element OR NOT 22 - the leading edge of sync pulses),

When writing to the counter 4 via the inputs 7 of the information word, the control signal is removed from the output of the counter 4 by the control signal O, the control signal is removed from the output of the counter 4, and when the control signal is removed from input 8, the blocking low level is removed from the output of amplifier 6 As a result, a level 1 signal appears on bus 2, on the leading edge of which counter 12 is triggered, from the output of the OR 14 element, and hence from the output of the AND 15 element, the locking low level signal disappears, and the pulse generator 11 begins to generate follow nost clock. The clock pulses from the output of the generator 11 pulses through the amplifier 10 and the bus 2 are fed to the subtraction count 4, where, at the falling edge of each clock pulse, the value of the stored code decreases by one. Simultaneously, the sync pulses from the bus 2 arrive at the addition input of the counter 12, where, along the leading edge of the next sync pulse, one is added to the contents of the counter 12. When counters 4 and 12 arrive

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such a number of clock pulses, which is equal to the value of the binary number originally recorded in counter 4, from its output through the element NOT 5, the output 9 of the device receives the request signal of the next information word. In addition, the signal from the output of counter 4 sets the output of amplifier 6 to a constantly low signal level, which blocks the passage of clock pulses along bus 2 and, therefore, to the input of counter 12.

The situation when a low signal level is present on bus 2 and the output of the element OR NONE 22 amplifier 10 is a regular sync pulse is detected by the trigger 13 on the falling edge of this sync pulse (this is the first synch pulse at the output of the IL-HE 22 element after blocking the tire 2). As a result, from the first output of the trigger 13 to the output 18 of the device receives a reception request signal

information in the counter 12

the words. In addition, the same signal prohibits the passage of clock pulses through the element OR NOT 22, as a result of which the output of the amplifier 10 maintains a low signal level until the trigger 13 is reset to its initial state. Simultaneously from the second output of the trigger 13, the low level signal through the element 15 stops the generator

11 pulses at the stage of completion of the formation of the trailing edge of the sync pulse.

When the information word is read from the device outputs 16, a level 1 control signal is fed to the device input 17, through which the stored in the counter is reset.

12 information. When a signal is removed from input 17 at the output of the element OR 14, a level O signal appears, which through the element 15 generates 11 pulses in the locked state and resets the trigger 13, while the output of the element OR NOT 22 / level 1 appears (the signal from the generator output 11 pulses is inverted).

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Thus, the device becomes in the initial state until the next information word is written to the counter 4, the transmission of which to the counter 12 is performed in an anasogic manner.

Claims (1)

Invention Formula A device for transmitting and receiving information, containing on the transmitter side a counter, the output of which is connected to the input of the element NOT, the output of which is the first control output of the device amplifier, the output of which is connected to the information bus, on the receiving side - a pulse generator, counter, And element, the amplifier, the first output of which is connected to the information bus, the counter reset input is the second control input of the device, characterized in that, in order to increase the reliability of the transfer 30 but  ABOUT 40 45 The data inputs are information inputs of the device, the first control input of the device is the first input of the amplifier and the write input of the counter, the output of which is connected to the second input of the amplifier, the output of which is connected to the subtracting input of the counter, on the receiving side the trigger and the IHM element are entered , the information bus is connected to the trigger setup input and the counter addition input, the outputs of which are connected to the first inputs of the OR element and are information outputs of the device; the second input of the AND element And is the second control input of the device, the output of the OR element is connected to the first input of the AND element and to the reset input of the trigger, the first output of which is connected to the second input of the AND element, the output of which is connected through the pulse generator to the second input of the amplifier, the second output of which is connected to trigger trigger input, the second output of which is the second control output of the device.