RU1809536C - Device for decoding code - Google Patents

Abstract

The invention relates to computing. Its use in data transmission and reception networks makes it possible to increase the reliability of decoding by eliminating information loss. The device contains triggers 6-8, an element EXCLUSIVE OR 10; delay elements 11,12, element 14, and counter 15. Thanks to the introduction of a transition detector 2, a pulse shaper 3.17, a pulse distributor 4, OR elements 5, 13, a RAM block 9, and a pulse generator 16, information loss is eliminated in the device to the first 2T interval in the input signal. 4 ill.

Description

The invention relates to computer technology and is intended for use in data transmission and reception networks, in particular from emergency beacons from the Cospas-Sarsat space communications system.

The aim of the invention is to increase the reliability of decoding by eliminating information loss up to the first interval of 2 T.

Figure 1 shows a block diagram of a device for decoding a Manchester-2 code; Fig. 2,3 is a timing diagram illustrating the operation of the device; Fig. 4 shows circuit diagrams of the components included in the device.

A device for decoding a Manchester-2 code contains an input 1, a transition detector 2, a pulse shaper 3, a pulse distributor 4, an OR element 5, triggers 6 ... 8, a RAM block 9, an EXCLUSIVE OR 10 element, delay elements 11, 12 , element OR 13, element AND 14, counter 15 pulses, generator

16 pulses, driver 17 pulses, outputs 18, .. 20.

The input 1 of the device is connected to the information input of the RAM unit 9 and to the input of the transition detector 2, the output of which is connected to the input of the 3 pulse generator and to the input of the 4 pulse distributor. The outputs of the driver 3 and detector 2 are connected to the inputs of the OR logic element 5, the output of which is connected to the pulse input of the trigger 6, to the installation input of which the first output of the distributor 4 is connected. The output of the trigger 6 is connected to the D-input of the trigger 7 and through the driver

17 to the first input of the OR element 13, the output of which is connected to the clock input of the RAM block 9 and through the delay element 12 to the clock input of the address counter 15, The outputs of the 15 address counter are connected to the address inputs of the RAM block 9, and the overflow discharge output an address counter 15 is connected to its CI carry input and is the output 20 of the device. The second output of the distributor 4 is connected to the mode selection input of the RAM unit 9, to the input of the trigger 0 of the trigger 8 and to the input of the pulse generator 16, the output of which is connected to the second input of the OR element 13 and is the output of the device 18. The third output of the distributor 4 is connected to the installation input at 0 of the counter 15 addresses. The output of driver 3 is connected to the C-input of trigger 8, as well as to the first input of element And 14, and the source of logic 1 is connected to the D-input of trigger 8.

The inverse output of trigger 8 through a delay element 11 is connected to the second input of AND element 14, the output of which is connected to the C-input of trigger 7, the output of which is connected to the first input of EXCLUSIVE OR element 10, and the output of block 9 of the main memory is connected to its second input. The output of the EXCLUSIVE OR element 10 is the output 19 of the device.

0 Diagram 1 (Fig. 2) shows the initial signal with the initial LOG level. 1, Diagram 1 (Fig. 3) shows the signal with the initial LOG level. O. Diagram 2 shows the synchronization pulses. Charts 3 match

5 to the Manchester-2 code, obtained as a result of modulo 2 addition of the signals of diagrams 1 and 2. Figure 4 shows the formation of the main pulses for each difference in the Manchester-2 code. Figure 5 shows

0 formation of additional pulses in the event that after the last main pulse a time of approximately 1, 2 T has passed. On the diagrams 6 of the time diagrams of FIG. 2 and FIG.

5 records arising at the time of the trailing edge of each odd pulse (1st, 3rd, 5th, etc.) of the total sequence of the main and additional pulses. Figure 7 shows the process.

0 to determine the beginning of the information packet. The diagrams 8 of the time diagrams (Fig. 2 and Fig. 3) show the process of counting the main and additional pulses, which in this case reduces the determination of the even or odd number of main and additional pulses received from the beginning of the parcel. On diagrams 9 shows the process of fixing the parity of the received pulses (primary and secondary) with

0 the moment the parcel starts. The first db additional pulse fixes the parity (or oddness) of the number of the main ones received from the moment of sending the pulses. From the moment of the first fixation to

5 arrivals of each subsequent additional impulses, the sum of the main and additional impulses is always even (or odd), therefore, all subsequent additional impulses will confirm

0 parity (or oddness) established by the first additional impulse in the package. Diagrams 10 illustrate the process of recovering received information based on an input signal.

5 Transition detector 2 is made in the form of an EXCLUSIVE OR 21 element with an integrating circuit R1, C1 at the input (Fig. 4a), Shaper 3 contains a key 22, vfj kidney R2, C2, an inverter 23, a differentiating circuit 24, and an inverter 25 (FIG. 46).

The pulse distributor 4 contains a key 26, a chain R3, СЗ, a threshold element 27, an inverter 28, differentiating circuits 29, 30 (Fig. 4c).

The OR element 13 is an OR logic element with differentiating circuits at the inputs.

We consider the operation of the device in the following modes: initial state, as well as writing and reading information.

In the initial state, there is no signal to input 1. At the output of trigger 6 is a signal Log.O, at the inverse output of trigger 8 is a signal Log.1. The trigger 7 is in an arbitrary state.

When a signal arrives in the Manchester-2 code (diagrams 3 in FIGS. 2 and 3), the integrating circuit R1 C1 of the driver 2 (FIG. 4) delays the voltage variation at the second input of the unevenness element 21 compared to the voltage at the first input. As a result, at each difference in the input signal, the voltage levels at the inputs of the element of unevenness 21 become uneven for a time, which causes the appearance of the main pulse (plot 4 in FIGS. 2 and 3) at the output of the element 21,

The pulses from the output of the detector 2 cause the keys 22 and 26 to close in the shaper 3 (Fig. 4b) and the distributor 4 (Fig. 4c) and the fast discharge of the capacitors C2 and C3 to almost zero level. After the switches 22 and 26 are opened, the capacitors C2 and C3 begin to charge. At the same time, there is a capacitor in shaper 3. C2 manages to charge to the level of switching the inverter 23 by about 1.2 T, and in the distributor 4, the co-driver S3 manages to charge to the level of switching of the threshold device 27 in a time approximately equal to (2.5i3) T. Thus, if time equal to approximately 1, 2T has passed from the moment of the last input signal difference, then an additional pulse will appear at the output of the shaper 3 (plot 5 in FIGS. 2 and 3).

During the receipt of the information packet, the capacitor C3, switched by the key 26, does not have time to charge, and at the output of the threshold device 27 (output P) there is a signal Log. 1 (diagram 7 in FIGS. 2 and 3), which allows trigger 8 to be triggered when the first additional pulse arrives at its input, and also allows the RAM unit 9 to record information.

In addition, the pulse from the third output of the distributor 4 sets the counter 15 addresses to 0.

The main and additional pulses, coming through the circuit 5 OR to the input of the trigger 6, trigger the last (plot 8 in figure 2 and 3). The signal from the output of trigger 6 is fed to the second input of the OR element 13, in which pulses are generated corresponding to the leading edges of the signal from trigger 6 (diagrams 6 in Figs. 2 and 3). These pulses arriving at the C-input of the RAM unit 9 record information arriving at the D-input into it at the addresses that are set using the address counter 15.

It should be noted that the following feature of the proposed device is obvious from FIGS. 2 and FIG. H. If the initial state of the Mznchester-2 code corresponds to Log.O (diagram 3 in FIG. 2), then before the appearance of the first additional pulse, an even number of main pulses has time to form (diagram 4 in FIG. 2) and the information in the RAM block 9 is written in the direct code (plot 10 in FIG. 2). If the initial state of the Manchester-2 code corresponds to Log, 1 (plot 3 in FIG. 3), then before the appearance of the first additional pulse, an odd number of main pulses have time to form (plot 4 in FIG. 3), and the information in the RAM unit 9 This will be written in the inverse code (plot 10 in FIG. 3).

On the leading edge of the first additional pulse entering through the open element 14 And on the C-input of the trigger 7, the installation of the latter (Epure 9 in figure 2 and 3). If an even number of main pulses has arrived before the first additional pulse, then trigger 7 is set to Log.O (diagram 9 in Fig. 2). The trailing edge of the first additional pulse D-flip-flop 8 in accordance with the constant level Log.1 at its D-input, is set at the inverse input to the state Log.O. Thus, the And element 14 is closed, subsequent additional pulses do not affect the state of the trigger 7, as well as the state of the trigger 8,

If an odd number of main pulses arrived before the first additional pulse (Figures 4 and 5 in Fig. 3), then trigger 7 is set to Log by an additional pulse. 1 (plot 9 in FIG. 3). The blocking of this state occurs as described above.

At the end of the flow of information to the input 1 of the device after a time (2, 5 ... 3) T, two control signals are generated at the outputs of the distributor 3 (Fig. 4c). First pulse signal through

the differentiating circuit 30 (output 1) sets to Log.O trigger 6, the second potential (output P) sets to Log.O trigger 8. The device returns to its initial state.

Reading information from the main memory unit 9 occurs after the end of the information by starting the pulse generator 16 with a signal from the second output of the distributor 4. The main memory unit 9 goes into read mode. Pulses from the output of element 13 are received at the clock input of block 9, and also through the delay element 12, at the counting input of address counter 15, as a result of which the recorded information is read out from the output of block 9 through the element EXCLUSIVE OR.

Depending on the state of trigger 7, data is output from element 10 either in the forward code, as recorded in block 9, or in the reverse. The latter case corresponds to writing data to block 9 in the reverse code (plot 10 in FIG. 3). After double conversion, the information at the output of the device appears directly.

The outputs 18 and 20 of the device also receive, respectively, pulses from the output of the generator 16, necessary for gating the information read from the memory block 9 for subsequent processing, as well as an overflow signal of the address counter 15, which serves to determine the beginning of the information repeatedly read from the information block 9.

Thus, regardless of what initial level the information in the Manchester-2 code began to come from, the proposed device provides lossless transmission of the transmitted information in full in the direct code. This is the technical and economic advantages of the proposed device for decoding the Manchester-2 code in comparison with the prototype and other similar solutions.

Claims (1)

SUMMARY OF THE INVENTION A device for decoding a Manchester-2 code, comprising first to third triggers, the output of the third trigger is connected with the input of the first delay element, the second delay element, the AND element, the EXCLUSIVE OR element, and a counter, characterized in that, in order to increase decoding reliability due to reduction of information losses, a RAM block, a pulse distributor, a pulse generator, pulse shapers, OR elements and a transition detector, the input of which is combined with the information input of the RAM block and is the input of the detector, are inserted into the device, into the device transitions connected to the first input the first OR element, the input of the pulse distributor and the input of the first pulse shaper, the output of which is connected to the second input of the first OR element, the first input of the And element and the C-input of the third trigger, the D-input of which is connected to the source of a logical unit, the output of the first delay element is connected to the second input of the element And, the output of which is connected to the C-input of the second trigger, the output of which connected to the first input of the EXCLUSIVE OR element, the output of the first OR element is connected to the C-input of the first trigger, the first output of the pulse distributor is connected to the R-input of the first the trigger / output of which is connected to the D-input of the second trigger and the input of the second pulse shaper, the output of which is connected to the first input of the second OR element, the output of which is directly and through the second delay element is connected respectively to the clock input of the random access memory block and the counting input of the counter, the second output of the pulse distributor is connected to the input of the mode selection RAM unit and the input of the pulse generator, the output of which is connected to the second input of the second OR element and is the clock output of the device, the third output of the pulse distributor connected to the counter zeroing input, the bit outputs of which are connected to the address inputs of the random access memory block, the output of which is connected to the second input of the EXCLUSIVE OR element, the output of which is the information output of the device, the counter overflow output is the synchronization output of the device. p # & 3 fi + Ugg / t W Editor Compiled by L. Olyshevsk Tehred M. Morgenthal Corrector L. Livrints JTffi X. fie.b