SU1597904A1 - Device for recording digital information - Google Patents

Abstract

The invention relates to magnetic recording, in particular, devices for recording digital information. The goal is to simplify the design. In the device, only three of the eight bits of the source information are transcoded (two bits less than the known). At the same time, the coded part size is also reduced to 4 bits instead of eight. As a result, the amount of permanent memory is significantly reduced and, consequently, performance is improved (power consumption, reliability). 1 il.

Description

The invention relates to the field of magnetic recording, in particular to devices for recording digital information.

The purpose of the invention is to simplify the device.

The drawing shows a functional diagram of the device for recording digital information.

A device for recording digital information contains a block 1 of synchronization and reception of digital information, the first and second inputs of which are the inputs of the device, to which the digital information signal and clock pulses, respectively, also arrive at the first input of the first AND element of the first 2I-OR-2, and the first output is connected to the first inputs of the second element AND the first 2 and second 3 elements 2И-OR, the third output is connected to the installation input of the higher bits of the counter 5 and interrogation of the fixed memory block 6, part of the information on the outputs of the installation. The small bits of the counter 5 and the address input of the block are fixed memory; the outputs of the counter 5 are connected to the inputs of the OR element 7, the output of which is connected to the second inputs of the second and first circuits of the first and second elements 2I-OR 2 and 3, respectively, and through the element NOT 8 - with the first input of the element AND 4 and the second inputs of the first and second elements AND, the first 2 and second 3 elements 2И-OR respectively, in addition, the output of the first element 2И-OR connected to the clock inputs of the counter 5 and shift p The register 9, and the output of the second element 2I-OR is connected to the output of the counting trigger 10, to one of whose arms is connected, the recording amplifier 11, the output of which is the second output of the device, the cyclic transfer input of the shift register 9 is connected to the output of the And 4 element, the output connected to the second input of the AND 4 element and the first input of the first circuit and the second element 2I-OR 3, and the output of the fixed memory blocks 6 with the installation inputs of the higher bits of the shift register 9 and

with

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Moreover, the third output and the remaining part of the information outputs of the synchronization and reception of digital information block 1, including the information output that is the least significant bit to the address of the polling of the fixed memory block, are connected to the corresponding ones Dov shift register 9.

The device provides the formation of a recording signal with an information capacity of 1.6 bits for a minimum period with the possibility of drying, including both clock and group self-synchronization of the playback signal. Functionally, the recording signal is formed by dividing the initial information into groups of eight bits. The resulting groups are converted to decimal code groups, of which the recording signal is formed by a non-zero method. In the process of conversion, first of three of the eight bits of the initial information, a four-bit basic code is formed, to which the values of the three bits of the code to be converted are added, including one of the bits at the beginning of the bits used and the code "O" 1, then cyclic shift is performed in accordance with the code value of the remaining three bits of the original information, resulting in a nine-bit code from which the write signal is formed.

The sync pulses and information signals, coming to the inputs of the synchronization and reception unit 1 of digital information, also provide for the generation of clock pulses and group synchronization pulses of the device (respectively, the second and third outputs of the synchronization unit 1 and reception of digital information) and the eight-bit parallel code of the initial information issued simultaneously with group synchronization pulse.

A group synchronization pulse sets two high-order bits of counter 5 to zero, and the code of the first three bits of the initial information is written to the three low-order bits. The next three bits (fourth, fifth, and sixth) are written to the second, third, and fifth bits of the shift register 9, respectively. In addition, the sixth bit of the original information with the two remaining (seventh and eighth) and group synchronization impulses is fed to the inputs interrogation of block 6 of the permanent memory, and the code from its output is recorded in the four most significant bits (6 ... 9 bits) of the shift register 9. In the fourth bit of the shift register 9, the code unit is recorded, and the least significant bit remains in zero condition. The codes stored in block 6 of the permanent memory with the corresponding addresses are listed in the table.

Now, since the high-order bits of counter 5 are zeroed, the output of the element OR 7 will be a zero signal, and the output of the element NO 8 will be the signal “b. As a result, the element AND 4, as well as the first and second elements AND, respectively, of the first 2 and second 3 elements 2I-OR will be open, and the second and first elements AND, respectively, 0 elements 2I-OR will be closed. Thus, the clock input of the shift register 9 will receive a sync signal from the device input through the first element 2I- OR 2, and element 4 will close the cyclic transfer circuit of the 5th shift register 9. Until the low bits of the counter 5 overflow (from one to eight clock cycles), a cyclic shift of the codes on the shift register 9 will occur, and the output of the element OR 7 is zero. In the same time period, the second element 2I-OR 3 will receive a signal from the second (clock) output of the synchronization unit 1 and receiving digital information to the input of the counting trigger, which will ultimately lead to a change in the signal at the amplifier output 11 entries.

Further, as soon as in the fourth discharge of counter 5, the signal “1” appears, which corresponds to the overflow of three lower orders, by the changed signal from the output of the element OR 7, the device will switch, resulting in the AND 4 element. The first and second elements AND, respectively, of the first 2 and second 3 elements 2I-OR will be closed, and the second and first elements 45 And of the same, respectively, elements will open. Now, the clock input of the shift register 9 will receive the clock pulses from the second output of the synchronization unit 1 and receive digital information, the cyclic transfer circuit will open and the code signal from the output of the shift register 9 through the second element 2I-OR 3 will be fed to the trigger input 10, thereby ensuring the formation of a recording signal.

50

55

Thus, during one cycle of operation of the circuit, a recording signal is generated with a ratio of time intervals between adjacent switches

ten

1: 2: 3: 4 and information capacity of 1.6 ry inputs of the second and first elements of the initial information on the minimum And the first and second elements 2I - the period of the recording signal. In this case, in each OR, respectively, and through the element NOT - with

the tenth (first) operation cycle in the signal input of the And element and the second record will necessarily switch, that g dami of the first and second element And the first provides group synchronization and second element 2И-OR, respectively, the output of the first element 2И-OR connected to the clock inputs of the counter and shift register, the output of the second element 2I-OR - with the input of the counting trigger, to one of the arms of which a recording amplifier is connected, the output of which is the second output of the device, cyclic transfer transfer input The needle register is connected to the output element of the digital information signal and the sync I, the output of the shift register is connected to the pulses that also come to the first input to the second input of the AND element and the first

the input of the first element AND the second element 2I-OR, and the outputs of the block of permanent memory - with the installation inputs of the higher bits of the shift register, the distinctive inputs of the second elements AND AND the fact that, in order to simplify the initial and second elements 2I - OR, third parties, third exit and remaining part

the information outputs of the synchronization and reception of digital information, including the information output, the outputs are connected to the outputs of the lower-order bits in the address of the counter's past bits and the address input of the fixed memory block, in addition to the constant block memory, at the same time connected to the corresponding input outputs of the counter connected to the inputs of the ele-mn installation of the lower bits of the shift OR, the output of which is connected to the second register.

during playback.

Claims (1)

Invention Formula A device for recording digital information containing a synchronization unit and receiving digital information, the first and second inputs of which are the inputs of the device to which the respective input of the first element AND of the first element 2I-OR is received, and the first input is the output of information request requests to the device, the second the output is connected to the first one; it is connected to the input of the installation of the higher bits of the counter and interrogation of the block of permanent memory, part of the information