SU1653169A1 - Dibit signal transmission device - Google Patents

Abstract

This invention relates to a digital signal switching technique. The purpose of the invention is to increase noise immunity by converting binary signals into bi-pulse. The device contains a signal accumulation unit 1, a read counter 2, a signal output unit 3, a signal conversion unit 4, a write counter 5, an output register 6. The information signals received at the 2nd input of the device along with the address of the outgoing line are recorded in the accumulation unit 1 in a cell corresponding to the number of the outgoing line, from where then through the signal conversion unit 4 is written into the signal output unit 3. Blocks 3 and 4 convert information to all outgoing lines into a relative binpulse signal, and this conversion is performed at the same time across all channels. When the length of information is equal to N bits, the formation of a binmpulse signal takes 2N cycles. Full conversion of signals in all channels takes 2N cycles of counter 2 reading, and for every two cycles, one bit is converted in all channels, 3 sludge. (I

Description

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About CD

The invention relates to communication technology and can be used in digital switching systems.

The aim of the invention is to improve noise immunity by converting binary signals to bi-pulse.

Fig. 1 shows a structural electrical circuit of a device for transmitting bi-pulse signals; in fig. 2 is a structural electrical circuit of the signal accumulation unit; FLG contains a structural electrical circuit of the signal conversion unit.

The bi-pulse transmission device contains a signal accumulation unit 1, a read counter 2, a signal output unit 3, a signal conversion unit 4, a write counter 5, an output register 6.

The signal accumulation unit 1 contains (Fig. 2) a memory unit 1-1, a register 1-2, a comparison element 1-3, an AND element 1-4.

The signal conversion unit 4 comprises the first and second triggers 4-1, 4-2, the first elements AND 4-3, the first elements OR 4-4, the third triggers 4-5, the second and third elements AND 4-6 and 4-7, the second and third elements are OR 4-8 and 4-9, the first element is NOT 4-10, the element IS NOT 4-11, the second element is NOT 4-12.

The device for transmitting bi-pulse signals works as follows.

The control inputs of the accumulation unit 1 receive control and interaction service signals (information I) along with the signal (at 1 and the addresses A (numbers) of the outgoing communication lines to which these signals need to be issued, and are written into the corresponding memory cells). In this case, the number of memory cells in the signal accumulation unit 1 corresponds to the number of outgoing communication lines assigned to them.The conversion of the service signals from the binary code to the bi-pulse code and their bitwise output to the outgoing communication lines is carried out Signal conversion unit 4 and signal output unit 3. Until previous service signals are issued from signal output unit 3 on the communication line, new signals are stored in signal accumulation unit 1.

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The overwriting of new service signals from the signal accumulation unit 1 to the signal output unit 3 is performed using the read 2 and write 5 counters, as well as the signal conversion unit 4.

The counters of reading 2 and record 5 electrically represent one counter, the lower bits of which constitute the bits of the counter 2 reading, and the four old bits - the bits of the trigger 5 records. The synchronization of the operation of the device is fully ensured with the help of read counters 2 and write 5 operating at the station generator frequency f.

The read counter 2 generates the write and read signals for the signal accumulation unit 1 and the signal output unit 3, the read signal also goes to the signal conversion unit 4 and the output register 6.

The reading counter 2 also generates the addresses (numbers) of the memory cells from which information is read (written).

The read counter 2 has m + 1 bits, of which n (n 7) most significant bits determine the cell address of the memory block 1.3 n one least significant bit - the trigger generates from its

the right shoulder (zero) signal read neither 6c-p, and from the left - the recording signal

Ј, „. Thus, the reading counter 2 provides continuous cyclic reading and writing of information. In this case, for one reference to the accumulation units 1 and the issuance of 3 signals, information is first read from the i-th memory cell, and then written to the same i-th memory cell. The total cycle for accessing accumulation blocks 1 and issuing 3 signals consists of N specified private access, where N is the number of memory cells in accumulation blocks 1 and 3 signals, that is, all memory cells of these blocks will be read and written during the common cycle The number of such common cycles is calculated by the record counter 5, which for this purpose receives signals from the high-order output of counter 2 reading about

Record the information And from the control unit of the switching system (CU) into the memory cells of the signal accumulation unit 1 using the address A and

recording cycle with.

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from read counter 2, proceed as follows. The address A from the control unit and the address A from the reading counter 2 goes to the comparison element 1-3 (Fig. 2). If the addresses are the same, then the signal OJ - 1 from the output of the comparison element 1-3 opens the element AND 1-4, to which the signal 0. 1 and the cycle also arrive.

0 In this cycle Ј% p passes through the element I 1-4 and provides the recording of information And from the CU into the memory cell of the memory block 1-1 at address A. The information read from memory block 1-1 is written to the register 1-2 on which it is stored until the next clock cycle. The reading of information from memory block 1-1 is carried out with the use of

by the power of the address A and the clock Јcht from the reading counter 2 (see figure 1).

In order to convert and transfer to the communication line one service signal, which has eight bits, and each bit, when converting it from binary code to bn-pulse, is transmitted to output register 6 two times, 16 total cycles are necessary, which are counted using a four-bit counter 5 record.

The low-order bit of the write counter 5 determines the conversion of one bit of the signal and generates a pass (L), which enters the signal output unit 3 via the signal conversion unit 4.

The signal conversion unit 4 generates with the help of the element AND-NOT 4-11 and the element NOT 4-12 the signals di and оЈ. The signal About 1 is generated at those times when all four zero levers of the triggers of the record 5 counter are 1, i.e. & 1111.

The sixteenth cycle is performed through the corresponding AND 4-3 and OR 4-4 elements of the signal conversion unit 4 and overwrites the new cycle of service signals from the memory cells of the signal accumulation unit 1 through the triggers 4-5 of the signal conversion unit 4 and the corresponding And 4-6 elements, OR 4–9 per cell of the signal emitting unit 3.

If at least one of the bits of the record 5 counter, defining the signal ftd 1111, is equal to 0, then a signal of about 1 is generated. In case (2 1 recording is performed on the trigger 10

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4-5 of block 4 of information from block 3 of signal output.

The control of the recording of information on the triggers 4-5 is performed using the read signal Јcht from the counter 2 reading.

The signals and A are read out from the signal output unit 3 and are recorded in the signal conversion unit 4 by pausing the triggers 4-1 and 4-2 using a control signal

The conversion of binary (binary) service signals into bi-pulse signals and their bit-wise output in the communication line is performed as follows.

The service signals are cyclically read by the read counter 2 from the memory cells of the signal output unit 3 and are fed to the signal conversion unit 4. The number of memory cells of the signal output unit 3 corresponds to the number of communication lines assigned to these cells. The numbers of the communication lines and memory cells are the same. In the memory cells of the signal output unit 3, service signals and signs (signals) y and {binary code conversion, un-pulse, are stored.

Each bit (bit) of the binary service signal is converted and output to the corresponding communication line twice at the beginning and in the middle of its pulse. Therefore, reading of all the cells of the signal output unit 3 takes place in a cycle equal to half the pulse duration of one binary bit. .

In order to distinguish which time (first or second) the same binary bit is read and converted into a bi-pulse code, the sign / 3 transformation is entered

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45 of the beginning (leading edge) and midpoint of the binary bit of the service signal, If / 3 1, the leading edge is converted, and at (0, the middle 50 of the binary bit is converted.

 Since the relative bi-pulse signal is output to the line, when converting the binary digits of the service signal into the bi-pulse code, it is also necessary to know the polarity of the previous bi-pulse discharge given to the communication line. This polarity corresponds to the state of the communication line.

For this connection, the state of the line V is set. If Y is 1, then the line is called: D is state 1, and when Y is 0, the line is 0

The pulse of each binary unit of the eight-bit service signal by its leading edge changes the polarity of the corresponding bit of the bi-pulse service signal, which is realized with the help of the element AND 4-7 (average) OR 4-8 at | 3 1, G 0 and with the help of all elements AND 4-7, OR 4-8 at ft 1, 1, i.e. at the outputs of all elements AND 4-7 there will be zeros at this moment in time.

The pulse of each binary 0 signal served by its leading edge does not change the polarity of the bi-pulse signal, which is realized by the plots of AND 4-7 (right) or 4-8 at) f 1 P 1 elements and with the help of all AND elements 4-7, or 4-8 at

At O h 1 tvo at the outputs of all elements And at this moment the time will be zeros.

In the middle of a binary 1 and 0 pulse, the polarity of the corresponding bits of the bi-pulse signal is always changed, which is realized with the elements AND 4-7 (left), OR 4-8 with y O, and the binary O and with the help of all the elements And 4-7, or 4-8 at O, U 1 and binary 1, i.e. at the outputs of all elements And 4-7 at this point in time will be zeros.

Thus, the conversion of each binary bit into a bi-pulse code is performed in the signal conversion register 4 as follows.

After the next bit of the bin-pulse service signal is output to the communication line, the value of the characteristic rt changes to the opposite, and the value of the characteristic I is equal to the new state of the communication line. These new values of feature A are recorded in the signal output unit 3.

The information recorded in the signal conversion unit 4 is then fed to the inputs of the signal output unit 3 through the elements AND 4-6, 4-7, the elements OR 4-8, 4-9 and the element NOT 4-10 (FIG. 3). Since in the communication line the service signals are issued sequentially, the discharge after discharge and each discharge is read from block 3

issuing signals twice, then after the second issue of the next one, for example, the first bit, when recording the sign $ 1 in the signal output unit 3, all the service signal bits are also written to this block with a shift by one bit to the left

Claims (1)

In this case, the first bit becomes the last (eighth), and the second bit becomes the first, which is prepared in this way for sobbing into the communication line. The output to the communication line through the output register 6 is performed by the same bit that is recorded first. The process of issuing and shifting the service signal bits to the left is cyclic. At the same time, if a new signal is not received in block 1 of signal accumulation, the old signal is rewritten from block 1 of accumulation of signals to block 3 and a cyclic signal is output to the communication line again and hours, which increases the noise immunity of transmission of service signals sp zi Invention Formula A biopulse signal transmission device comprising a signal accumulation unit, a signal output unit and an output register, characterized in that, in order to increase the noise immunity by converting binary signals to binpulse signals, a signal conversion unit, a read counter and a write counter, whose output connected to the first input of the signal conditioning unit, the first output of which is connected to the first inputs of the signal output unit and the output register, the second and third passages of which are connected respectively to the first and second outputs of the reading counter, the third output of which is connected to the first input of the signal accumulation unit and the second input of the signal output unit, the third and fourth inputs of which are connected respectively to the first and second outputs of the reading counter and the second and third inputs of the signal accumulation unit, the output of which is connected to the second input of the signal conversion unit, the third input of which is connected to the second input of the output register, the input of the record counter is connected to the second output of the reading counter, the second output signal conversion unit connected to the fifth input of the signal output unit, the output of which is connected to the fourth input of the signal conversion unit. from WOW