SU1193812A1 - Phase shift-to-digital converter - Google Patents

Abstract

CONVERT: LESSING THE PHASE into a code containing the first and second pulse shapers whose inputs are connected to the input source, the first trigger, the output of the second pulse shaper connected to one input of the first element I, the output of which is connected to the counting input of the second trigger, the outputs of the first and The second trigger through the first and second differentiation elements are connected to the inputs of the third trigger, the output of which is connected to one input of the second element I, the other input of which is connected to the output of the generator pulse, and the output is connected to the counting input of the first counter, the outputs of the first counter through the first decoder are connected to another input of the first element, And the second counter, the installation input of which is connected to the installation input of the first counter, the zero input of the first trigger, connected to zero input of the second trigger, characterized in that, with the speed of performance, the second decoder, memory block, nepBbrfi, second, third and quarter registers, adder, first, second, third and fourth blocks of the AND elements are entered into it , the third counter, the first) and the second delay elements, the ILBi element, the input of the first pulse driver is connected to the counting input of the first trigger, the outputs of the first and second differential elements are connected to the read inputs and the memory module E1 or to the counting input of the second the counter, the outputs of which are connected to the address input of the memory unit, and through BTopoft § the decoder - to the zero input of the first (first trigger, input of the first delay element, the first input of the first block of elements Nick zero inputs of the first and registers, the second input of the first block of elements AND connect it to the potential zero bus, the remaining inputs - to the outputs of the first: the counter, the first group of PCs of the elementary I blocks connected to the first group of inputs of the adder, and the second group of outputs to informational inputs The third counter, N3 counting input of which is connected to the output of the second element G1, and the outputs are connected to the second group of inputs of the adder and to the information inputs of the second block of elements And, the outputs of the second block of elements And connected to the information the third register inputs, the outputs of which are connected to the information inputs of the memory block, the outputs of the memory block connected to the information inputs of the second register, the outputs of which are connected

Description

to the third group of inputs of the adder, 1 input; sum 1 or 1; 1, key; to jn-formation: np - 1 inputs of the third block of I- elements, KOToiDoro outputs connected to the inputs of the fourth register j, outputs of the fourth register are connected to C) Converted code and to the information 5151-1-1 inputs of the fourth block of elements I, a; - -. 1 whose courses are connected to the information, the first register, the first one

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regis)., to the public:; transitions from: ummatp) a, ak p; ijo differentiating from one element to the controllers X ;; d and th and third ojiOKOB:) through the second ed (; kent overdrc control input q o ka g of elements and n to ust-avovo-) Bxojxy g nggygs schechch, and go elsm (-nga chad.e:) LCD-1: i.) dk: 1H ;; NO 1-tsechno; chu INPUT psrzogo scheggch

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Invention refers to automation and computational technology; and can be used for analogue from sources of infrastructure / ian with G1Ifrovy vygchksde.pnym at article:

 invention - nojibmieiuie speed transform phase shift to code:

In the drawing, the led-on structural scheme of the proposed gptaoorazovatsl

11conversion.gr contains sources 1 of signals (phase-shifted. /, O / t, the output of which through 1 tormirshatai impuns connected to cncTiibiM 15khod.) Trigger.), A. friend -; through serially connected forms: 1b 4 innigs and glemeng ii :) - with a countable input of the trigger o,; s of the trigger 3 and 6 through the dig; Lend ru10 hie element; / g. 5, form-guu-o; ;;; ir ms yro ibHbie narrowly. ipulse with jicui.): output differences D: with triggering trigger pads, connected to the set HB (with trigger inputs 9, and through the WL 10 switch - with the counting input of the counter 1 1, D reiUiparopa : ./: pulses, generated ayushche; -o.; with coal 1 mpulsy. -1111y frequency through the element And 13 soy.dg1ien with the counting of the input 1.sh counters i a. and 15. The control input of the element And 13 is connected to trigger output 9., Counter codes 14 are connected, through decoder 16 with the control input of the element 5, and through block 1 of the elements of the I with information inputs and inputs of the counter 15 and the first group of the inputs of the adder 18. Input, s read and write block 19 of memory with HJiUirlli With outputs DI1phereN, I; U101: THEM

3j.ieMiii: oii 7 and 8, address :; hol: l with sbij-odds counter 1., is; keys le; Issue J and informational and; ixc, ;; s; i - cooiBeTCraCHiKj with nkhodagchp; e; Istra 20 and C: out.; 1; Am 5 register:, Bxo; ti pei-Istra 21 through bl;: Approx. .: Part 5 II are connected to the second group HOII χ (; Dov oym; atopa 18 and infory a-C1-1: HNKg-11: BMDI C4t-iiHKa:., and Л:. :: o; ii.; register 2 ;: soe / ignign ;. r pej-jjft ipyiiioii enter the sum of: -ora G-, et ertai and p / nia of the inputs of sum-o:,.-i 2 with..M: -f i- i. I-: jb) .xo : aMi-i register c .: a, b. - (Slice. -1: :;; ..;:.:. Sudii), 3.; i:.; K / o el;; - items e-i and i. Entry and RSL -1otru 2 ;, Exo; i ol; .-; a 9 and amkg ;; this overhang ;;; ;. connected (-11ran.chlyui; 14M., chmi (.KI-H .; .2 i;.: J; sjieM (о ;; V; ii through part 27 of the end; 1 with the control oh odem ;; oaoka 2o ed; emen: h) in I and with us: ta; 1 skoiiiiiji--. BXi.;.; I.oM c-) ef4WKa 15. B DG j account chikg il decoder 28 connect Ga, .B;) with H ; - The left i inputs pi-i g; .h ;;) 3 ii ii regist1) o 2 (1; 22, with the spy enter the block i / element go}}; t y, with the input ojiGMeHTa 29 zadarhg. .O / htotorO1-s; 1: one unit with a mustache: ano-input input of counter 14 and counter 11. The second input of unit 17 is connected to the 1PINE 30 zero-potential.

Block 17 of malicious elements And consists of ha + 1 elements I. Where m is the number of bits of the counter 14. The first inputs of the elements And block 1 7 are connected to the first CARE. ;). The second entrances of the I and I elements are with trgm inputs 3 of the block 17. The second input of one of the elements of AND 17 is connected to the second input of block 17 and to the potential potential zero bus, and the output of this element I to one of the second; the outputs of block 17 and with the information input of the higher bit of the counter p - 1 outputs of the elements I (where p is the number of bits of the counter 15) are connected to the second outputs of block 17, and the rest - to the first outputs of block 17, the adder consists of three combinational adders The first combinator combinator consists of p bits, the second combiner adder consists of (t - p + 1) bits, and the third one consists of m bits. The first and second group of inputs of the first combinational adder are connected respectively to the second and third groups of inputs of the adder 18. The output of the higher bit of the first combi national adder is connected to BTOpo i by the group of inputs of the second combi adder, the first group of inputs of which is connected to the first group of inputs of the adder 18. The first group of inputs of the lower bits of the third combinational summat1) a is connected to the outputs p-1 of the lower digits of the first combi fiauHOHHoro adder, and the rest of the inputs of the higher bits are from the outputs of the third combination of an adder. The second group of inputs of the third combinational adder is connected to the fourth rpynnoii HXOZIOB adder 18, and vkho ;; b - to the outputs of the adder. The converter works as follows. At the end of the previous nickel, after the initialization of all the triggers, the counter and the registers, the output signal of the source 1 of the signals through the shaper 2, generating start-impulse :, sets the counting trigger 3 to the unit state. The impulse formed from the positive differential of trigger 3 by differentiating element 7 establishes three reii 9 to one personal state, which is opened by the E.sup.E 13 and generator i 2 impulses are sent to counters i4 and; 5. When the code-b counter 1A is 1p € -p; the value corresponding to half the full value of the phase, the decoder 16 opens the element AND 5, allowing the passage of stop pulses from the driver 4 to the counting input of the trigger 6. Divided into two by the trigger 6 and formed by 4x |) Evaluating the element 8, the stop pulses set the trigger 9 to the zero state by closing the element H 13 and stopping the arrival of the pulses from the generator 12 until the next start-pulse. If the measured phase shift at the beginning of the measurement cycle is less than half the full value of the phase, then iiiirai immediately after the start-impulse. If the stop pulse is eliminated if the EU; if the measured phase shift exceeds half the full value of the phase shift, then the measured phase shift is taken from the start pulse to the highest stop pulse, and this operating principle is maintained until the end of the current cycle. The start and stop pulses, divided into two triggers 3 and 6, through the i-UDi 10 element enter counter 11. The measurement cycle ends after the η-fold instantaneous measurement of BeiiHOio phase shift values. The sum MaiMibul p-fold measurement code accumulates in counter 14, the count of the measurement number is performed by counter 1, where the number 2n + 1 is collected at the end of the measurement cycle. The output of the decoder 28 is triggered, resetting the triggers 3 and 6, registers 20 and 23. and through delay element 29, counters 14 and 11. On counter 5 after ka:; the current phase value code is set after the measurement. The pulses from the output of the differentiating element 8 through the block 22 of the elements And the code from the counter 15 is rewritten into the register 21, after which the counter 15 is zeroed. The same pulses are used to write down or parallel write to 6: ioK 19 memory of register code 21. jV; write pec is generated by g; bit 11. The low-order bit of counter 11 does not participate in the formation of the address of the write and write code. The first current phase code in the cycle is recorded at the first address, and the (n-1) -th current phase code at the (n-1) th address. The current code of the nth measurement is not recorded in memory block 19.

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therefore, block 19 may have no more than n-1 addresses.

Reading from memory block 19 begins simultaneously with the start of the current phase measurement and is produced by pulses formed by differentiating element 7.

In each cycle, reading begins at the first address of the memory block 19 and precedes the writing at the address of the new current phase value. The read information is stored in the register 20 in the additional code. At the end of the first measurement cycle, before the pulse decoder 28 is reset to the initial state, counters 14 and 11, the total code of the phase from counter 14 through block 17 elements AND, counter 15, adder 18, block 24 elements And is recorded in registers 25 and 23. The averaged value of the output phase code is obtained by dividing the total register code 25 by the number n of measurements in the cycle. With n 2, division is made by simply shifting to the left the total phase code by K binary bits.

At the end of the first current measurement of the second cycle, the phase code of the first current measurement is supplied to the second group of inputs of the adder 18, and the value of the first measurement phase of the first cycle stored in memory block 19 is supplied to the third group of inputs in the additional code. In the outputs of the adder 18, the difference between the (n + 1) -th and first measurement codes is obtained, which is summed with the total register code 25.

The total value of the phase code of the first cycle has

N (1) N, j +.

 The total value of the code after the first measurement is w {a loop

N (2) N, +. .. Nf ,, N (1) + (N, - N,).

After n + 1 measurements, register 25 accumulates the total phase code n and the last measurements.

The control pulse, formed, 1m at the end of each measurement, the sum obtained in the adder 18, through the block 24 elements And recorded in the register 25. After time.

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determined by delay element 27, the same amount is recorded in register 23, and 1 is produced: zero

5 At the end of the second current measurement of the second cycle, the group of inputs of the adder 18 receives the phase code for this measurement, and the third group of inputs in the additional code O is the phase value of the second measurement of the first cycle, which was stored in memory block 19. The difference between the codes of the (n + 2) -th and second measurements is obtained, which is summed up with the total register code 25. In this case, it is easy to prove that after the n-2 measurements in register 25, the cyivrMapHbrfi phase code n of the last measurements accumulates.

20 Thus, in the second pickle, after each measurement, up to 2n-1 measurements in register 25} of the cases: the total code of the last measurements is recorded. After the n-th measurement of the second cycle

Total Phase Code from Counter

14, the pulse of the decoder 28 is recorded in registers 25 and 23.

The entry of counter code 14 in registers 25 and 23 is as follows. The pulse of the decoder 28 through the block G / elements And the code (p-1) of the lower bits of the counter; 4 is recorded in the counter 15, Ol, 4 yvremeyino with the same impulse -: registers 20 and 23 are set to the zero state and through one of the elements of the block 17 the most significant bit of the counter 15., so the registers 20 and 23 and the old bit of the counter , 5 contain only zeros, the code from the lower bits of the counter 1 5 and the rest: the first star; -hk bits of the counter 14 through the adder 18; i the open block of 24 elements And the pulse of the differentiating element 8 is recorded in registers 25 and 23.

Thus arg. starting with the n-th measurement, with each subsequent measurement of the instantaneous phase shift value in register 25, the total phase shift code of the last n measurements is formed, and, therefore, the transducer speed becomes equal to the measurement frequency of the instantaneous phase shift value.

The number of bits of the counter 15 is chosen so that its maximum weight corresponds to

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a phase shift of no more than 360. In order to reduce the amount of memory of the block 19, the number of bits of the counter 15, the bits of the counter 15 of the current phase value for writing to block 19 and for summation can be taken much smaller than the maximum value of the received code requires.

For example, if the sum of all types of measurement errors and the phase shift values of the output signals per cycle does not exceed one arc minute, then the number of digits of counter 15 can be taken no more than six, if the price of the least significant bit of counter is at least one arc second.

In such a converter, it is possible to use a memory block in a microchip design, which does not require high 3812g

speed, with one information input and output, and with information inputs equal to the number of code bits. If 5 is used a memory block with one information input and output, then the write and read into it is done in bits, and to write and read each bit of information it is necessary to form

the address code of each bit of the writeable and readable phase shift code.

Information on the output of such

5, the converter can be updated at a frequency equal to the frequency of the input signals, which improves the speed of the proposed converter as compared to the known one.

Claims (1)

A PHASE SHIFT CONVERTER IN THE CODE containing the first and second pulse shapers, the inputs of which are connected to the input source, the first trigger, the output of the second pulse shaper is connected to one input of the first element And, the output of which is connected to the counting input of the second trigger, the outputs of the first and second triggers through the first and second differentiating elements are connected to the inputs of the third trigger, the output of which is connected to one input of the second element And, the other input of which is connected to the output of the pulse generator ow, and the output is connected to the counting input of the first counter, the outputs of the first counter through the first decoder are connected to another input of the first element AND, the second counter, the installation input of which is connected to the installation input of the first counter, the zero input of the first trigger is connected to the zero input of the second trigger, different the fact that, with a speed improvement circuit, a second decoder, a memory block, first, second, third and fourth registers, an adder, first, second, third and fourth blocks of elements And, a third counter are introduced into it , the first and second delay elements, the OR element, the output of the first pulse shaper is connected to the counting input of the first trigger, the outputs of the first and second differentiating elements are connected to the read and write inputs of the memory block and through the OR element to the counting input of the second counter, the outputs of which are connected to the address the input of the memory block, and through the second decoder - to the zero input of the first trigger, the input of the first delay element, the first input of the first block of AND elements and to the zero inputs of the first and second registers, the second input of the first block of elements And connect * not ?! with a bus of zero potential, the remaining inputs are with the outputs of the first counter, the first group of outputs of the first block of elements And is connected to the first group of inputs of the adder, and the second group of outputs is to the information inputs of the third counter, the counting input of which is connected to the output of the second element And, and the outputs are connected to the second group of inputs of the adder and to the information inputs of the second block of elements And, the outputs of the second block of elements And are connected to the information inputs of the third register, the outputs of which are connected to information inputs the storage unit, the storage unit outputs are connected to data inputs of the second register, whose outputs are connected SU .. „1193812 to the third group of inputs of the adder, the outputs of the adder are connected to the formation inputs of the third block of elements AND, the outputs of which are connected to the inputs of the fourth register, the outputs of the fourth register are connected to the output of the converter and to the information inputs of the fourth block of elements AND, the outputs of which connected to the information inputs of the first register, the outputs of the first ϊ 9 3 8? 2 register .; connected to the fourth group of inputs of the adder. output of a differentiating element;: · connected to the control inputs of the second ..... th and third blocks of AND elements and through the second delay element to the control 'input of the fourth p-k - k of AND elements and to the installation input of the third counter; -. and inside: dato п г г г мо мо мо? та та та та та та та задержки та задержки задержки задержки задержки задержки задержки задержки задержки задержки задержки задержки та задержки задержки та та та та та та та дат дат дат дат дат