SU557504A1 - Telegraph code combinations accumulator - Google Patents

Description

one

The invention relates to telecommunications and can be used in telegraph communication systems.

A telegraphic code storage unit is known that contains sequentially connected logical inputs of combinations and memory blocks, logical elements of combination output, write and read counters, and a clock bus connected to memory blocks, with the memory blocks and control block being triggered. with separate inputs, matching schemes.

Rewriting code combinations from one accumulation stage to another free stage is performed by a circuit consisting of coincidence circuits and a service trigger, using two clock sequences iJ

However, the known drive contains a large number of elements, in particular static triggers, which causes its low reliability.

The purpose of the invention is to increase reliability by reducing the number of storage elements.

To do this, a telegraph combination accumulator containing serially connected logical elements of the combination input and memory blocks, logical elements of the combination output, write and read counters, and a clock bus connected to the memory blocks are entered with the elements AND the memory is made on shift registers, to the inputs of which are connected respectively the inputs of the logical elements of the output of the combinations, the outputs of the shift registers are connected to the corresponding inputs, the logical elements of the input of the combinations, to the input the account The recording clock through the OR element is connected to the clock bus and the pulse bus of input code combinations, and the output of the corresponding bits of the recording counter is connected to the inputs of the first And element,

whose auxiliary input is connected to the write-out bus, the output is directly connected via the NOT element, respectively, to the second and third inputs of logical input combinations, the input of the counter reads through the OR element with the i-jrtjioft clock output of the second And element, one input which is connected to the output bus ktssg; Ых combinations, and the second input is connected to the output of ipnrrepa, and one input of the trigger is connected to the bus of input of code combinations, and the other to the output of the third element And, to the inputs of which the corresponding output and read counters are connected, the inputs of the fourth AND element are connected to the outputs of the readout counter and the read resolution bus, and the output is connected to the additional inputs of the logical combination of the output of code combinations and the CHJIXpOliMnynbCOB bus, The t-drive is performed on an integrated standard logic circuit, which allows to simplify it, improve the volume-wise performance, increase reliability and decrease the number of connections between its specific elements. The drawing shows a block diagram of the proposed drive. The drive of telegraph code combinations contains a memory block made 1; and the shift registers 1, whose inputs are connected to the logical & jiei fGHTOB 2 combinations input and the inputs of logical elements 3 output combinations, registers 1 are connected to the corresponding, inputs of logical elements 2 counters;: records 4, to the input of which an element OR 5 is connected to a clock bus n bus 7 impulses to enter code combinations, and the outputs of the corresponding bits of the record counter 4 are connected to the inputs of ep. I 8, the additional input of which It is connected to the write resolution bus 9, and the output of which is directly connected through the element NOT 10 to the second and third inputs of logic elements 2, the readout counter 11, the input to which is connected {through the element OR 12 with the clock bus 6 and the output of the second And 13, one input of which is connected to the bus 14 of the output code combination, and the second input - with the output, trigger 15, with the No. 1 one input of the trigger connected to bus 7, and the other to the output of the third element And 16, to the inputs, the corresponding outputs of counters 4 and 11 are connected to the outputs of the latter are also connected to inputs of the fourth AND 17J edeme.nta one input of which is connected to the bus 18razresheni read and output by kpyuchen extra logic inputs achementov 3 and bus 19 clock. The corresponding inputs of registers 1 are connected to the clock bus 6, the corresponding inputs of counters 4.11 are connected to the initial installation bus 20, the inputs of logic elements are 2nd input code buses 21, the outputs of logic elements 3 are output code buses 22. The proposed drive works as follows . At the initial moment of the pulse fed through the bus 20, the counters 4 and 11 are set to the zero state. A bus sequence is fed to the bus 6. In this case, counters 4 and 11 are in one step (zero) phase state. At the output of the third element And 16, an impulse periodically appears, which includes a trigger 15, from the output of which the second element 13 prohibits. The code combination 21 enters a code combination that needs to be written. Thereafter, a write enable signal is provided to bus 9. At the times when the counter 4 is in the zero state, at the output of the element And 8 and at the output of the element 10 there appears an impingement permitting the writing of code combinations that draw over the buses 21 into registers 1 through the logic elements 2 and prohibit the passage of code combinations from the outputs of registers 1. Upon termination of the write enable signal, bus 7 receives an input of code combinations that shifts the phase state of counter 4 one left and resets trigger 15, from which the resolution goes to 13. Process And nt input codeword ended. Recording the code combination circulates in registers 1, the drive is ready to receive the following code combination, the input of which is similar. The drive operation in the output mode is as follows. On line 18, the nocTjaiaeT signal is resolved and not read. At the output of the fourth element And 17, the pulses appear at the moments of time or, respectively: they are zero to the zero state of the counter 11. The pulses from the output of the element And 13 allow the first code combination to pass through the elements 3 to the output code buses 22. At the end the read enable signal to the bus 14 receives a pulse of the output of code combinations. This pulse shifts the phase state of the counter 11 by

unit to the left and arrives at the element OR 12 only if there is a resolution from the trigger 15, which enters the input of the second element And 13. This happens only when the counters 4 and C are in different phase states, i.e. when the drive is not empty. The scheme is ready for the output of the following code combination. Input and output can occur simultaneously with different frequencies.

Claims (1)

1. Auth. swith No. 285040, and O4 B13 / Sa, prior. 05.05.69.