JPS63309989A - Screen controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a screen control device, and particularly to a screen control device equipped with a screen memory, for displaying italic characters obtained by rotating input characters by 90 degrees to the right or left. Or it relates to a screen control device that can print.

[Conventional technology]

Conventionally, as a configuration of a data control circuit of a screen memory in this type of screen control device, the one shown in FIG. 5 is known.

Now, for convenience of explanation, in the screen memory 12 of FIG.
It is assumed that one data write and read operation is performed word by word, with 16 bits as one word.

Processor l causes register 2 to hold information indicating from which position in the 16-bit area in the screen memory data should be written via signal a. The pattern generator 3 generates a specific pattern (mask pattern) consisting of 16 bits as the signal C in response to the signal from the register 2. This pattern is inputted to the AND circuit 8 by the signal C, inverted by the logic NOT circuit 4, and inputted to the AND circuit 5 as the signal d.

On the other hand, 16-bit data to be written into the screen memory 12 is given to the register 6 from the processor 1 via a signal a. The write data held in register 6 is applied to shift circuit 7 by signal e, and is transferred to register 2.
16 by being shifted in response to the signal from
The most significant bit (MSBj) of the bit write data is
It is applied to the AND circuit 8 as a signal f placed at the bit position indicated by the information held in the register 2.

Here, an operation is performed on the screen memory 12 to change part of the data read from the screen memory 12 and write it again.
When so-called read-modify-write is performed in a sequence, the data read from the screen memory 12 is first held in the register 9 via the signal g. The output signal of this register 9 is given to the AND circuit 5, so that the signal d from the logic NOT circuit 4 is
An AND operation is performed with the inverted pattern given as . The calculation result in the AND circuit 5 is
It is applied to the OR circuit 10 via the signal j.

On the other hand, the output signal i of the AND circuit 8 is the result of the AND operation of the shift result f of the data to be written given via the signal f and the pattern given by the signal C. In the OR circuit 10, a logical sum operation is performed on a part of the data to be written into the screen memory 12 and a part of the data read from the screen memory 12, and the result is output as a signal.

Then, when the buffer circuit 11 is turned on during read/modify write, the signal k changes to the buffer circuit 1.
1, is output as signal g, and written into screen memory 12. As a result, the data held in the screen memory 12 is updated, but at this time, a part of the designated position is rewritten with data from the processor.

Next, add 1 to the word address of the screen memory, generate a pattern again from the pattern generator 3, and perform the same operation.The remaining part of the data to be written will be transferred to the screen memory 12.
will be written to.

By doing so, the processor 1 can write data without being aware of the relationship between the data writing position in the screen memory 12 and the bit unit of data writing and reading.

[Problem that the invention seeks to solve]

In the data control circuit of the screen memory in the conventional screen control device shown in FIG. 5, data for one writing or reading unit in the screen memory is normally arranged in the main scanning direction of the rask scan of the screen. It is composed of Therefore, in general, the structure is not suitable for writing and reading data in the sub-scanning direction.

For this reason, for example, if input characters are to be displayed rotated by 90'' with respect to the normal screen display direction, a means for rearranging character patterns in a matrix should be provided, or character patterns that have already been rearranged should be prepared. There is a need.

In the case of the former method, if an increase in the amount of circuitry is not allowed, the processor will rearrange the character patterns, which is inappropriate when high-speed display on the screen is required. Furthermore, if the image is rotated by 90 degrees and then displayed in an italic form, the display performance will deteriorate and become impractical.

Therefore, display devices and printing devices that require high-speed display often adopt the latter method, but in this case, if you try to display italics in addition to normal fonts, the scale of the character generator increases. There is a problem with doing so.

(Object of the Invention) The present invention is intended to solve the problems of the prior art, and is to provide a screen control device equipped with a screen memory that rotates input characters by 90'' with respect to the normal display direction. The object of the present invention is to provide a screen control device that does not reduce the processing speed and does not require increasing the capacity of a character generator when displaying or printing in italics.

[Means for solving problems]

The screen control device of the present invention includes a screen memory for printing and a microprocessor for controlling the screen memory. mX
Processor data consisting of yl (m, n are natural numbers) bits is shifted in a shift circuit so that its MSB is written from a designated position in each m×n bit area on the main scanning line of the screen memory, and A specific pattern is multiplied in one AND circuit. The data read from the screen memory is multiplied by the inverse pattern of the above-mentioned pattern in the second AND circuit, and the multiplication result of the first AND circuit is added to this multiplication result and written to the screen memory. , read modify
It uses a raster scan method that rewrites data by performing write operations. Starting with a first register string in which n m-bit registers are connected in cascade through delay circuits, the number of registers is decreased by one in order. A group of registers that divides an xn-bit data signal into m-bit units, inputs it to each register string, sequentially delays it for each main scan, and outputs it, and data from the processor.
The shift circuit includes a selector that selectively inputs output signals of the same timing from each register column constituting the register group to the shift circuit. This allows the input characters to be written in the screen memory by switching between the original font and the italic characters.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows the features of the screen control device of the present invention.
An example of the circuit configuration of the register group 13 is shown.

In FIG. 1, registers 16 to 19 are each 4-bit registers, and the output signals of registers 17 to 19 are connected to input terminals of 4-bit registers 20 to 22, respectively, via delay circuits 26 to 28. 21.2
The output terminals of registers 2 and 2 are connected to the input terminals of 4-bit registers 23 and 24 through delay circuits 29 and 30, respectively, and the output terminal of register 24 is connected to the input terminal of 4-bit register 25 through delay circuit 31. There is.

Registers 16-19 each receive signals 0. p.

The signals applied to q and r are held by the write pulse applied to signal W. The signals W are also given to the registers 20 to 25, respectively, and by the time the write pulse is generated in the signal W, the output signal of the previous stage register is sent to the input terminal of the next stage register via the delay circuits 26 to 31. Therefore, when a write pulse is generated in the signal W, the data in the previous stage before being rewritten is held in the registers 20 to 25.

That is, for example, register 1 is written in the first write pulse.
The data held in 9 is held in register 22 on the second write pulse, held in register 24 on the third write pulse, and held in register 25 on the fourth write pulse to produce an output signal V. . Similarly, the data held in register 18 by the first write pulse is held in register 21 by the second write pulse, and held in register 23 by the third write pulse, producing output signal U. Furthermore, the data held in the register 17 by the first write pulse is held in the register 20 by the second write pulse, producing an output signal t. The data held in register 16 on the first write pulse produces output signal S. In this case, the delay circuit 26
.about.31 are used simply to ensure timing for writing data in registers at subsequent stages.

In this way, the register group 13 in FIG.
Output signals s, t from p, q, r, respectively
.

It consists of 4 register rows leading to U and V, and each register row has the function of dividing 16-bit data input at the same timing into 4 bits each and outputting them sequentially at different timings. There is.

FIG. 2 explains the operation of the register group shown in FIG. 1, and the register group 13 is the same as that shown in FIG.

In FIG. 2, 16-bit data At, Bi, Ci, and Di input to the register group 13 are data al~aa, b+~bn+C+~C4, respectively.
dj ~ l, data al+bl+ CI+
dj is input to signal 0 and data az.

b, , c, di are input to signal p, and data a3 +
b3 + C3, d2 are input to the signal q, data am + ba, C41da are input to the signal r, and temporally in the order of Ai, Bi, Ci, Di, the first time,
In synchronization with the second, third, and fourth write pulses,
shall be entered.

Since the register group 13 is configured as shown in FIG. 1, the output of the register group 13 when the first write pulse is applied is as shown at 80 in FIG. Bo for the second, third, and fourth write pulses.

Co, DO, for example, data a, ~a
, the respective 4-bit data are sequentially delayed for each write pulse cycle in the signals s, t, u, and v. Other data b+ ~bn + CI'
A similar relationship holds true for =Car dj to di.

FIG. 3 shows the configuration of an embodiment of the screen control device according to the present invention, in which the same parts as in FIG. 5 are designated by the same numbers, and the register group 13. Selector 14. Register 15 has been added.

In FIG. 3, the register 15 is given information indicating the distinction between normal printing and italic printing from the processor 1 via the signal line a. In the case of normal printing, the register 15 outputs, for example, "0" to the signal n, which causes the selector 14 to select the signal e of the register 6 and output the signal m to the shift circuit 7. The operation of the circuit of FIG. 3 in this state is no different from the conventional case shown in FIG.

In the case of italic printing, the register 15 outputs "1", which causes the selector 14 to output the signal of the register group 13!
is selected and the signal m is output to the shift circuit 7.

Now, assuming that signal a is 16 bits, register group 13 is
It has the configuration shown in the figure, and all registers 16 to 25 forming the register group 13 have a 4-bit configuration.

The 16-bit input data Ai explained in FIG.
, Bi, Ci, and Di are input sequentially for each main scan of the original signal, but the signal line o is input to the register group 13.
, P, q, r, and are divided into 4 bits and input to the signal lines s, t, u, at the output of the register group 13.
In V, each 4 bits are sequentially outputted as data delayed for each write pulse W.

Therefore, by applying the write pulse W in synchronization with the main scanning, the 16-bit data Ao, Bo, C at the same timing on the signal lines s, t, u, and v.
o and DO are sequentially written to the screen memory 12 through the shift circuit 7 for each main scan in the same manner as in the case of FIG. 5 during read-modify-write writing.

Therefore, in the input data Ai, data a and %an of the same main scanning period are divided into 4 bits each in the write data on the screen memory 12 and are sequentially located on subsequent main scanning lines.

FIG. 4 shows a display example of the character pattern written in the screen memory 12 by the screen control device of the present invention shown in FIG. 3, where (a) shows the case of normal printing; Characters in the normal font are shown when the ``Affa Bed N'' is rotated 90 degrees to the right.Also, (b) shows the case of italic printing, and the characters in the normal font shown in (a) are printed using the screen control of the present invention. The example is shown in which the characters are converted into italic characters and displayed depending on the device.

In Fig. 4, in the case of normal printing, each dot displayed on the same main scanning line as shown in Fig. 4 (a), and in the case of italic printing, as shown in Fig. 4 (b), each dot is displayed on the same main scanning line. 4 dots are sequentially displayed with their positions changed so that they are located on the next main scanning line, indicating that italicized characters are displayed as a whole.

〔Effect of the invention〕

As explained above, according to the present invention, by simply adding a simple circuit consisting of a register and a selector to a conventional screen control device, characters rotated by 90 degrees to the right or left can be inputted, and the characters can be italicized. It can be converted into text and displayed or printed.

At this time, there is no need for the processor to rearrange characters rotated 90 degrees to the right or left to italic characters, so there is no reduction in processing speed, and therefore the display speed on the screen 1 the printing speed on the paper never decreases. Furthermore, since there is no need to have a character pattern rotated 90 degrees to the right or left and further italicized, the capacity of the character generator does not increase.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the circuit configuration of a register group in the image control device of the present invention, FIG. 2 is a diagram explaining the operation of the register group shown in FIG. 1, and FIG. 3 is a screen control diagram according to the present invention. FIG. 4 is a diagram showing a display example of a character pattern written in the screen memory by the screen control device of the present invention, and FIG. 5 is a diagram showing the configuration of a conventional screen control device. It is a diagram. 1... Processor, 2.6, 9, 15.16~
25...Register, 3...Pattern generator, 4...Logic negation circuit, 5.8...
・Logic product circuit, 7...Shift circuit, 10...
...OR circuit, 11...Buffer circuit, 1
2...Screen memory, 13...Register group, 14...Selector, 26-31...
・Delay circuit.

Claims (1)

[Claims] (1), equipped with screen memory, m×n (m, n are natural numbers)
Processor data consisting of bits is shifted in a shift circuit so that the MSB thereof is written from a designated position in each m×n bit area on the main scanning line of the screen memory, and a specific pattern is written in a first AND circuit. At the same time, the data read out from the screen memory is multiplied by an inverted pattern of the pattern in the second AND circuit, and the multiplication result of the first AND circuit is added to the multiplication result, and the data is read out from the screen memory. By writing in
In a raster scan type display or printing device that rewrites data by performing a read/modify/write operation, a first register string in which n m-bit registers are connected in cascade through alternate delay circuits. Starting from , the number of registers is sequentially decreased by one to form n register rows, and the m×n bit data signal from the processor is divided into m bits and input to each register row. a register group that sequentially delays and outputs the output; and a selector that selectively inputs data from the processor and output signals of the same timing of each register string constituting the register group to the shift circuit, A screen control device characterized in that input characters can be written in a screen memory by switching between the original font and italic characters.