JP2697420B2 - Data writer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data writing device for writing a write data to a memory in place of the data generation device when a write request is received from a data generation device for generating the write data.

In recent years, with the development of distributed processing systems and communication technology due to the advent of high-performance microprocessors, the development of computer networks for interconnecting geographically dispersed computers and sharing resources has been actively pursued. Have been done.

In such a computer network, it may be necessary to write data from one computer on the network to the memory of another computer in order to share the memory.

When such data writing is performed,
In order to increase the use efficiency of a central processing unit (hereinafter, referred to as a “CPU”) of a computer that writes data, it is necessary to reduce the load on the CPU in the data writing process.

[0005]

2. Description of the Related Art Conventionally, in order to reduce a load on a CPU in a data writing process, a data writing device is conventionally provided in a computer on a data writing side, separately from the CPU.
When a write request occurs in the CPU, the data writing device executes a data write process in place of the CPU.

According to such a configuration, after the write request is accepted by the data writing device, the CPU is released from the data writing process, so that the load on the CPU in the data writing process can be reduced.

FIG. 5 is a block diagram showing an example of the configuration of a computer network having such a data writing device.

In FIG. 1, reference numeral 11 denotes a computer on which data is written, and reference numeral 12 denotes a computer on which data is written. A bus 13 connects these computers 11 and 12.

Upon receiving a write request from the CPU 111, the computer 14 replaces the CPU 111
This is a data writing device for writing data to the memory 121 of FIG.

The conventional data writing device 14 basically writes data in the following procedure.

When a write request is received from the CPU 111, the CPU 111 notifies the CPU 111 that the next data write is possible after the data write based on the previous write request is completed.

Based on the notification, the write data and the write address supplied from the CPU 111 are latched by the latch circuit 141.

Each time the latch operation is performed,
It notifies the computer 12 that the bus 13 is occupied for writing data.

In synchronization with this notification operation, the write data latched by the latch circuit 141 is stored in the memory 121.
Write to.

FIG. 6 is a block diagram showing a specific configuration of a conventional data writing device which executes a data writing operation in such a procedure.

In FIG. 1, when a write request signal S1 is received from the CPU 111, the write request signal S1 is transmitted after data writing based on the previous write request is completed.
1 is an AND circuit.

Upon receiving the write request signal S1 from the AND circuit 21, the signal 22 notifies the CPU 111 that the next data may be written (hereinafter, referred to as a signal).
This is a writable notification circuit that generates a “writable notification signal” S2.

Reference numeral 23 denotes a latch signal generation circuit that generates a latch signal S3 for latching the write data and the write address output from the CPU 111 together with the write enable notification signal S1 in the latch circuit 141. This latch signal S3 is output in synchronization with the write enable notification signal S2.

Reference numeral 24 denotes an empty state determination circuit for determining whether or not the bus 13 is empty. This empty state determination circuit 24 outputs a bus occupation request signal to the bus master,
By receiving a bus occupation permission signal from the bus master, it is determined that the bus is idle.

When the empty state determination circuit 24 determines that the bus 13 is empty, the latch signal S3
Is an AND circuit.

Reference numeral 26 denotes a latch signal S from the AND circuit 25.
3 is an occupation state notification circuit that generates a signal (hereinafter, "occupation state notification signal") S4 for notifying the computer 12 that the bus 13 is occupied for data writing.

When an occupation state notification signal S4 is generated from the occupation state notification circuit 26, a signal 27 for notifying the computer 12 that the data writing process is possible (hereinafter referred to as "writing period notification signal S4"). Signal) S5
Is a writing period notification circuit that generates

Note that the write enable notification circuit 22, latch signal generation circuit 23, occupation state notification circuit 26, and write period notification circuit 27 are composed of a plurality of flip-flop circuits and logic circuits.

However, when these are viewed in a black box, they are all set terminals, reset terminals, clear terminals,
It has a non-inverted output terminal, an inverted output terminal, and a non-inverted output based on the state of a set input, a reset input, and a clear input,
The inverted output changes. FIG. 7 shows a truth table in this case.

The data write operation in the above configuration will be described with reference to the timing chart of FIG. Note that the various signals shown in FIG.
“H” level) is the active level.

When a write request occurs in the CPU 111, the write request signal S1 output from the CPU 111 goes high as shown in FIG. 8A.

The write request signal S1 is output from the AND circuit 2
1 and is gated by the gate signal S6 output from the inverted output terminal of the latch signal generation circuit 23.

If it is assumed that data writing is in an initial state, the latch signal generating circuit 23 is set in a reset state in this initial state.

Therefore, in this initial state, gate signal S6 is at "H" level. Thus, in this case, when the write request signal S1 becomes "H" level, the write enable notification circuit 22 is immediately set to the set state.

As a result, the write enable notification signal S2 output from the non-inverting output terminal of the write enable notification circuit 22 becomes:
As shown in FIG. 8B, the level becomes “H” level.

Thus, the CPU 111 is notified that the write data has been received, and that the next data can be written. As a result, this CPU 111
Determines that the data writing has been completed, and if necessary,
Outputs the next write request.

At the same time, the latch signal generation circuit 23 is set. As a result, the latch signal S3 output from the non-inverted output terminal goes high as shown in FIG. 8C.

As a result, together with the write request signal S1,
The write data and the write address output from the CPU 111 are latched by the latch circuit 141.

The judgment signal S7 output from the empty state judging circuit 24 is "H" when the bus 13 is empty.
Level, and when it is not empty, it is at the “L” level.

Therefore, when the latch signal S3 becomes "H" level and the bus 13 is in an empty state, the occupation state notification circuit 26 is set to the set state.

As a result, the occupation state notification signal S4 output from the non-inverted output terminal goes high as shown in FIG. 8D. As a result, the fact that the bus 13 is in the occupied state for writing data indicates that the computer 1
2 is notified.

When the occupation state notification signal S4 goes to "H" level, the writing period notification circuit 27 is set.

As a result, the write period notification signal S5 output from the non-inverting output terminal goes high as shown in FIG. 8 (e). As a result, the computer 1
2 is notified that it is the data writing period.

Thus, in the computer 12, a control signal (row / column address strobe signal or the like) for writing the write data latched by the latch circuit 141 into the memory 121 is generated.

When the data writing is completed, a signal (hereinafter referred to as a "writing completion notification signal") S8 output from the computer 12 to notify the computer 11 of the completion of the data writing, as shown in FIG. , "H" level.

As a result, the write period notifying circuit 27 is set to the reset state. As a result, the write period notification signal S5 becomes "L" level.

At this time, the write period notifying circuit 27
The reset signal S9 output from the inversion terminal of this signal becomes "H" level, so that the latch signal generation circuit 23 and the occupation state notification circuit 26 are set to the reset state.

As a result, the latch signal S3 and the occupation state notification signal S4 are set to "L" level.

When the latch signal generation circuit 23 is set to the reset state, the gate signal S6 becomes "H".
Since the level becomes the level, the gate of the AND circuit 21 is opened.

Therefore, at this time, if the next write request has occurred (if write request signal S1 is at "H" level), the above-described operation is repeated again.

Thereafter, similarly, every time a write request is generated in the CPU 111, the above-described operation is repeated.
From the computer 11 to the memory 121 of the computer 12
Is executed.

As described above, the conventional data writing device 14 cancels the notification of the occupation state (sets the occupation state notification signal S4 to the "L" level) every time the data writing is completed, and the next data writing apparatus 14 sets the next state. When there is a write request, the notification operation of the occupation state is started again.

This corresponds to the data writing device 14 described above.
However, it is intended for a system in which write requests occur discontinuously.

However, even in such a system, a data write request may occur continuously (hereinafter, such a generation mode is referred to as a "burst mode").

As described above, when the write request is generated in the burst mode, the conventional data writing device 14 has a problem that the data writing time becomes long.

That is, the write period notification signal S5 can be set to the "H" level only when the occupation state notification signal S4 is at the "H" level due to its nature.

Therefore, in the configuration in which the occupation state notifying signal S4 is set to the "L" level every time the data writing is completed, even if the next writing request occurs at the time of the data writing being completed, immediately. , Writing period notification signal S5
Cannot be set to the “H” level.

That is, even in such a case, first, the occupation state notification signal S4 is set to the "H" level, and then the writing period notification signal S5 is set to the "H" level. There must be.

Thus, the time T _A (see FIG. 8) from when the write data and the write address in the next write request are latched by the latch circuit 141 to when the write period notification signal S5 is set to the “H” level is set. become longer.

When the time T _A becomes longer, in the burst mode, the time T _A is accumulated by the number of times of data writing, so that the entire data writing time becomes longer.

[0056]

As described above, in the conventional data writing device, the notification of the bus occupation state is released every time the data writing is completed. There is a problem that the writing time becomes longer.

Therefore, an object of the present invention is to provide a data writing device capable of shortening the data writing time in the burst mode.

[0058]

FIG. 1 is a block diagram showing the principle configuration of the first aspect of the present invention.

In the figure, reference numeral 41 denotes a data generator for generating write data. Reference numeral 42 denotes a memory in which write data output from the data generator 41 is written. 43 is a bus connected to the memory 42.

Reference numeral 44 denotes a data writing device which is a feature of the present invention. When the data writing device receives a write request from the data generation device 41, the data writing device writes the write data into the memory 42 instead of the data generation device 41.

In this data writing device 44, 44
1 receives a write request from the data generator 41,
An occupation state notifying means for notifying that the bus 43 is in an occupied state for the purpose of writing write data to the memory 42.

Each time the data write based on the write request is completed, 442 determines whether or not the next write request has occurred. If the next write request has not occurred,
Notification cancellation means for canceling the notification operation of the occupation state notification means 441. 443 is a write from the data generator 41
Each time a request is received, data based on the previous write request
After the writing is completed, the next data is stored in the data generator 41.
Writable notification means for notifying that writing is possible
It is. 444 is a write request from the data generator 41
Each time the data is received, data is written based on the previous write request.
After the data has been read, the
Data holding means for holding embedded data. 445
Indicates that write data is held in the data holding unit 444
Every time this write data is written to the memory 42
Data writing processing means for executing the processing of
When write requests are continuously generated from the generator 41
In response to the first write request,
This data write processing is performed in synchronization with the notification operation of the stage 441.
And write the second and subsequent data write requests.
In synchronization with the notification operation of the
Execute data write processing.

[0063]

According to the above configuration, even if the data writing is completed, the notification operation of the occupation state is not canceled if the next writing request has occurred.

Therefore, when the present invention is applied to the data writing apparatus as shown in FIG. 5, the write period notification signal S5 can be set to the "H" level immediately at the timing when the latch of the write data is completed.

As a result, the time T _A as shown in FIG. 8 can be eliminated, so that the data write time in the burst mode can be reduced as compared with the conventional case.

[0066] Specifically, if the number of write data in the burst mode and n, conventionally, it is possible to shorten the (n-1) T _A Only the data write time.

[0067]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention.

FIG. 2 is a block diagram showing an apparatus for generating a write period notification signal S5 in order to execute a data write process according to the present invention.
The configuration in the case of applying to the above is shown as a representative.

Therefore, in FIG. 2, the same parts as those in FIG. 6 are denoted by the same reference numerals, and detailed description will be omitted.

FIG. 2 is different from FIG. 6 in the way of resetting the occupation state notifying circuit 26 and the way of setting the writing period notifying circuit 27.

Therefore, hereinafter, the configuration of FIG. 2 will be described focusing on the reset configuration and the set configuration.

First, the reset configuration of the occupation state notification circuit 26 will be described.

In FIG. 6, the occupation state notifying circuit 26 is reset every time data writing is completed.

On the other hand, in this embodiment, even if the data writing is completed, if the next writing request is generated at that time, the occupation state notifying circuit 26 is not reset, and the writing request is generated. Reset only if not available.

However, in this case, if the burst mode continues for a long time, the bus 13 will be occupied for a long time for data writing.

This causes a disadvantage that the bus 13 cannot be used for another purpose.

Therefore, in this embodiment, the number of writable data in the burst mode is limited.

That is, when the burst mode is continued and the number of write data reaches a predetermined number m (m ≧ n),
The occupation state notification circuit 26 is forcibly reset.

This reset is performed by the burst disable determination circuit 3
1 and the AND circuit 32.

Here, the burst disable determination circuit 31 performs the data write in the burst mode when
This is a circuit for determining whether or not the burst mode can be continued.

That is, the burst impossibility determination circuit 31
Each time the data writing is completed, it is determined whether or not the next writing request has occurred. If the writing request has occurred, it is determined that continuation is possible. If not, it is determined that continuation is impossible.

The burst rejection determination circuit 31
In parallel with this determination processing, it is determined whether or not the number of data writes has reached a predetermined number m. If not, it is determined that continuation is possible.

In this case, the burst impossibility judging circuit 3
Normally, the determination signal S10 output from the H. 1 goes to the “H” level, and goes to the “L” level during the burst mode.
When it is determined that the burst cannot be continued, the level returns to the “H” level.

The AND circuit 32 is a gate circuit that gates the reset signal S9 output from the write period notifying circuit 27 based on the determination signal S10 output from the burst disable determination circuit 31.

By the gate operation of the AND circuit 32,
When it is determined that the burst mode can be continued, the occupancy state notifying circuit 26 is not reset. When it is determined that the burst mode cannot be continued, the occupancy state notification circuit 26 is reset.

FIG. 3 is a block diagram showing an example of a specific configuration of the burst impossibility determination circuit 31.

As shown in FIG.
Is composed of a shift register 311, a JK flip-flop circuit 312, an inverter 313, and an OR circuit 314.

The shift register 311 is composed of (m-1) stages of D flip-flop circuits D _{1 to} D _{m- 1} .

The write termination notification signal S8 is supplied to the clock terminals of the D flip-flop circuits D _{1 to} D _m-1 .

The first-stage D flip-flop circuit D
₁Of the data signal S11 of “H” level
Is supplied, and the D flip-flop circuits D of the second and subsequent stages are supplied._Two
~ D _m-1The data input terminal of
Circuit D₁~ D_m-2So that the non-inverted output of
Has become.

Further, each of the D flip-flop circuits D ₁ to D ₁
The occupation state notification signal S4 is supplied to the clear terminal of D _m-1 .

The write termination notification signal S8 is supplied to the clock terminal of the JK flip-flop circuit 312, and the D flip-flop circuit D of the (m-1) th stage is supplied to the J terminal.
An inverted output of _m-1 is supplied.

The JK flip-flop circuit 31
The non-inverted output of the D flip-flop circuit _Dm-1 and the write request signal S1 are supplied to the K terminal of the second through the OR circuit 314.

However, in this case, the write request signal S1 is
The power is supplied in an inverted state by the inverter 313.

Further, a reset signal S12 is supplied to the clear terminal of the JK flip-flop circuit 32. The reset signal S12 is output in an initial state before data writing is started.

The judgment signal S1 of the burst impossibility judgment circuit 31
0 is output from the inverted output terminal of the JK flip-flop circuit 312.

An operation of determining whether or not the burst mode can be continued in the above configuration will be described.

In the initial state, the occupation state notification signal S
4 is at "L" level, the D flip-flop circuit D ₁
~ D _m-1 are in the clear state.

In this initial state, since the write request signal S1 is at "L" level, the output of the inverter 313 is at "H" level.

Thus, the JK flip-flop circuit 3
Twelve J and K inputs are both at "H" level.

The JK flip-flop circuit 31
2 has been reset by the reset signal S12 in the initial state, so that the determination signal S9 is at the “H” level.

In this state, if the next write request occurs before the first data write to memory 121 is completed, the output of inverter 313 goes to "L" level, so that JK flip-flop circuit 312 The K input changes from "H" level to "L" level.

As a result, when the write end notification signal S8 becomes "H" level, the JK flip-flop circuit 31
The state of 2 is reversed. As a result, the determination signal S10 switches from “H” level to “L” level.

In the shift register 311,
First-stage D flip-flop circuit D ₁The non-inverted output of
The level switches from “L” level to “H” level.

Thereafter, each time the write end notification signal S8 goes high, the shift register 311
The data signal S11 is sequentially shifted by one stage.

In the process of shifting the data signal S11, if a write request is continuously generated (if the burst mode is continued), the J and K inputs of the JK flip-flop circuit 312 are at "H" level and "L" level, respectively. "Level.

Thus, in this case, the state of JK flip-flop circuit 312 does not change even if write end notification signal S8 attains the "H" level. As a result, the level of the determination signal S10 is also maintained at the “L” level.

In this state, the number of data writes is (m-1)
When the number reaches the number, the non-inverted output of the D flip-flop circuit D _m-1 switches from “L” level to “H” level.

Thus, the JK flip-flop circuit 3
12 is switched from the "L" level to the "H" level, and when the data write number reaches m, this J input
The state of the K flip-flop circuit 312 is inverted.

As a result, the level of the determination signal S10 also becomes
The level switches from “L” level to “H” level.

On the other hand, when the write request is interrupted in the process of shifting data signal S11, the K input of JK flip-flop circuit 312 switches from "L" level to "H" level.

As a result, the state of the JK flip-flop circuit 312 is inverted at the timing when the write end notification signal S8 goes to the "H" level immediately after the write request is stopped, so that the judgment signal S10 also changes from the "L" level. Switching to "H" level.

The reset configuration of the occupation state notification circuit 26 has been described above. Next, the set configuration of the writing period notification circuit 27 will be described.

In the data writing device of FIG. 6, the writing period notifying circuit 27 is controlled based on the occupation state notifying signal S4.
Was set to the set state.

However, in this embodiment, the level of the occupation state notification signal S4 is maintained at the "H" level as long as the write requests are continuously generated.

Therefore, at least in the burst mode period, the write period notification circuit 27 cannot be set based on the occupation state notification signal S4.

Therefore, in this embodiment, for the first write request, the write period notifying circuit 27 is set based on the occupation state notification signal S4, and for the second and subsequent write requests, writing is enabled. It is set based on the notification signal S2.

In FIG. 2, reference numeral 33 denotes a selector for switching the set signal.

The selector 33 selects the occupation state notifying signal S4 as a set signal when the judgment signal S10 output from the burst impossibility judging circuit 31 is at "H" level, and writes when it is at "L" level. The enable notification signal S2 is selected.

As a result, the write period notifying circuit 27
For the first write request, it is set by the occupation state notification signal S4, and for the second and subsequent write requests,
It is set by the write enable notification signal S2.

The above is the occupation state notification circuit 2 in FIG.
6 and the reset configuration of the write period notification circuit 27.

Next, the set operation of the occupancy state notifying circuit 26 and the reset operation of the write period notifying circuit 27 will be described based on a specific example of the generation mode of the write request.

FIG. 4 is a timing chart showing the operation when the write request is interrupted after three consecutive requests.

In the figure, t ₁ is the reset signal S12
Indicates the timing at which the signal becomes “H” level, and t ₂ , t ₄ ,
t ₆ are first respectively, showing a second, third timing the write request is generated.

Further, t ₃ indicates the timing at which the occupation state notification signal S4 becomes “H” level based on the first write request, and t ₅ , t ₇ , and t ₈ indicate the first,
This shows the timing at which the second and third data write operations are completed.

In the initial state, as shown in FIG. 4 (h), since the reset signal S12 of the JK flip-flop circuit 312 of the burst impossibility judging circuit 31 is at "L" level, this JK flip-flop circuit 312 Set to clear state.

As a result, the judgment signal S10 output from the JK flip-flop circuit 312 is changed to the state shown in FIG.
As shown in FIG.

In this initial state, FIG.
As (d), the so occupied state notification signal S4 is at "L" level, D flip-flop circuits D ₁ ~D _m-1 burst not judging circuit 31 is set to a clear state.

In this state, when the first write request occurs, the occupation state notification signal S4 is synchronized with the write request signal S1 (see FIG. 4A) as shown in FIG. 4D. H "level.

At this time, since the determination signal S10 is at the “H” level, the selector 33 selects the occupation state notification signal S4 as the set signal of the write period notification circuit 27.

As a result, the write period notification signal S5 becomes
As shown in FIG. 4 (e), the signal becomes “H” level in synchronization with the occupation state notification signal S4.

As a result, data writing for the first write request is executed. When the data writing is completed, as shown in FIG.
8 goes to the “H” level.

As a result, the writing period notification circuit 27 is set to the reset state, so that the writing period notification signal S5
Becomes the “L” level.

At this time, since the second write request has occurred, the J and K inputs of the JK flip-flop circuit 312 of the burst rejection decision circuit 31 become the “H” level and the “L” level, respectively. ing.

Thus, the JK flip-flop circuit 3
12 is set to a set state in synchronization with the end of the first data write. As a result, the determination signal S10 becomes “H”.
The level switches to the “L” level.

Thus, in the selector 33, the write enable notification signal S2 is selected as the set signal of the write period notification circuit 27.

As a result, the write period notification signal S5 attains the "H" level in synchronization with the write enable notification signal S2. Thereby, the second data write is executed.

Timing t when this data writing is completed
_{At 7} , a third write request has already occurred.

Therefore, in this case, since the JK input of JK flip-flop circuit 312 does not change, even if write end notification signal S8 attains the “H” level, determination signal S
10 is maintained at the “L” level.

Thus, also in this case, the write period notification signal S5 is set to "H" in synchronization with the write enable notification signal S2.
Level. Thereby, the third data write is executed.

[0142] However, at the timing t ₈ this data writing has been completed, the fourth of the write request has not occurred.

As a result, in this case, all the JK inputs of the JK flip-flop circuit 312 go to the “H” level.

As a result, the determination signal S10 becomes "H" level at the timing when the third data writing is completed.

As a result, the gate of the AND circuit 32 is opened, so that the occupation state notifying circuit 26 sets the write period notifying circuit 2 at the timing when the third data writing is completed.
7 is reset by the gate signal S9 output from the gate signal S7.

Thereafter, if a write request is issued again, the above-described operation is performed again.

As described in detail above, according to this embodiment,
Each time data writing is completed, it is determined whether or not the next write request has occurred. If so, the notification of the occupation state is not released, reducing the data write time in burst mode. can do.

For example, in the example shown in FIG.
Only by _A , the data write time can be reduced.

Further, according to this embodiment, when the number of data writes in the burst mode reaches a predetermined number m, the data write in the burst mode is forcibly released, so that the bus 13 The inconvenience of being occupied by data writing for a long period can be eliminated.

As described above, one embodiment of the present invention has been described in detail, but the present invention is not limited to such an embodiment.

(1) For example, in the above embodiment, the configuration in which the occupation state notification signal S4 is set to the "H" level in synchronization with the latch signal S3 has been described.

However, in the present invention, any configuration may be used as long as it is set to the "H" level in synchronization with the write request.

For example, it may be set to the “H” level in synchronization with the write request signal S1 or the write enable signal S2.

(2) In the above embodiment, the reset signal S4 is set to set the occupation state signal S4 to the "L" level.
9 has been described.

However, in the present invention, any configuration may be used as long as it is set to the "L" level in synchronization with the end of data writing.

For example, it may be set to the “L” level in synchronization with the write end notification signal S8.

(3) Further, in the above embodiment, when the write period notification signal S5 is set to the "H" level, the second and subsequent write requests are synchronized with the write enable notification signal S2. The configuration for setting to the “H” level has been described.

However, according to the present invention, any configuration may be used as long as the configuration is set in synchronization with the latch of the write data and the write address.

For example, "H" is synchronized with the latch signal S3.
The level may be set.

(4) In addition, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0161]

As described in detail above, according to the present invention,
A data writing device capable of shortening the data writing time in the burst mode can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a principle configuration of the invention according to claim 1;

FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a configuration of a burst disable determination circuit in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of FIGS. 2 and 3;

FIG. 5 is a block diagram showing an example of a configuration of a computer network to which the present invention is applied.

FIG. 6 is a block diagram showing a configuration of a conventional data writing device.

FIG. 7 is a diagram showing a truth table of the circuit shown in FIG. 6;

FIG. 8 is a timing chart for explaining the operation of FIG. 6;

[Explanation of symbols]

111 CPU (Data Generator) 112 Memory 13 Bus 14 Data Writer 141 Latch Circuit (Data Holder) 21 AND Circuit (Writable Notifier) 22 Writable Notifier 23 Latch Signal Generator (Data Holder) 24 Free State Judgment circuit (occupation state notification means) 25 AND circuit (occupation state notification means) 26 Occupation state notification circuit (occupation state notification means) 27 Write period notification circuit (data writing processing means) 31 Burst disable determination circuit (notification cancellation means) 32 AND circuit (notification canceling means) 33 selector (data writing processing means) 41 data generating device 42 memory 43 bus 44 data writing device 441 occupation state notifying means 442 notification canceling means 443 writable notifying means 444 data holding means 445 data writing processing means

Claims (4)

(57) [Claims] 1. A data generator for generating write data.
When a write request is received from the
Write the write data to the memory
When receiving the write request , the device stores the write data in the memory.
To write data to the bus connected to the memory.
And occupied state notifying means for notifying that it is in the occupied state, each time receiving the write request, based on a previous write request
After the data writing is completed, the data
Write enabled to notify that the next data can be written
Function notification means, and each time a write request is received, the
After the data writing is completed, the data
Data holding means for holding the write data supplied from
And the step of holding the write data in the data holding means.
Each time the write data is written to the memory.
Data writing processing means for executing processing, and data writing processing by the data writing processing means being completed.
Each time it completes, determines whether the next write request has occurred
If not, the notification of the occupation state notification means
Notification canceling means for canceling the operation , wherein the data write processing means is configured to
Occurs in response to the first write request
Is synchronized with the notification operation of the occupation state notification means.
Data write processing, and write the second and subsequent data
Request is the same as the notification operation of the writable notification unit.
Executing the data writing process in anticipation.
Data writing device. 2. The occupancy state notifying means, wherein
Request occurs consecutively, the first write data
When the data is held in the data holding means, the notification is executed.
2. The data writing device according to claim 1, wherein
Place. 3. The occupancy status notifying means includes:
Request to determine if the bus is free
And, if idle, to perform the notification operation
The data writing device according to claim 1, wherein 4. The notification canceling means according to claim 1 , wherein:
If it occurs continuously for a predetermined number of times, the number of times
When the writing of data for the
2. The notification operation of a stage is canceled.
Data writing device.