JPS6273863A - Data input and output memory - Google Patents

Abstract

PURPOSE:To attain excellent operation without complicated external control constitution and simultaneous and asynchronous data input/output by storing an input data sent at each line together with the data length and reading a data of each line based on the data length stored at read. CONSTITUTION:A shift register 3 converts a video input data signal DIN having 128-bit of datalength sent serially from a video data generating source such as a picture scanner into a parallel signal and sent in parallel to a buffer register 4. The buffer register 4 stores similarly an 8-bit control data including a data having a line length of a video signal and writes it in a memory array 1 together with the 128-bit video data signal in parallel. A memory write control block 5 generates a write array address signal in the memory array 1 and a data relating to the line length based on a line section signal WDE* representing the effective section of one line of the video input data signal DIN. Thus, no external control is required and the output of the required data is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to data input/output in which input data and output data can be accessed simultaneously and asynchronously.

More specifically, the present invention relates to a data input/output memory capable of converting the frequency of a video signal, synchronizing timing, delaying, etc.

[Prior art]

For example, video signals from Laser Beamsha printers that record images by scanning laser light, and video signals from televisions have a large amount of data. The transmission method is common.

For example, when transferring data to a laser or beam printer, when the sending host (host) - computer sends a video signal to the laser beam printer, it has a buffer memory for synchronization. laser·
It is necessary to transfer the video signal using a serial transmission method in accordance with the rotation of the rotating mirror of the beam number printer. Such a buffer memory is also used for so-called scaling processing in which the size of an image is changed by changing the frequency of a video signal.

Such buffer memories include first-in first-out memory (FIFO memory),
A static RAM capable of high-speed operation is used. The former type of memory has a simpler circuit configuration, but because it does not have high speed or large capacity, it can only be used for synchronizing several dozen pieces of data at most. In addition, although it is highly variable in magnification and has high versatility, it has the disadvantage that it requires an address e-counter, a selector circuit, etc., making the peripheral circuit configuration for memory operation complicated.

〔the purpose〕

An object of the present invention is to provide a data input/output memory with a new configuration that solves the drawbacks of the above-mentioned memory, and
The purpose of the present invention is to provide a data input/output memory that operates well without a complicated external control configuration even for high-speed data input/output, and is capable of simultaneous and asynchronous data input/output.
Another object of the present invention is to provide a data input/output memory with a configuration suitable for one-chip integration.

〔Example〕

The present invention will be explained in detail below based on Examples.

FIG. 1 is a diagram showing an example of a block configuration of a memory provided with the present invention.

The memory array 1 is a memory capable of read/write operations for a plurality of data φ bits.

The memory timing control block 2 is a block that controls timing of read/write operations of the memory array 1, addresses of the memory array, and the like.

The shift register 3 has a data length of 128 bits, and is a 1/register for converting the video input data signal DIN serially sent from a video red data generation source such as an image scanner into a parallel signal. The video data signal is sent in parallel to buffer register 4, which is a buffer when writing to memory array 1.

Buffer register 4 has a capacity of 136 bits, and also stores 8-bit control data including line length data of the video signal sent from memory array write control block 5, and stores 128-bit video in memory array 1.・
Write in parallel with the data signal.

The memory write control block 5 transfers the write array address signal and line length data of the memory array I to a line indicating a valid section of one line of the video input data signal DIN inputted from the video red data source. It is generated based on the section signal WDE.

Buffer register 6 has a capacity of 136 bits and is used when reading memory subarray 1. The data read out in parallel from the memory array 1 is converted from parallel to serial data via the buffer register 6. Among them, the video φ data has a data length of 128 bits to generate the video output data signal DOUT. The control data is also sent to the memory read control block 8.

The memory read control block 8 inputs the read array address signal of the memory array 1 and the line interval signal RDEt indicating the valid interval of one line of the video output data signal DOUT from the buffer register 6. Based on the data 1 e.g. laser beam φ
It is generated in synchronization with the input of a dot start signal RDS from an image processing device such as a printer.

For example, the CLR main signal is input at the start of inputting one screen worth of video data from the video data source and is used to initialize the block, and the WCK signal and RCK signal are the video red This is a clock signal for video data during writing and reading, which is generated from a data source and an image processing device. Note that the symbol at the end of the signal name in this embodiment indicates that the signal is an active low signal. In this way, serially input video data is converted into parallel data, stored in the memory array 1, read out in parallel and output serially, and the storage and read operations are executed independently, asynchronously, and at high speed. do.

Figures 2 to 4 are timing diagrams for explaining the operation of the five circuits.
It is a chart.

Figure 2 shows a case where the data length of one video reference line is 512 bits, the data length of shift registers 3 and 6 is 128 bits, and memory array 1 has a 136 x 8 bit configuration (the number of arrays is 8). is assumed. in this case,
Memory write control block 5 and buffer register 4
The number of control data signal lines between the memory read control block 8 and the buffer register 6 is 7 bits (1
There are 8 bits in total: 28-bit count signal) and 1 bit (line continuation signal). Note that the data length of one video line does not need to be an integral multiple of the data length of the shift register 3.6, and the data length of one video line is 200.

You can change it for each line, such as 300.250.

The timing chart in Figure 2 shows that after the circuit is reset using the CLII signal, the video clock WCK is used to reset the circuit.
A timing example is shown for application to frequency conversion in which video data is written and at the same time a read operation is performed using a high-speed video clock or clock RCK with respect to the video clock WCK at the time of writing. Also, Wo-w7 in the figure
.

R0 to R7 indicate memory addresses and array addresses of array 1 at the time of writing and reading, respectively. As is clear from Fig. 2, one line of video data that is input serially is divided and stored in parallel in memory array 1, and when read, it is divided and stored in memory array 1. The video data is read out in parallel multiple times and output serially. Therefore, one line of video data is stored in the memory array 1 intermittently, so that when the storage operation is interrupted, the video data stored in the memory array 1 can be read out. As a result, video data is serially input at the same time as video data is serially output at different frequencies.

Next, FIGS. 5 to 9, which show configurations for achieving the operations shown in the timing conflict chart shown in the second figure, will be explained using timing charts.

FIG. 5 shows a specific example of the circuit configuration of the memory write control block 5.

The write number address counter 10 is stored in the memory array l.
This is a counter that counts the array address when writing the memory.
Since the number of arrays in array 1 is 8, a 3-bit counter is used. The write array group address signal which is the count output of the write contention address counter 10 is sent to the memory timing control block 2 as shown in FIG. 7, and is used as the write address of the write data.

In this embodiment, the write address counter 10 is a synchronous up Φ counter, and the write address counter 10 is a synchronous up Φ counter.
! When the write address array number address signal is cleared to the value O and the enable terminal E is 1, the write number clock WC is cleared.
The count is increased by inputting K.

The write φ bit counter 11 indicates WDE! Write/write by counting the WCK signal during the signal output period.
Enable signal E of address φ counter 10 and write clear bit) - counter for generating count signal 0 In this embodiment, since the data length of shift φ registers 3 and 7 is 128 bits, the data length of 7 bits is 128 bits. Use a synchronous up counter. The write bit contention count signal of the count value is CLRl.

It is reset to the value O by the WRQt signal, and the ripple carry output RC becomes 1 when all bits become 1. This l carry output RC is used as the enable signal E of the write array contention counter 10 and as the input of the flip-flop 14. Further, the light fist bit count signal is stored in the memory array 1 along with the video data via the buffer register 4, as shown in FIG. As a result, the length of the video content data stored in each memory array is stored in association with the video data as a read Φ bit φ count signal.

D-type flip-flop 12 and AND gate 13
is a circuit for detecting the rear end of the WDE main signal,
A VEND signal as shown in the timing chart of FIG. 3 is generated. The VEND signal is logically summed by an OR gate 16 and is used as a signal to indicate the end of inputting one line of video data, and is input to the enable signal E of the write array counter 10 and the flip-flop 14. Further, the MWDE request signal delayed by one clock from the WDE main signal due to the WCK signal is stored in the memory array 1 via the buffer register 4 as shown in FIG.

This is the MWDE signal line signal in continuation signal and is used for reproducing one line of video signal during a read operation, that is, for determining the end of reproducing one line during reproducing the RDE main signal.

The output WRQ signal of the D-type flip flop 14 is used as a data write signal to the buffer register 4 as shown in FIG. 8, and as a write request signal to the memory timing control block 2 as shown in FIG. be done.

FIG. 6 shows a specific example of the circuit configuration of the memory group read control block 8.

The read address number counter 20 is a counter that counts array addresses when reading the memory array 1, and similarly to the write address counter 10, it receives a 3-bit read array address signal as shown in FIG. This is a synchronous up φ counter that outputs to the memory timing control 2 as shown in FIG. The read address counter 20 is cleared to a value O by the CLR1 signal, and is counted up by inputting the read clock RCK when the enable terminal E is 1.

The read bit φ counter 21 is a read bit φ counter 21.
This is a 7-bit synchronous down counter for counting the enable signal E of the counter 20 and the bit length for generating the RDE* signal. The lead fist bit counter 21 has a video file from the memory reference array.
Leading with data. RCK clock input for loading the write-bit Φ count signal (indicating the bit length of the read video data) into the read bit number count signal using the RLD signal and serially outputting the video data from the shift number register 7. Count every time
When the count value reaches O, the double carry signal RRC becomes 1. Therefore, when the RRC signal becomes 1, serial output of video data from the shift register 7 ends.

D type flip party flop 22. AND gate 23
, JK type flip-flop 24 is an MRD read with video data from memory array l.
RD by E main signal (-MWDE zero signal) and RLD signal
This is a circuit for generating an E* signal. That is, the flip-flop 24 is set with the RI and D signals inputted with the RDS main signal, and as a result, the RDE low signal becomes low. Then, after the serial output from the shift register 7 of the video data whose MRDE main signal in the data read from the memory array 1 is 1 is completed, the RR
The C signal resets flip-flop 24. In this way, the output light of the video data (e.g.
MRDE from input of RDS signal from laser Φ beam printer)! Shifting of video book data with signal 1
A serial output complete-1RDE low signal from register 7 can be formed. Therefore, the RDE main signal indicating the input data length of one line can be formed according to the data read clock frequency.

D type φ flip-flop 29, NOR gate 30
is the RDS as shown in the timing chart of Figure 4.
This circuit generates a read start signal, RTOP signal, from this signal.

The SR flip-flop 25, the D-type flip-flop 2B, and the AND gate 27 generate an FRRQ signal that sets the first data from the memory array l into the buffer register 4 in response to the first WRQ signal after the input of the CLR signal. This is a circuit for This FRRQ signal is O
It becomes the RRQ signal through the R gate 28. After this circuit operates, a data number set request for the buffer register 4 is made by the RTOP signal and the RRC signal. That is, the output RRQ signal of the OR gate 28 makes a data set number request to the memory timing control block 2, and in response, the memory timing control block 2 outputs the RDLD signal. Note that the FRRQ signal is already a video signal when the RDSt signal is first input.
It is used to store video data to be output first in the buffer number register 6 in advance to enable serial output of data.

FIG. 7 is a diagram showing the exchange of signal lines in the memory timing control block 2.

Memory timing control block 2 receives the WRQ signal, R
In response to the RQ signal, it outputs an array address signal and a WR multiplied signal RD signal to control data read and write operations for the memory array 1.

When the WRQ signal is accepted, the light shown in Figure 5 is activated.
When a write operation is performed using the write array address signal from the address counter 10 and the RRQ signal is accepted, the read array address signal from the numbered address counter 20 shown in FIG. RD is used to perform a read operation, and RD, which is a data latch signal to the buffer register 6 when reading data, is used to perform a read operation.
Outputs double signal.

Incidentally, when the WRQ signal and the RRQ signal are generated at the same time, priority is given to the signals so that either read or write operation can be accepted.

Figure 8 shows shift register 3 and buffer register 4.
FIG. 3 is a diagram showing the exchange of peripheral signal lines.

The video input data signal DIN is serially written into the shift register 3 by the clock WCK signal. W
The DEt signal is used as a shift operation permission signal.

Buffer register 4 is a D-type flip-flop, and the parallel data from shift register 3 is latched in response to the WRQ signal, and becomes data to be written to memory number array 1.

Figure 9 shows buffer register 6 and shift register 7.
FIG. 3 is a diagram showing the exchange of peripheral signal lines.

Contrary to FIG. 8, the parallel read data from the memory array I is latched into the pattern register 6, which is a D-type flip-flop, by the RDLD signal.

The latched data is stored in the memory read control block 8.
, and are sent to shift register 7, respectively.

The RLD signal is used as a data load signal to the shift register 7.

As mentioned above, one line of video input serially.
The data is divided and stored in parallel in memory array 1, and the divided and stored video data is sequentially read out in parallel and output as serial video conference data for one life. Storing and writing video data to 1 is performed at high speed.

Also, since the storage and readout to the memory array is performed in a time-sharing manner, readout can be performed in between storage to the memory array, thereby allowing the serial video red data to be input at the same time as the video data.・Serial output of data becomes circular.

Furthermore, since the video data storage and readout operations of the memory array 1 are performed using WCK and RCK, and these operations are performed independently, the storage and readout operations can be performed asynchronously.

In this embodiment, input data and output data each have a 1-bit memory configuration, but the shift register 3,
By increasing the number of bits in the buffer register 4, memory array 1, buffer register 6, and shift register 7 by the necessary number of bits, it becomes possible to convert to other bits.

Further, the data to be processed is not limited to video φ data, but may also be serial data output from a word processor, computer, etc., and can be used as an input/output buffer for various data.

Also, as can be seen from the timing chart in Figure 2, the write interval to the memory array L becomes longer, so even when high-speed serial input/output of video data occurs, the low-speed memory array is available.

In addition, even when dynamic fist memory is used as memory array 1, since there is a margin in timing, it has a built-in self-squeezing fresh axle, and a pseudo metal RA
M operation is easily realized and usable.

Furthermore, the line length of written data can be reproduced simply by inputting the read start timing signal, eliminating the need for a line length counter during read, which was previously required, and the circuit configuration of single memory application equipment. simplification becomes possible.

Furthermore, for the same reason, it becomes possible to deal with signals having different data lengths for each line.

〔effect〕

As explained above, according to the present invention, the data length is stored together with the input data, and the data readout for each line is performed based on the data length, so it is not necessary to externally control the data readout for 1 line and 2 minutes. The necessary data can be reliably output.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a block configuration of a memory according to the present invention, and FIGS. 2 to 4 are timing diagrams for explaining circuit operation.
5 is an explanatory diagram showing a configuration example of the memory write control block 5 in FIG. 1; FIG. 6 is a diagram showing a configuration example of the memory read control block 8 in FIG. 1; The figure shows the memory timing control block 2 in Figure 1.
FIG. 8 is a diagram showing an example of the structure around the shift register and eight-folder Φ register 4 in FIG. 1, and FIG. 7 is a diagram showing an example of the configuration around 7. FIG. In the figure, l is a memory array, 2 is a memory timing control block, 3 and 7 are shift registers, 4 and 6 are buffer registers, 5 is a memory write control block, and 8 is a memory read control block. be. Figure 6? man figure 7

Claims (1)

[Claims] A data input/output memory characterized in that input data sent for each line is stored together with its data length, and data of each line is read out based on the stored data length at the time of reading.