JPS6361324A - Data input/output memory - Google Patents

Abstract

PURPOSE:To attain the successive accommodation and the successive reading of data simultaneously and asynchronously by stopping automatically a reading action after the successive reading of the successively written data is completed. CONSTITUTION:A read address counter 20 is cleared to a value '0' with a CLR signal, and when an enable terminal E is '1', a read clock RCK is inputted and counting-up is executed. A read bit counter 21 counts a bit length to generate an enable signal E of the read address counter 20 and a line section signal RDE to show the effective section of one line of a video output data signal. After the serial output is completed from the input of a reading starting signal RDS from the output destination of video data, an RDE signal to show the data length of one inputted line can be formed in accordance with a clock frequency for reading the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to data input/output in which input data and output data can be accessed simultaneously and asynchronously.

More specifically, the present invention relates to a data input/output memory capable of converting the frequency of a video signal, synchronizing timing, delaying, etc.

[Prior art]

For example, video signals from laser beam printers that record images by scanning laser light, and video signals from televisions have a large amount of data, so the data is transferred by decomposing the image into serial signals for each line. A serial transmission method is common.

For example, when transferring data 4 to a laser beam printer, when the sending host computer sends a video signal to the laser beam printer,
It is necessary to have a buffer memory for synchronization, and to transfer the video signal using a serial transmission method in accordance with the rotation of the rotating mirror of the laser beam printer.

Such a buffer memory is also used for so-called scaling processing, which changes the size of an image by changing the frequency of a video signal.

As such a buffer memory, a first-in-first-out memory (FIFO memory) and a static RAM capable of high-speed operation are used. The former type of memory has a simple circuit configuration, but because it does not have a high speed and a large capacity, it can only be used for synchronizing five sets of data at most. On the other hand, the latter type of memory is highly versatile in terms of synchronization and scaling, but has the disadvantage that it requires address counters, selector circuits, etc., making the peripheral circuitry for memory operation complex and large-scale. There is.

Therefore, the authors first developed a sequential design that operates well without a complicated external control configuration even for high-speed data input/output, allows simultaneous and asynchronous data input/output, and is suitable for one-chip integration. proposed an accessible memory. As mentioned above, if this type of memory is used as a line buffer memory for video signals, for example, buffering for 8 lines (not limited to 8) as shown in Figure 11 is as follows: In other words, each of 1 to 8 in Fig. 11(a) has a capacity for one line of video signal, and the capacity of Fig. 11(b) (i
), according to the timing chart for writing, 1 is (
At the timing of 1), the 1st line is written, the 2nd line is written to 2...The Nth line is written to N sequentially, and when writing to the 5th line of the memory in (a), the 2nd line is written to N. ), data is read from the l-th line. In this way, the write operation and the read operation are performed sequentially, and for example, 2 times for one screen in FIG.
If you want to buffer 048 lines, it will be 204 lines.
When the 8th line is written, the 2044th line has been read. Therefore, the number of lines equivalent to the number of lines just buffered is read out. (i.e.,
In order to reproduce only the number of lines that have been written, some means of counting the number of read lines is required. For example 2048
11 bits for line, 1 bit for 4096 lines
It is 2 bits, and requires a counter control circuit, etc. Alternatively, if the input and output (writing and reading) do not have a constant period in time (that is, the time interval from writing to the same line memory to reading is not constant), the control becomes even more complicated.

〔the purpose〕

The present invention has been made in view of the above points, and it is an object of the present invention to provide a data input/output memory that operates efficiently and can be used in any manner without providing any special auxiliary circuits.

〔Example〕

The present invention will be explained in detail below based on Examples.

FIG. 1(a) is a diagram showing an example of a block configuration of a momeri to which the present invention is applied. The memory shown in the first figure is formed as a one-chip memory.

Memory array 1 includes a plurality of data bits and
This is memory that allows write operations.

The memory timing control block 2 is a block that controls the timing of read/write operations of the memory array I, addresses of the memory array, and the like.

The shift register 3 has a data length of 128 bits, and is a register for converting the digital video input data signal DIN, which is serially sent from a video data source such as an image scanner, into a parallel signal. The video data signal sent from memory write control block 5 is sent in parallel to buffer register 4, which is a buffer when writing to memory φ array 1. Buffer register 4 has a capacity of 136 bits. (
8-bit control data including line length data of the video signal is also stored at the same time and written in parallel to the memory array 1 along with the 128-bit video data signal.

The memory write control block 5 indicates the valid section of one line of the video input data signal DIN inputted from the video data source by writing the write array address signal of the memory array I and data regarding the line length. It is generated based on the line section signal WDE*.

Buffer register 6 has a capacity of 236 bits and is used when reading memory array I. The data read out in parallel from the memory array I undergoes parallel to serial data conversion via the buffer register 6, of which the video data has a data length of 128 bits 0ft to generate the video output data signal DOUT. • Control data is sent to the register 7 and also to the memory read control block 8.

The memory read control block 8 receives the read array address signal of the memory array I and the line interval signal RDE* indicating the valid interval of one line of the video output data signal DOUT from the buffer register 6. Based on data on e.g.
The read start signal is generated in synchronization with the input of the RDS tree from an image processing device such as a printer.

For example, the CLR* signal is input at the start of inputting one screen worth of video data from a video data source and is a signal used to initialize the block, and the WCK signal and RCK signal are used to input video data, respectively. Basic clock signal for video data during write and read operations generated from the source and image processing device.

be. In this embodiment, the tree symbol at the end of the signal name indicates an active low signal.

In this way, serially input video data is converted into parallel data and stored in the memory array 1, and the data is output in parallel and serially, and the storage and readout operations are performed independently, asynchronously, and at high speed. Execute.

Reference numeral 9 designates a selector for determining whether input data is to be stored in the memory array 1 as valid data or used as a preset for a write write bit counter and write address counter in a memory write circuit to be described later. In this embodiment, the data line (D
IN) is shared, the number of external control lines is minimized. The ASET signal is a signal that instructs the selector 9 to switch, and when the ASET signal is "1", the input to the selector 9 is as a preset input value of the write bit counter and write address counter.
ASS* input with address data from outside
At the rising edge of the (address set strobe) signal, one bit is input serially. Also, ASE
When the T signal is "O", the input to the selector 9 is input to the serial input of the shift register 3 at the next stage as data to be stored in the memory array 1. Figure 1 (b
) is a timing chart when 01 is input to the write array counter and 40H is input to the write bit counter.

Figures 2 to 4 show timing diagrams for explaining circuit operation.
It is a chart.

Figure 2 assumes that the data length of one video line is 512 bits, the data length of shift registers 3 and 6 is 128 bits, and memory array 1 is a memory with a 136 x 8 bit configuration (the number of arrays is 8). are doing.

In this case, memory write control block 5 and buffer
The number of control data signal lines between the register 4 and memory read control block 8 and the buffer register 6 is 7.
There are a total of 8 bits: a bit (128-bit count signal) and 1 bit (line continuation signal). In addition, 1 video
The data length of a line does not need to be an integral multiple of the data length of shift registers 3 and 6, and even if the data length of a video line changes from line to line, such as 200°300.250. good.

The timing chart in Figure 2 shows that after the circuit is reset using the CLR* signal, the video clock WCK is used to reset the circuit.
A timing example is shown for application to frequency conversion in which video data is written and, at the same time, a read operation is performed using a video clock RCK that is faster than the video clock WCK at the time of writing. Also, Wo-W7 in the figure
, Ro-R7 indicate the array address of memory array l at the time of writing and reading, respectively. As is clear from FIG. 2, 1542 minutes of video data input serially is divided and stored in parallel in memory array 1, and when read, the video data is divided and stored in memory array l.・It reads data multiple times in parallel and outputs it serially. Therefore, l
Since lines of video data are intermittently stored in memory array 1, when the storage operation is interrupted, the video data stored in memory array 1 can be read out. At the same time as the serial input of video data, the serial output of video data at different frequencies is performed.

Next, FIGS. 5 to 9, which show configurations for achieving the operations shown in the timing chart shown in the second figure, will be explained using timing charts.

FIG. 5(a) shows a specific example of the circuit configuration of the memory write control block 5. Also, Figure 5(b) shows the memory
The address map of array 1 is shown, and as shown, memory array 1 is a 136 bit x 8 array memory.

Write address-counter 10 is memory array 1
This is a presettable counter that counts array addresses when writing. In this embodiment, as described above, since the number of arrays in memory array I is 8, a 3-bit counter is used. Write address counter 1
The write array address signal with a count output of 0 is
As shown in FIG. 7, it is sent to the memory timing control block 2 and used as a write address for write data.

In this embodiment, the write address counter 10 is a synchronous up counter, and when the write array address signal is cleared to the value 0 by the CLR main signal and the enable terminal E is 1, the write clock is W.C.
The count is increased by inputting K.

The write bit counter 11 performs write operations by counting the WCK signal during the output period of the WDE* signal.
This is a presettable counter for generating an enable signal E and a write bit count signal for the address counter 10. In this embodiment, since the data length of shift registers 3 and 7 is 128 bits, a 7-bit synchronous up-counter is used.

The write bit count signal of the count value is CLR.
*Reset to value O by signal, all bits have value 1
When this happens, the ripple carry output RC becomes 1.

This l carry output RC is used as an enable signal E of the write array counter 10 and as an input of the flip-flop 14. The write bit-count signal is also stored in memory array l along with the video data via buffer register 4, as shown in FIG. The length of the video data is stored in bits 128-135 of each memory array in association with the video data as a read bit count signal.

The shift register 18 is a serial-in parallel-out shift register that provides preset inputs to the write address counter lO and the write bit counter 11, and outputs all 0s by the CLR* signal.
is cleared to ASS* in one state of the ASET signal.
(address set strobe) At the rising edge of the signal,
The address value selected by the selector 9 is manually/shifted serially. Since write bit counter 11 and array address counter IO are 7-bit and 3-bit counters, respectively, shift register 1
8 is a shift register capable of parallel output of 10 bits in total. The NOR gate 17 is used to load the 10-bit address value serially input to the shift register 18 from the outside into the write address counter lO and the write bit counter 11 in parallel at the beginning of the WDE main signal. An ADLD tree signal is generated. Therefore, if the ASS* signal is not input after the CLR* signal is input, the write bit counter 11 and write address counter 10 start counting from "0", but ASS*, ASET.

1) When a predetermined address is set by each IN signal, the WDE* signal (section signal of l line video signal)
The count starts from the set count value in synchronization with the ADLD* signal after input. For example, light
When the array count is set to 0 in the address counter 10 and the bit count in the write bit counter 11 is set to 64 (100,0000),
As shown in the address map in b), writing starts from position S of bit address 64 of array address O.

If the l line has 256 bits, data is written in the area up to bit address 64 (position E) of array address 2. On the other hand, the write bit count value (read bit count value) stored together with the video signal indicates the write bit count value after writing to l block (i.e., 128 bits corresponding to each array). Therefore, as shown in the figure, array = O is 7
FH (128 bits), array=1 indicates 7FH (128 bits), and array 2 indicates 40H (64 bits). On the other hand, when data is written, the WDE* signal is also written with l' or "0" as one bit, corresponding to the write data. A timing chart of the above video signal writing operation is shown in FIG. 5(C). That is, the data set in the shift register 3 is shown in FIG.
The WRQ signal output from the D type F/F 14 in a) is latched into the write data buffer register 4 as shown in FIG.
).

127 (7F) (), 64 (40H) are memory
written to array 1. Then, as described later, it is reproduced at the time of reading.

FIG. 6(a) shows a specific example of the circuit configuration of the memory read control block 8.

Read address counter 20
This is a counter that counts array addresses when reading data, and is a synchronous counter that outputs a 3-bit read array address signal to the memory timing control 2 as shown in Figure 7, similar to the write address counter IO.
It is an up counter. The read address counter 20 is cleared to the value O by the CLR* signal, and is counted up by inputting the read clock RCK when the enable terminal E is 1.

The read bit counter 21 receives the read address.
It is a 7-bit synchronous down counter for counting the enable signal E1 of the counter 20 and the bit length for generating the RDE tree signal. Read bit counter 21 receives video data from memory array 1.
The read bit count signal (= write bit count signal = indicating the bit length of successive video data) read together with the data is loaded by the RLD signal, and the video data is serially transferred from the shift register 7. A countdown is performed every time an RCK clock is input for output, and when the count value reaches 0, the ripple φ carry signal RRC becomes 1. Therefore, the RRC signal is 1
When this happens, the serial output of video data from the shift register 7 ends.

FIG. 6(b) shows a timing chart for reading data for one line stored in the state shown in FIG. 5(b).

The read start signal RDS* (for example, l
The RLD signal is output from the (output at the beginning of the line) signal over l blocks of the next RCK signal, and the bit count value (128 ) is the lead
Loaded into bit counter 21 and read array
128 bits are output corresponding to address O.

On the other hand, at the time of the above write, data was written from address 64, so the read bit count value was 6.
4 (40H), MRDE * (MWDE
The signal read out from the memory) becomes “LO”. In other words, from the moment the MRDE tree signal falls to LO'', the written data is output from the beginning and goes to LO from the RCK signal following the MRDE* signal, as shown in the circuit shown in Figure 6(a). and the final data (read
Array address 22. The RDE* signal which becomes "Hl" at RCK after the read bit counter address 20) is output becomes the interval signal of the written valid data.

In this way, after completing serial output from the shift register 7 of video data in which the MRDE main signal is 1 from the input of the RDS* signal from the video data output light (for example, a laser beam printer), the RDE *Can form a signal. Therefore, the RDE* signal indicating the data length of the input l line can be formed according to the data read clock frequency.

D-type flip-flop 29, NOR gate 30
is the RDS as shown in the timing chart of Figure 4.
*This is a circuit for generating the RTOP signal, which is a signal for read start from the signal.

The SR flip-flop 25, the D-type flip-flop 26, and the AND gate 27 generate an FRRQ signal that sets the first data from the memory array 1 into the buffer register 4 in response to the first WRQ signal after the CLR* signal is input. This is a circuit for This FRRQ signal is O
It becomes the RRQ signal through the R gate 28. After this circuit operates, a data set request for the buffer register 4 is made by the RTOP signal and the RRC signal. That is, the output RRQ signal of the OR gate 28 is sent to the memory timing control block 2 as a data set signal.
A request is made, and in response, the memory timing control block 2 outputs an RDLD signal. Note that the FRRQ signal is already a video signal when the RDS* signal is first input.
It is used to enable serial output of data and to store video data to be output first in the buffer register 6 in advance.

FIG. 7 is a diagram showing the exchange of signal lines in the memory timing control block 2.

Memory timing control block 2 receives the WRQ signal, R
In response to the RQ signal, data read and write operations for the memory array I are controlled (array address signal, WR times signal, RD times signal is output).

When the WRQ signal is accepted, the light shown in Figure 5 is activated.
When a write operation is performed using the write array address signal from the address counter 10 and the RRQ signal is accepted, the read array address signal from the read address counter 20 shown in FIG. It is used to perform read operations, and also uses the buffer when reading data.
Outputs the RDLD signal, which is a data latch signal to register 6.

Incidentally, when the WRQ signal and the RRQ signal are generated at the same time, priority is given to the signals so that either read or write operation can be accepted.

Figure 8 shows shift register 3 and buffer register 4.
FIG. 3 is a diagram showing the exchange of peripheral signal lines.

The video input data signal DIN is serially written into the shift register 3 by the clockwise WCK signal.

The WDE* signal is used as a shift operation permission signal.

Buffer register 4 is a D-type flip-flop, and latches parallel data from shift register 3 in response to the WRQ signal, which becomes write data to memory array l.

Figure 9 shows buffer register 6 and shift register 7.
FIG. 3 is a diagram showing the exchange of peripheral signal lines.

Contrary to FIG. 8, parallel read data from memory array I is latched into buffer register 6, which is a D-type flip-flop, by the RDLD signal.

The latched data is stored in the memory read control block 8.
, and are sent to shift register 7, respectively.

The RLD signal is used as a data load signal to the shift register 7.

FIG. 10 shows a circuit for detecting the coincidence of the written portion and the written portion.

As explained in FIG. 5(b), there is a one-to-one correspondence between the number of written lines and the write array address. Therefore, the fact that the read array address and the write array address are equal means that in the above-mentioned example of use as a multi-line buffer, the series of preceding write operations has finished and the following read operation has finished. This occurs when reading the last written line is finished, or when the same array address is accessed in the middle of a series of write 1-/read sequences.

In FIG. 10(a), when the comparator 60 detects a match between the read array address and the write array address and outputs the EQU signal, a flip signal is sent to J-.
The flop 63 is reset and the output RENB signal is “L”
Then, the input RDE tree IN signal and RCKIN
The signal is OR gate 64. 65, and the internal operation stops. This state is released by the CLR* signal. That is, when the CLR* signal is input, the flip-flop 63 is set to J-, the RENB signal is turned ON, and the R
CKIN signal and RDE*IN signal are RCK signal and R
It is supplied internally as the DE main signal to enable read operation. Further, since the inputs of the comparator 60 are each reset to O by the CLR tree signal, the comparison by the comparator 60 becomes effective after the first read operation is completed. The RENB signal is output to the outside as is, and becomes "1" when the reading of the written data is completed, so the external circuit detects this and considers it to be the end of buffering for one screen. There is no need to provide any external counter means.

As mentioned above, 1542 minutes of video input serially.
The data is divided and stored in parallel in memory array l, and the divided and stored video data is sequentially read out in parallel and output as one line of serial video data. The storage and writing of video data to 1 is performed at high speed. Also, storing and reading from the memory array
Because it is done in a time-sharing manner, reads can be performed between stores to the memory array, thereby allowing serial output of video data at the same time as input of serial video data.

Furthermore, since the video data storage and read operations of the memory array I are operated by WCK and RCK, respectively, and are operated independently, the storage and read operations can be performed asynchronously.

Furthermore, in the present invention, the end signal is output after reading only the number of actually written lines, so the external circuit only has to consider this signal as the end of one screen, and externally counts the number of lines. A counter or the like is not required, and the circuit is significantly simplified. Furthermore, it can also be used as an ERROR signal for abnormal accesses such as when a read operation catches up with a sequential line write operation and accesses the same array.

Furthermore, in the present invention, since the write start address can be externally controlled, for example, if the horizontal synchronization signal of an LBP (laser beam printer) is used as the RDS tree (read start) signal, the written 15
It becomes easy to shift the horizontal synchronization signal by the desired number of pixels for 42 minutes of data, and by using this memory, the number of peripheral circuits can be significantly reduced. Furthermore, since the address count preset value input is a serial input and the input is also shared with the data input line, the number of external control lines can be reduced as much as possible.

Furthermore, in the present invention, after reading only the number of actually written lines, it automatically stops even if a read signal is output from the outside, so there is no need for a control circuit etc. to control the number of lines read to the outside. The circuit is simplified.

Furthermore, the line length of written data can be reproduced simply by inputting a read start timing signal, eliminating the need for a line length counter during read, which was previously required, and the circuit configuration of this memory application device. simplification becomes possible.

Furthermore, for the same reason, it becomes possible to deal with signals having different data lengths for each line.

In this example, the process was terminated by checking the match between the outputs of the array address counter, but the number of lines written internally (number of WDE trees) and the number of lines read (RD
It can be easily inferred that even if a counter is used to count the number of E*, the invention can be implemented without detracting from the spirit of the invention.

〔effect〕

As explained above, according to the present invention, it is possible to operate efficiently without providing any special additional equipment externally, and
It is possible to provide a data input/output memory that can operate in any manner.

[Brief explanation of drawings]

FIG. 1(a) is a diagram showing an example of the block configuration of a memory according to the present invention, FIG. 1(b) is an operation timing chart diagram of FIG. 1(a), and FIGS. 2 to 4 are: Timing for explaining circuit operation
Chart diagram; FIG. 5(a) is an explanatory diagram showing a configuration example of the memory write control block 5 of FIG. 1(a); FIG. 5(b) is a diagram showing an address map of the memory array; 5(C) is an operation timing chart of FIG. 5(a), FIG. 6(a) is a diagram showing a configuration example of the memory read control block 8 of FIG. 1, and FIG. b) is the operation timing chart of FIG. 6(a), and FIG. 7 is the memory timing control block 2 of FIG.
8 is a diagram showing an example of the structure around the shift register and buffer register 4 in FIG. 1, and FIG. 9 is a diagram showing an example of the structure around the shift register and buffer register 4 in FIG. Figure 10(a) is a diagram showing an example of the peripheral configuration. Figure 10(a) is a circuit diagram for detecting coincidence between a write address and a read address. Figure 10(b) is a diagram showing the operation timing of Figure 10(a).
This is a chart diagram, and FIG. 11 is a diagram showing the prior art. In the figure, 1 is a memory array, 2 is a memory timing control block, 3 and 7 are shift registers, 4 and 6 are buffer registers, 5 is a memory write control block, and 8 is a memory read control block. .

Claims (1)

[Claims] It has a built-in write address counter, read address counter, and input/output shift register so that it can simultaneously and asynchronously store and read data sequentially.
A data input/output memory characterized in that it has a stop control means that automatically stops a read operation after sequentially reading data that has been sequentially written is completed.