JPH07182496A - Image processor - Google Patents

Abstract

PURPOSE:To execute the rotation of an image and the rotation processing of a mirror at high speed as against plural image data whose number of bits in one picture element differ and to inexpensively constitute an image processor. CONSTITUTION:Image data are alternately written into buffer memories 9 and 10, and they are alternately read. Image data which are read from the buffer memories 9 and 10 are synthesized into word data of prescribed bit width by the use of a word synthesis circuit 13. Reading from the buffer memories 9 and 10 and writing into the word synthesis circuit 13 are controlled in accordance with the indicated angles of rotation and mirror rotation. At the time of writing from the word synthesis circuit 13 into a page memory 17, a write order is controlled in accordance with the rotation angle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to the case where the number of bits of one pixel of input image data is different,
The present invention relates to an image processing apparatus that generates an image in which an input image is rotated by a rotation angle that is an integral multiple of 90 ° or is a mirror image rotation, and outputs and stores the image in a page memory.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus that rotates an input image or a mirror image of the input image is known. For example, Japanese Patent Laid-Open No. 4-183169 discloses that image data is written / read to / from a page memory in a cycle of image data in units of bits.

[0003]

By the way, a page memory requires a large storage capacity, and therefore a DRAM is usually used. However, since the minimum random read / write cycle of a DRAM is usually 100 nsec or more, the method disclosed in Japanese Patent Laid-Open Publication No. Hei 4 (1999) -53242 is adopted. -1
In the technique disclosed in Japanese Patent No. 83169, when the number of bits per pixel of image data is 1 bit, the frequency that can be used as a video clock or a pixel clock is up to about 10 MHz, and image processing can be performed at high speed. There is a problem that can not be done.

Actually, in recent years, it has been required that image processing such as rotation or mirror image rotation can be performed in real time on a high resolution image. For this reason, a video clock frequency of about several tens MHz is used. Is becoming popular.

Of course, even in the one disclosed in Japanese Patent Laid-Open No. 4-183169, if an SRAM capable of high-speed processing is used as a page memory, it is possible to support a video clock of several tens of MHz. Not only does the cost increase, but the size of the entire device also increases.

Further, in the method disclosed in Japanese Patent Laid-Open No. 4-183169, since writing / reading of data in the page memory is performed in a cycle of image data in a bit unit, for example, a minimum random read / write cycle is performed. Even if the page memory is configured using a high-speed SRAM of about 10 nsec, the video clock for processing binary images, that is, image data in which 1 pixel is 1 bit, is 100 MHz, but the number of information bits in 1 pixel is 8 bits. When processing the image data of, the frequency of the video clock is limited to 12.5 MHz, and it is difficult to process the high resolution image data at high speed.

Further, in the one disclosed in Japanese Patent Application Laid-Open No. 4-183169, the image data is not stored in a continuous address from the writing start address on the page memory by the size of the image data, but is stored in the image memory. Since the row / column is assigned to a fixed address bit of the page memory, there is a problem that a wasteful unused area occurs in the page memory.

Further, assuming that the number of information bits of one pixel is N and the word width of the page memory is W (≠ N) bits, when the image data is stored in the page memory, (W / N ) × (W / N) pixel unit blocks must be taken into consideration, but in the one disclosed in Japanese Patent Laid-Open No. 4-183169, the row / column of the image is assigned to a fixed address bit of the page memory. Therefore, for example, when an image scanner that outputs image data in which the number of information bits of one pixel is different from the predetermined number of bits is connected, the configuration of the image processing unit must be changed. Occurs.

The present invention solves the above-mentioned problems, and can perform rotation or mirror image rotation processing on input image data in real time and at high speed without using a high-speed storage device for the page memory. It is an object of the present invention to provide an image processing device that can be used.

It is another object of the present invention to provide an image processing apparatus capable of storing image data at consecutive addresses on a page memory, and thus a wasteful unused area is generated in the page memory. And

A further object of the present invention is to provide an image processing apparatus capable of performing rotation or mirror image rotation processing on input images having different numbers of information bits per pixel.

[0012]

In order to achieve the above object, the image processing apparatus of the present invention rotates an input image having a bit number N per pixel by an angle which is an integral multiple of 90 ° or a mirror image. In an image processing apparatus for outputting and storing in a page memory having a word width of W bits in a mode, a specifying unit for specifying a rotation angle, an image size and mirror image on / off, and image data of an input image for at least W / N lines are primary. A primary storage means composed of a buffer memory having a word width of B bits to be stored, an input means for inputting input image data in parallel to the primary storage means for each B / N pixel, and a bit number N per pixel of the input image are designated. The write address and the read address of the buffer memory of the primary storage means for each W / N line according to the rotation angle and the image size designated by the means and on / off of the mirror image. Control means for controlling image data to write and read image data in a predetermined order, and at least B / for synthesizing W-bit word data to be output from the image data read by the control means to the page memory. The image data read by the control means is designated by the secondary storage means composed of N W-bit registers and the number of bits per pixel of the input image by the designation means in the register of the secondary storage means. Designated by the designating means, the synthesizing means for synthesizing the W-bit word data by setting them in a predetermined order according to the rotation angle, the output control means for outputting the synthesized W-bit word data in the predetermined order. Corresponding to the rotation angle, the page data is output in a form in which the input image is rotated by the rotation angle or the mirror image of the word data output by the output control means. And address control means for controlling the write address of the page memory so as to be stored in the memory.

[0013]

In the image processing apparatus of the present invention, the random read / write cycle of the buffer memory as the primary storage means and the register as the secondary storage means is (B / N) × (video clock cycle), and the page memory Since the random write cycle of the image data is (W / N) × (video clock cycle), for example, B = 4, W = 8, N = 1
Also, assuming that the video clock is 50 MHz, an inexpensive SRAM with a random read / write cycle of 80 nsec can be used as the buffer memory, and a random read / write cycle of 1 nm as the page memory.
It is possible to rotate or mirror-image rotation using an inexpensive DRAM of 60 nsec.

Further, in the image processing apparatus of the present invention, it is not necessary to fix the number of bits N per pixel of the input image data to one type, and by setting the value of N, images having various numbers of information bits are set. The data can be processed for rotation or mirror image rotation.

Further, in the image processing apparatus of the present invention, the image reading efficiency of the image scanner can be improved. This is because in the present invention, when the mirror image rotation process is performed, the image is read even when the image scanner returns to scan, and the image data obtained at that time is processed, so that only one direction is scanned as in the conventional case. The efficiency of image reading can be improved as compared with the image scanner.

[0016]

Embodiments will be described below with reference to the drawings.
In the embodiments described below, the image processing apparatus has image data in which the number of information bits of one pixel is 1 bit, that is, N = 1, and information bit number of one pixel is 2 bits, that is, N =
Two image data can be rotated or mirror-image rotated, and the word width of the buffer memory is 4 bits, that is, B = 4, and the word width of the page memory is 8 bits, that is, W = 8. And

FIG. 1 is a diagram showing the configuration of an embodiment of the image processing apparatus of the present invention. The image input device 1 inputs image data to the image processing device of the present invention, and outputs image data synchronized with a video clock together with control signals such as a line synchronization signal and a page synchronization signal.

The image input interface 2 is an interface for taking in image data from the image input device 1, and is synchronized with the video clock from the image input device 1 using a control signal such as a page sync signal and a line sync signal. The output image data is loaded into the image processing device.

The parallel conversion circuit 3 aligns N-bit image data of one pixel synchronized with the video clock for each (B / N) pixel and converts it into B-bit parallel data.

The multiplexers 4, 5, 6 are connected to the control circuit 2
A control signal from 0 selects and outputs one of the two input data.

The bidirectional buffers 7 and 8 respectively input the image data output from the parallel conversion circuit 3 to the buffer memory # A9 and the buffer memory # B10, and multiplex the image data read from the respective buffer memories. 4 is input.

Buffer memory # A9, buffer memory #
B10 is for temporarily storing the input image data, and is configured by a storage device such as SRAM. As described above, the word width of these buffer memories 9 and 4 is 4 bits, that is, B = 4.

Buffer memory write address generation circuit 1
1 is buffer memory # A9 or buffer memory #
The line address is generated when the image data is written in B10.

Buffer memory read address generation circuit 1
2 is buffer memory # A9 or buffer memory #
The read address is generated when the image data is read from B10.

The word synthesizing circuit 13 synthesizes a W-bit word from the image data read from the buffer memory # A9 or the buffer memory # B10 so as to generate a rotated image.

Page memory write address generation circuit 14
Is a word synthesizing circuit 13 so that the input image is output to the page memory in a desired rotated or mirror-image rotated manner.
The write address is generated when the image data having the W-bit word width synthesized by is written in the page memory 16.

The page memory interface 15 serves as an interface between the page memory 16 and the image processing apparatus.

The page memory 16 stores image data obtained by rotating or mirror-rotating an input image by the image processing apparatus, and is composed of a storage element such as DRAM.

The CPU 17 sets a rotation angle, setting of whether or not to perform a mirror image, an input image size, a value of the information bit number N of one pixel of the input pixel, and the like in the register 18, various instructions such as an instruction to start processing. Give instructions.

The register 18 has one of the rotation angle, the input image size, the mirror image designation, and the input image set by the CPU 17.
The number of information bits N of a pixel is stored and held.
The rotation angle set in the register 18 is 0 °, 180 °
°, clockwise 90 ° (hereinafter clockwise is referred to as CW),
In the case of CW270 °, the DEG # 1 signal and the DEG # 0 signal, which will be described later, take the values shown in FIG. 30A, respectively, and the MIR is set in accordance with the mirror image designation set in the register 18.
ROR signal Takes the value shown in FIG. 30B.

The CPU interface 19 is the CPU 1
It interfaces with 7. The control circuit 20 centrally controls the operation of the entire image processing apparatus.

The process flow will be described below. The image data taken in from the image input device 1 to the image input interface 2 is input to the parallel conversion circuit 6. As shown in FIG. 2, the parallel conversion circuit 6 is composed of D-type flip-flops 101 to 106 and a 4-bit 2-input / 1-output multiplexer 107.

In FIG. 2, when the rotation process is executed, the reset signal nRESET is set prior to the start of the process.
Is asserted, and the D-type flip-flops 101 to 106 are initialized by this signal. After that, the image data is input together with the video clock CLK. However, when the number N of information bits of the input image is 2, the data signal line D in the figure is used.
Image data is input to 0 and D1 in synchronization with the video lock. When N = 1, the image data is input to the data signal line D0 in synchronization with the video clock.

The SELN signal has a value shown in FIG. 30C according to the information bit number N of one pixel of the input image, and this signal causes the information bit number N of one pixel to be N =
In the case of 2, every two pixels are converted into 4-bit data in parallel, and in the case of the number of information bits of one pixel N = 1, every four pixels are converted into 4 bits.
It is converted to bit data in parallel.

The image data parallel-converted by the parallel conversion circuit 3 is stored in the buffer memory # according to the address generated by the buffer memory write address generation circuit 11.
(W / N) lines are written in A9. Next (W
/ N) line image data is similarly written in the buffer memory # B10 according to the address generated by the buffer memory write address generation circuit 11, but at the same time, the image data written in the buffer memory # A9 is buffered. It is read according to the address generated by the memory read address generation circuit 12. Thereafter, the buffer memory # A9 is provided for each (W / N) line of the input image data.
And the buffer memory # B10 alternately write and read image data.

The buffer memories # A9 and # B10 perform state transitions as shown in FIG. 3 when writing / reading image data. In the figure, state 11
0 is the initial state, and in this state, the write enable signal nWENB for controlling the operation of the buffer memory write address generating circuit 11 and the read enable signal nRENAB for controlling the operation of the buffer memory read address generating circuit 12 are at H (high level). ) Has been negated.

After that, a start signal S indicating the start of processing
When TART is asserted, the state 111 is entered. In this state 111, the write enable signal nWENAB
Is asserted to L (low level) and the buffer memory write address generation circuit 11 operates, so that image data for (W / N) lines is written in the buffer memory # A9, but at this time, the buffer memory # B10 is idle. It is in a state.

Buffer memory write address generation circuit 1
When 1 generates a write address for (W / N) lines, the write completion signal WC is asserted from the buffer memory write address generation circuit 11 for one clock cycle, and the state transits to the state 112. In this state 112, both the write enable signal nWENAB and the read enable signal nRENAB are negated to H, and the multiplexer 5 switches the address of the buffer memory # A9 to the buffer memory read address generation circuit 12 side.
The address of the buffer memory # B10 is the multiplexer 6
Switches to the buffer memory write address generation circuit 11 side, and the multiplexer 4 selects the read data of the buffer memory # A9.

State 112 then transitions to state 113.
In the state 113, the buffer memory # A9 is reading image data, and the buffer memory # B10 is writing image data. The write enable signal nWENAB and the read enable signal nRENAB are set.
Are both asserted low.

Buffer memory write address generation circuit 1
1 is the asserted write enable signal nWE
When operated by NAB and a write address for (W / N) lines is generated, the write completion signal WC is asserted for one clock cycle. Further, the buffer memory read address generation circuit 12 operates by the asserted read enable signal nRENAB, and when the read address for (W / N) lines is generated, asserts the read completion signal RC for one clock cycle.

State 113 transits to state 114 when only write completion signal WC is asserted, and state 11 when only read completion signal RC is asserted.
5 and transits to the state 116 when both the write completion signal WC and the read completion signal RC are asserted.

In the state 114, the buffer memory # A9 is reading image data (nRENAB = L).
The buffer memory # B10 is in the idle state. Then, the state 114 transits to the state 116 when the read completion signal RC is asserted.

The state 115 is a state in which the buffer memory # A9 is in the idle state and the buffer memory #B is writing data (nWENAB = L). And state 11
5 is in state 11 when the write completion signal WC is asserted.
Transition to 6.

The state 116 is the write enable signal nW.
Both ENAB and the read enable signal nRENAB are negated to H, the address of the buffer memory # A9 is switched to the buffer memory write address generation circuit 11 side by the multiplexer 5, and the address of the buffer memory # B10 is buffer memory by the multiplexer 6. It is switched to the read address generation circuit 12 side, and the multiplexer 4 selects the read data of the buffer memory # B10.

State 116 then transitions to state 117.
The state 117 is a state in which the buffer memory # A9 is writing image data and the buffer memory # B10 is reading image data, and the read enable signal nR.
Both ENAB and the write enable signal nWENAB are asserted to L. Then, the state 117 is the state 1 when only the write completion signal WC is asserted.
18, and when only the read completion signal RC is asserted, the status transits to state 111 and the write completion signal W
When both C and the read completion signal RC are asserted, the state transits to the state 112.

The state 118 is a state in which the buffer memory # A9 is idle and the buffer memory # B10 is reading data (nRENAB = L). Then, the state 118 transits to the state 112 when the read completion RC is asserted, and returns to the initial state of the state 110 when both the read completion signal RC and the input image all data read completion signal END are asserted. .

Buffer memory write address generation circuit 1
As shown in FIG. 8, 1 is a buffer memory write address generation circuit 160 for writing N = 1 image data.
And a buffer memory write address generation circuit 162 for writing image data of N = 2, 14 bits 2 inputs /
1-output multiplexer 161 and 1-bit 2-input /
It is composed of a one-output multiplexer 163.

The multiplexer 161 has WADD1, W
One of the two inputs of ADD2 is selected by the select signal SELN and output as a WADD signal. This WAD
The D signal indicates the write address of the buffer memory. The select signal SELN takes a value shown in FIG. 30C according to the number N of information bits of one pixel of image data.

The multiplexer 163 selects one of the two inputs WC1 and WC2 based on the select signal SELN and outputs it as a WC signal. The WC signal is a signal indicating the completion of writing.

Buffer memory write address generation circuit 1
An example of the configuration of 60 is shown in FIG. In the figure, LDATA1
Is a data signal and its value is ((NF / 2) -1). This value is previously calculated by the CPU 17 for the number of pixels NF in the main scanning direction of the input image data from N = 1 (NF × N / B−
This is a value calculated in 1) and set in the register 18, and indicates the image size. The ZERO signal is a data signal having a value of 0, and the MIRROR signal is a signal having a value shown in FIG. 30B with respect to ON / OFF of the mirror image. CLK
Reference numeral 4 is a clock signal obtained by dividing the video clock by 4. The multiplexer 130 outputs the data signal LDATA1 when the mirror image is on and the data signal ZERO when the mirror image is off.
To output.

In the figure, 131 is an 11-bit loadable down counter, 132 is an 11-bit loadable up / down counter, and 133 is a 3-bit up counter. The count output of the up / down counter 132 is WADD1 # 0 to WADD # 10 which are the lower 11 bits of the write address WADD1 of the buffer memory. The count output of the up counter 133 is WADD1 # 11 to WADD1 # 13 which are the upper 3 bits of the write address WADD1 of the buffer memory. The up-down counter 132 counts down when the mirror image is on, and counts up when the mirror image is off.
The WC1 signal is a write completion signal of the buffer memory write address generation circuit 160, and is asserted to H when the write is completed.

FIG. 5 is a diagram showing a configuration example of the buffer memory write address generation circuit 162, in which the data signal LDA is used.
The value of TA2 is ((NF / 4) -1). This value is CP
U17 is the number of pixels NF in the main scanning direction of the input image data in advance
Is a value set in the register 18 by calculating (NF × N / B−1) for N = 2, and indicates the image size. The ZERO signal is a data signal having a value of 0, and the MIRROR signal is shown in FIG.
This signal has a value of 0B. CLK2 is a clock signal obtained by dividing the video clock by two. When the mirror image is on, the multiplexer 134 outputs the data signal LDATA2.
When the mirror image is off, the data signal ZERO is selected and output.

In the figure, 135 is a 12-bit loadable down counter, 136 is a 12-bit loadable up / down counter, and 137 is a 2-bit up counter. The output of the up / down counter 136 is WADD2 # 0 to WADD2 # 11 which are the lower 12 bits of the write address WADD2 of the buffer memory. The count output of the up counter 137 is WADD1 # 12 to WADD1 # 13 which are the upper 2 bits of the write address WADD2 of the buffer memory. The up / down counter 135 counts down when the mirror image is on and counts up when the mirror image is off. WC2
Is a write completion signal of the buffer memory write address generation circuit 162, which is asserted to H when the write is completed.

FIG. 10 is a diagram showing the generation order of the write addresses generated by the buffer memory write address generation circuit 11 when the mirror image is off, and FIG. 11 is the write generated by the buffer memory write address generation circuit 11 when the mirror image is on. It is a figure showing the generation order of an address. The buffer memory # A9 and the buffer memory # B10 have the same address generation order. Note that in FIGS. 10 and 11, the Y address is the upper log of the write address.
It is represented by ₂ (W / N) bits and the X address is represented by the lower log ₂ (NF × N / B) bits of the write address.

FIG. 10 shows that the mirror image is off, that is, MIRROR.
= L indicates the generation order of the buffer memory write address, and the writing of the image data is performed at the address Y =
It starts from 0, X = 0, increments by 1 for (NF × N / B-1) times to generate an address, and when address Y = 0, X = (NF × N / B-1), Then, the address upper log ₂ (W / N) bit is incremented by 1 and the value of the address lower log ₂ (NF × N / B) bit is returned to 0 to generate address Y = 1 and X = 0. Then, in the same manner, an address is generated as shown in the figure by incrementing by 1 for (NF × N / B−1) times, and addresses Y = W / N−1 and X = NF × N / B−1. When the address is generated up to, the write completion signal WC is asserted.

FIG. 11 shows that the mirror image is on, that is, MIRROR =
It is a figure which shows the generation order of the buffer memory write address in case of H, Address Y = 0, X = NFxN / B-1
Starts writing from 1 to 1 for (NF × N / B-1) times
Decrement to generate address and address Y =
When 0 and X = 0, the next higher address log ₂ (W /
N) bit is incremented by 1 and address lower log
₂ Set the value of (NF x N / B) bits to (NF x N / B-1)
Then, the addresses Y = 1 and X = NF × N / B−1 returned to are generated. Then, again, similarly, (NF × N / B−1) times are decremented by 1 to generate addresses as shown, and when addresses Y = W / N−1 and X = 0 are generated, The write completion signal WC is asserted.

FIG. 9 is a diagram showing the buffer memory read address generation circuit 12, which is a buffer memory read address generation circuit 16 for reading N = 1 image data.
4, a buffer memory read address generation circuit 166 for reading out image data of N = 2, a 14-bit 2-input / 1-output multiplexer 165, and a 1-bit 2-input / 1-output multiplexer 167.

The multiplexer 165 has RADD1, R
One of the two inputs of ADD2 is selected by the select signal SELN and output as the RADD signal. This RAD
The D signal indicates the read address of the buffer memory. The select signal SELN takes a value shown in FIG. 30C according to the number N of information bits of one pixel of image data.

The multiplexer 167 selects one of the two inputs RC1 and RC2 based on the select signal SELN and outputs it as an RC signal. The RC signal is a signal indicating the completion of reading.

The read address of the buffer memory is the rotation angle, and the current image data is the buffer memory #
It is controlled according to whether it is being read from A9 or the buffer memory # B10.

FIG. 12 is a diagram showing the generation order of read addresses of the buffer memory when the rotation angles are 0 ° and 180 °. In this case, the buffer memory # A9 and the buffer memory # B10 have the same address generation order. In FIG. 12, the Y address is represented by the upper log ₂ (W / N) bits of the read address, and the X address is the lower log ₂ (NF × N / N) of the read address.
B) Represented in bits.

In FIG. 12, the read address Y: X = 0: 0 is initially generated. And (NF × N / B
-1) One increment is performed only once, and the address Y:
When X = 0: (NF × N / B−1), the next higher lo
The value of the g ₂ (W / N) bit is decremented by 1 to generate the address Y: X = 1: (NF × N / B−1).

After that, the address is generated as shown by decrementing by 1 for (NF.times.N / B-1) times, and addresses are generated up to the address Y: X = (W / N-1): 0. The read end signal RC is asserted.

FIG. 13 is a diagram showing the generation order of read addresses for the buffer memory # A9 when the rotation angles are 90 ° and 270 °. In this case, the read address Y: X = 0: 0 is generated first, and then the upper address log
₂ The value of (W / N) bit is incremented by 1 (W / N) times to generate an address, and the address Y: X =
(W / N-1): When it becomes 0, the next higher address log
The value of the ₂ (W / N) bit is returned to 0 and the lower address lo
g ₂ (NF × N / B) bit is incremented by 1,
Address Y: X = 0: 1 is generated. After that, addresses are generated as shown in the figure, and the addresses Y: X = (W /
N-1): When (NF × N / B-1) is generated, the read end signal RC is asserted.

FIG. 14 is a diagram showing the generation order of the read address of the buffer memory # B10 when the rotation angles are 90 ° and 270 °. In this case, first, the read address Y: X = 0: (NF × N / B−1) is generated, and then the value of the upper address log ₂ (W / N) bit is changed to (W
/ N) is incremented by 1 to generate an address, and the address Y: X = (W / N−1) :( NF × N /
B-1), the next higher address log ₂ (W /
N) The value of bit is reset to 0, and the lower address log
₂ (NF × N / B) bits are decremented by 1 to generate the address Y: X = 0: (NF × N / B-2). Thereafter, addresses are generated as shown in the figure, and when the address Y: X = (W / N-1): 0 is generated, the read end signal RC is asserted.

FIG. 6 shows a configuration example of the buffer memory read address generation circuit 164. In the figure, 140 is an 11-bit loadable up / down counter, 141 and 142 are 3-bit up counters, and 143 is an 11-bit loadable down counter. Here, up counter 1
42 and the down counter 143 count the number of data read from the buffer memory, and the count outputs of the up / down counter 140 and the up counter 141 respectively include the lower 11 bits and the upper 3rd bits of the 14-bit read address RADD1. Is generating.

The buffer memory read address generation circuit 164 has LDAT1, DEG # 1, and BUFNU.
M, nRENAB and CLK4 are input. LDAT1
Is a data signal stored in the register 18, and its value is (NF / 2-1). DEG # 1 is a signal that takes a value shown in FIG. 30A according to the rotation angle, and this value is also stored in the register 18. BUFNUM
Is a signal that becomes L when the image data is read from the buffer memory # A9 and becomes H when the image data is read from the buffer memory # B10. Also, nRE
NAB is a read enable signal output from the control circuit 20, and CLK4 is a clock signal obtained by dividing the video clock by four.

FIG. 7 is a diagram showing a configuration example of the buffer memory read address generation circuit 166, in which 150 is a 12-bit loadable up / down counter and 15 is a loadable up / down counter.
1 and 152 are 2-bit up counters, and 153 is 12
It is a bit loadable down counter. The up counter 152 and the down counter 153 count the number of image data read from the buffer memory, that is, the number of generated addresses.
The count output of 0 and the up counter 151 respectively generate the lower 12 bits and the upper 2 bits of the 14-bit read address.

The buffer memory read address generation circuit 166 is provided with LDAT2, DEG # 1, BUFNU.
M, nRENAB and CLK2 are input. LDAT2
Is a data signal stored in the register 18, and its value is (NF / 4-1). DEG # 1 is a signal that takes a value shown in FIG. 30A according to the rotation angle, and this value is also stored in the register 18. BUFNUM
Is a signal that becomes L when the image data is read from the buffer memory # A9 and becomes H when the image data is read from the buffer memory # B10. Also, nRE
NAB is a read enable signal output from the control circuit 20, and CLK4 is a clock signal obtained by dividing the video clock by two.

The multiplexer 4 has a buffer memory #A.
9 or 4-bit image data read from the buffer memory # B10 is selected and input to the word synthesizing circuit 13.

FIG. 15 is a diagram showing a configuration example of the word synthesizing circuit 13. The word synthesizing circuit 13 includes bit registers 170, 171, 172, 173, and an 8-bit 4-input-1-output multiplexer 174. The 4-bit data output from the multiplexer 4 is input to the registers 170, 171, 172, and 173, and the 8-bit data held by each register is input to the multiplexer 174.

The register 170 is composed of eight register components W0 to W7 for storing 1-bit data,
Similarly, register 171 has eight register components X0.
~ X7, register 172 is eight register component Y0
~ Y7, register 173 is eight register components Z0
~ Z7.

A circuit diagram of the register component W0 is shown in FIG. In the figure, 180 is a 1-bit 4-input-1-output multiplexer, 181 and 183 are 1-bit 2-input-1-output multiplexers, and 182 is a D-type flip-flop for storing 1-bit data. BDAT is 4-bit data output from the multiplexer 4. CLK is a video clock. CDAT1, CD
AT2 is an 11-bit loadable down counter 14 of the buffer memory read address circuit 164.
3 and the 12-bit loadable down counter 153 of the buffer memory read address circuit 166.

The signal DIR is a signal for controlling how data is set in the register 170 and its direction, and the most significant bit M of the register 170 is set.
In the case of backward set in which data is set from SB to the least significant bit LSB, it becomes L, and L of the relevant register
It is a signal which becomes H in the case of backward setting in which data is set from SB to MSB.

This DIR signal is generated by the data set direction circuit shown in FIG. 17, LDAT1 and LDAT2 are the count output of the 3-bit up counter 142 of the buffer memory read address circuit 164 shown in FIG. 6 and the count output of the 2-bit up counter 152 of the buffer memory read address circuit 166 shown in FIG. 7, respectively. Is.

The same applies to the other register components.

The word synthesizing circuit 13 uses the buffer memory #
Each time (W / N) pieces of data are read from A9 and # B10, (B / N) pieces of word data are generated and output. In other words, when N = 1, four word data are generated each time 8 data is read from the buffer memory, and when N = 2, two word data are generated each time 4 data is read from the buffer memory. Output.

Here, when N = 1, the register 17
Using four registers of 0 to 173, eight data are read from the buffer memory, and every time four word data are synthesized in the four registers of 170 to 173, the multiplexer 174 outputs the 8-bit word data WDAT1,
The word data WDAT is selected and output in the order of WDAT2, WDAT3, WDAT4. When N = 2, two registers 170 and 171 are used,
Read four data from the buffer memory,
Every time two word data are combined in two registers of 0 and 171, the multiplexer 174 sets the word data WD in the order of 8-bit word data WDAT1 and WDAT2.
Selectively output AT.

Next, each register 1 of the word synthesis circuit 13
How to set data in 70 to 173 will be concretely shown.

18A and 18B show the case where N = 1,
In addition, when the rotation angle is 0 °, the word composition of the image data of the odd line when the image start line is the odd line is shown. In FIGS. 8A and 8B, the time taken to read out eight pieces of data from the buffer memory is set as one cycle, and this one cycle is set as one data.
It is divided into T1 to T8 at the timing of reading the two.
The same applies hereinafter.

The read 4-bit data is B
3 (MSB), B2, B1, B0 (LSB), and the numbers attached to the right shoulders of the bit representations indicate at which timings T1 to T8 the bits were read. Therefore, for example, the bit "B3 ¹ " indicates that the bit is read at the timing of T1.

The 4-bit data read first is set in the register components W0 to W3 of the register 170 as shown in FIG. 18A, and the 4-bit data read next is stored in the register 170. Register component W4
~ Set to W7. After that, data is set as shown in FIG. 18A, and when the eighth 4-bit data is set in the register components Z4 to Z7 of the register 173 as shown in FIG.
The word data WDA is synthesized by the multiplexer 174 sequentially from WDAT1 to WDAT4.
Select and output T.

FIGS. 19A and 19B show word composition of image data of even lines when N = 1 and the rotation angle is 0 °. The view of this figure is the same as that described above.

Similarly, FIGS. 20A and 20B show word combination of image data of odd lines when N = 1 and the rotation angle is 180 °. Similarly, FIGS.
24A and 24B show word combination of image data of even lines when N = 1 and the rotation angle is 180 °, and FIGS. 24A and 24B show N = 1 and the rotation angle C.
26A and 26B show word combination of data in the case of W 270 °, and FIGS. 26A and 26B show word combination of image data in the case of N = 1 and the rotation angle is CW 90 °.

In FIG. 22A, N = 0 and the rotation angle is 0.
FIG. 22B is a diagram showing word composition of image data of each odd line when the image start line is an odd line in the case of 0 °, and FIG. 22B shows N = 0 and the rotation angle is 0 °.
FIG. 9 is a diagram showing word combination of image data of even lines when the image start line is an even line. In FIGS. 22A and 22B, the time taken to read four pieces of data from the buffer memory is one cycle, and this one cycle is divided into T1 to T4 at the timing of reading one data. The same applies hereinafter.

The read 4-bit data is B
3 (MSB), B2, B1, and B0 (LSB), and the number attached to the right shoulder of each bit expression indicates at which timing T1 to T4 the bit was read. Therefore, for example, the bit "B3 ¹ " indicates that the bit is read at the timing of T1.

Now, in the case of image data of odd lines,
First, one piece of data read out is the register components W0 to W7 of the register 170 as shown in FIG. 22A.
Is set to. After that, the data is set as shown in FIG. 22A, and the fourth data is stored in the register 171.
When the register components X4 to X7 are set, the word synthesizing circuit 13 synthesizes two pieces of word data, so that the multiplexer 174 selects the word data WDAT1,
WDAT2 is sequentially selected and output. This is the word data WDAT.

FIG. 22B in the case of image data of even lines.
Is set as shown in, and word data is synthesized,
The signals are sequentially output by the multiplexer 174.

In FIG. 23A, N = 2 and the rotation angle is 1
FIG. 23B shows the word composition of the image data of the odd line in the case of 80 °, and FIG. 23B shows the word composition of the image data of the even line in the case of N = 2 and the rotation angle of 180 °. Is Note that FIG. 23A,
The view of B is the same as that described above. The same applies hereinafter.

FIG. 25 shows word composition of image data when N = 2 and the rotation angle is CW 270 °. FIG. 27 shows N = 2 and the rotation angle is CW90. It shows a word composition of image data in the case of °.

The 8-bit word data synthesized by the word synthesizing circuit 13 as described above is written in the page memory 16 based on the write address generated by the page memory write address generating circuit 14. The write address generated by the address generation circuit 14 is supplied to the page memory interface 15 in association with the word data from the word synthesis circuit 13 under the control of the control circuit 20. As a result, the page memory interface 15 performs a handshake transfer for writing the word data in the page memory 16.

FIG. 28 shows a configuration example of the page memory write address generation circuit 14. In FIG. 28, when the rotation process is started, the base address of the page memory 16 stored in the register 18 is loaded into the 22-bit register 221 prior to the start of the process. In addition,
The base address of the page memory 16 is set by the CPU 17 and registered in the register 18 as an address at which the word data including the first pixel of the input image should be written.

The ALU 220 is controlled by a control signal output from the control circuit 20 in accordance with the rotation angle.
The operation of subtracting 1 from the input value (A-1), the operation of adding 1 to the A input value (A + 1), and the operation of the A input value to B
The operation of subtracting the input value (AB) and the operation of adding the A input value and the B input value (A + B) are performed and output to the register 221. The address stored in the register 221 is input, and the width of the page memory 16 in the main scanning direction, that is, the number of words NW is input from the register 18 to the B input. The number of words NW of the page memory 16 is written in the register 18 in advance by the CPU 17.

FIG. 29 is a diagram showing in what order the write addresses are generated by the page memory write address generation circuit 14.

In FIG. 29, when the write address is sequentially generated in the main scanning direction, the ALU 220 sets A + 1 to A + 1.
When the write address is sequentially generated in the main scanning direction in the opposite direction of the main scanning, the ALU is controlled.
220 is controlled to perform the operation of A-1, and when the write address is sequentially generated in the sub-scanning direction in the sub-scanning direction, the ALU 220 is controlled to perform the operation of A + B, and the write address is When sequentially generated in the sub-scanning direction in the reverse direction of the sub-scanning, the ALU 220 is controlled to perform the operation AB.

29A shows the generation order of the write address of the page memory 16 when the rotation angle is 0 °, and FIG. 29B shows the write address of the page memory 16 when the rotation angle is 180 °. Shows the order of occurrence,
FIG. 29C shows page memory 1 when the rotation angle is CW 90 °.
6D shows the generation order of the write address of No. 6, and FIG. 29D shows the generation order of the write address of the page memory 16 when the rotation angle is CW 270 °.

As a result of the above processing, an image rotated by a desired rotation angle or a mirror image is developed in the page memory 16.

[0098]

As is apparent from the above description, according to the present invention, the minimum random read / write cycle of the storage device used for the page memory and the buffer memory is the same as the cycle of the video clock of the input image. Since there is no need, it is possible to perform rotation or mirror image rotation processing using a storage device that operates at low speed.

Further, when a storage device having the same minimum Sandam read / write cycle is used, the processing can be performed at a higher speed than the conventional image processing apparatus.

Therefore, the calorific value of the device can be reduced, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a parallel conversion circuit 3.

FIG. 3 is a state transition diagram for explaining control of writing / reading of image data in a buffer memory.

FIG. 4 is a buffer memory write address generation circuit 16
It is a figure which shows the structural example of 0.

FIG. 5: Buffer memory write address generation circuit 16
It is a figure which shows the structural example of 2.

FIG. 6 is a buffer memory read address generation circuit 16
It is a figure which shows the structural example of FIG.

FIG. 7: Buffer memory read address generation circuit 16
It is a figure which shows the structural example of 6.

FIG. 8 is a buffer memory write address generation circuit 11
It is a figure which shows the structural example.

FIG. 9 is a buffer memory write address generation circuit 12
It is a figure which shows the structural example.

FIG. 10 is a diagram for explaining a generation order of write addresses generated by a buffer memory write address generation circuit when a mirror image is turned off.

FIG. 11 is a diagram for explaining a generation order of write addresses generated by a buffer memory write address generation circuit when a mirror image is turned on.

FIG. 12 is a diagram for explaining a generation order of read addresses generated by the buffer memory read address generation circuit when the rotation angles are 0 ° and 180 °.

FIG. 13 is a diagram for explaining the order of generation of read addresses generated by the buffer memory write address generation circuit for the buffer memory # A9 when the rotation angles are CW 90 ° and 270 °.

FIG. 14 is a diagram for explaining the order of generation of read addresses generated in the buffer memory # B10 by the buffer memory write address generation circuit when the rotation angles are CW 90 ° and 270 °.

FIG. 15 is a diagram showing a configuration example of a word synthesizing circuit 13.

16 is a diagram showing a configuration example of a register constituent element W0 of the register 170 of the word synthesizing circuit 13. FIG.

17 is a diagram showing a configuration example of a data set direction circuit of the word synthesizing circuit 13. FIG.

FIG. 18 is a diagram for explaining word composition of image data of odd lines when N = 1 and a rotation angle of 0 ° in the word composition circuit 13;

FIG. 19 is a diagram for explaining word combination of image data of even lines when N = 1 and a rotation angle of 0 ° in the word combination circuit 13.

FIG. 20 is a diagram for explaining word combination of image data of odd lines when N = 1 and a rotation angle of 180 ° in the word combination circuit 13.

FIG. 21 is a diagram for explaining word combination of image data of even lines when N = 1 and a rotation angle of 180 ° in the word combination circuit 13;

FIG. 22 is a diagram for explaining word composition of image data of even and odd lines when N = 2 and a rotation angle of 0 ° in the word composition circuit 13;

FIG. 23 is a diagram for explaining word composition of image data of even and odd lines when N = 2 and a rotation angle of 180 ° in the word composition circuit 13;

FIG. 24 is a diagram for explaining word composition of image data in the word composition circuit 13 when N = 1 and a rotation angle CW270 °.

FIG. 25 is a diagram for explaining word composition of image data in the word composition circuit 13 when N = 2 and a rotation angle CW270 °.

FIG. 26 is a diagram for explaining word composition of image data in the word composition circuit 13 when N = 1 and a rotation angle CW90 °.

FIG. 27 is a diagram for explaining word composition of image data in the word composition circuit 13 when N = 2 and a rotation angle CW90 °.

FIG. 28 is a diagram showing a configuration example of a page memory write address generation circuit.

FIG. 29 is a diagram for explaining the generation order of write addresses generated by the page memory write address generation circuit.

FIG. 30 shows a rotation angle and signals DEG # 0, # 1 and
It is a figure which shows correspondence between the mirror image designation | designated and signal MIRROR, and the information bit number N per pixel of an input image, and signal SELN.

[Explanation of symbols]

1 ... Image input device, 2 ... Image input interface, 3 ...
Parallel conversion circuits 4, 5, 6 ... Multiplexer 7,
8 ... Bidirectional buffer, 9 ... Buffer memory #A, 10 ...
Buffer memory #B, 11 ... Buffer memory write address generation circuit, 12 ... Buffer memory read address generation circuit, 13 ... Word synthesis circuit, 14 ... Page memory write address generation circuit, 15 ... Page memory interface, 16 ... Page memory, 17 ... CPU, 18 ... Register, 19 ... CPU interface, 20 ... Control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04N 1/387 // G09G 5/36 520 K 9471-5G 530 E 9471-5G

Claims (1)

[Claims] 1. An input image having a number of bits N per pixel is 9
In an image processing apparatus for outputting and storing in a page memory having a word width of W bits in a state of being rotated by an angle that is an integral multiple of 0 ° or being a mirror image, a specifying unit that specifies a rotation angle, an image size and ON / OFF of a mirror image, Primary storage means composed of a buffer memory having a word width of B bits for primary storage of image data of an image for at least W / N lines; input means for inputting input image data in parallel to the primary storage means for each B / N pixel; Depending on the number of bits N per pixel of the input image, the rotation angle designated by the designating means, the image size, and the mirror image on / off, the write address and the read address of the buffer memory of the primary storage means are set for each W / N line. From the control means for controlling and writing and reading the image data in a predetermined order, and the image data read by the control means The secondary storage means composed of at least B / N W-bit registers for synthesizing W-bit word data to be output to the page memory, and the register of the secondary storage means read by the control means. A synthesizing unit that sets the image data in a predetermined order according to the number N of bits per pixel of the input image and the rotation angle designated by the designating unit to synthesize W-bit word data, and the synthesized W bit Output control means for outputting the word data in a predetermined order, and the word data output by the output control means corresponding to the rotation angle designated by the designating means in a mode in which the input image is rotated by a rotation angle or is a mirror image. An image processing apparatus comprising: an address control unit that controls a write address of the page memory so that the address is stored in the page memory.