JPS6273864A - Data input and output memory - Google Patents

Abstract

PURPOSE:To attain excellent operation without complicated external control constitution and simultaneous and asynchronous data input/output by dividing an input data sent serially at each line into plural internal processing data bit lengths and reproducing a serial data by one line. CONSTITUTION:The data length of 1 video line is not required to be an integral number of multiple of the data length of shift register 3, buffer register 6 and can be changed at each line. The video data by one line inputted serially is split and stored in a memory array 1 in parallel, and at the read, the video data stored splittingly in the memory array 1 is read in parallel for plural number of times and outputted serially. Since the storage of the video data by one line is attained intermittently, the video data stored in the memory array 1 is read at the interruption of the storage. Thus, the storage area of the memory is split and the area corresponding to the data length is used and the utilizing efficiency of the memory is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to data input/output capable of simultaneously and asynchronously accessing input data and output data.

More specifically, the present invention relates to a data input/output memory capable of performing operations such as frequency conversion, timing synchronization, and delay of video signals.

[Prior art]

For example, video signals of laser beam printers and televisions that record images by scanning laser beams have a large number of data, l, i. A serial transmission method that transfers data is common.

For example, when transmitting data to a laser beam printer, the host computer on the sending side sends the video signal to the laser beam printer, and it uses a buffer for synchronization. It is necessary to have a memory and to transfer the video signal using a serial transmission method in accordance with the rotation of the rotating mirror of the laser beam φ printer. Such a buffer memory is also used for so-called scaling processing, in which the size of an image is changed by changing the frequency of a video signal.

Such buffer memory includes first in/first out memory (FIFO memory),
A static RA) I capable of high-speed operation is used.

The former type of memory has a simpler circuit configuration, but is faster and has been used since ancient times.
Since there is no t, it can only be used for synchronizing data of number 1 at most.The latter memory, on the other hand, is highly versatile for synchronizing and scaling, but it cannot be used as an address counter, There is a drawback that the peripheral circuit configuration for memory operation becomes complicated because a selector circuit and the like are required.

[[Object 1] The object of the present invention is to provide a data output memory with a new configuration that solves the disadvantages of the 4-memory memory, and also for high-speed data output. The purpose is to provide a data output memory that operates well without an external control configuration and allows data input/output in one cycle at the same time, and has a configuration suitable for one-chip integration. Its purpose is to provide output memory.

〔Example〕

A detailed explanation of the present invention will be given below based on the following embodiments.

FIG. 1 is a diagram showing an example of a block M configuration of a memory provided with the present invention.

Memory 7 rays contain multiple data bits
This is a memory that allows write operations.

The memory timing control block 2 is a block that controls all of the timing of read/write operations of the memory array 1, addresses of the memory array, etc.

The shift register 3 has a data length of 128 bits and is a register for converting a video input data signal DIN serially sent from a video data source, such as an image scanner, into a parallel signal. Data 0 is sent in parallel to buffer φ register 4, which is a buffer when writing to memory array 1.

Buffer register 4 has a capacity of 136 bits, and simultaneously stores 8-bit control data including line length data of the video signal sent from memory write control block 5, and stores 128 bits in memory array l. video of
3 inputs in parallel with the data signal.

The memory write control block 5 uses the write array address 0 of the memory array 1 and data regarding the line length to indicate the valid section of one line of the video input data signal DIN inputted from the video φ data source. It is generated based on the line section signal WDEt.

Buffer register 6 has a 136-bit capacity and is a buffer register used when reading memory array l. The data read out in parallel from the memory working array 1 is converted from parallel to serial data via the buffer register 6, of which the video data has a data length of 128 bits to generate the video output data t\DOUT. The control data is also sent to the memory read control block 8.

The memory read control block 8 converts the read of the memory array 1, the 7-ray address signal, and the line interval signal RDEt indicating the effective time between one line of the video output data signal ('jD OUT) into an eight-pass filter ψ. Based on the data regarding the line resistance inputted from the register 6, a line competition start signal from an image processing device such as a laser fist beam printer is generated manually by the RDS family.

The CLR1 signal is e.g.
Start of input of off-screen video φ data is entered manually at 111F and used to initialize the block (No. 1, WCK
Shinsou and RCK4I So are the lights generated from the video fist data exchange source and the image processing device, respectively, and the video fist data clock No. 1 at the time of REIT. Incidentally, in this embodiment, the zero character at the end of the name (-) indicates that it is an active low name (t). In this way, the serially input video e-data is converted into parallel data, stored in the memory array L, read out in parallel, and outputted serially, and the storage and readout operations are performed asynchronously in the 11 data arrays. Run fast.

2 to 4 are timing reference charts for explaining circuit operation.

Figure 2 shows a case where the data length of the l video line is 512 bits, the data length of shift registers 3 and 6 is 128 bits, and memory array 1 has a 136 x 8 bit configuration (the number of arrays is 8). is assumed. in this case,
Memory write control block 5 and eight φ register 4
The number of control data signal lines between the memory read control block 8 and the buffer register 6 is 7 bits (1
There are 8 bits in total: 28-bit count signal) and 1 bit (line continuation signal). Note that the data length of the l video φ line does not need to be an integral multiple of the data length of the shift register 3.6.

Also, the data length of l video line is 200°300°.
．． It may change for each line, such as 25 (J).

The timing chart in Figure 2 shows that after resetting the CLR signal path, the video clock WCK
A timing example is shown for application to frequency conversion, in which video data is written and, on the same page, a read operation is performed using a high-speed video clock RCK with respect to the video clock WCK at the time of writing. Further, Wo to W7°Ro-R7 in the figure indicate array addresses of the memory array 1 at the time of writing and reading, respectively. As is clear from Fig. 2, video data for l lives input serially is divided and stored in parallel in memory array l, and when read, it is divided and stored in memory array l. Video data is read out multiple times in parallel and output serially. Therefore, since video data for l lives is stored in memory array l intermittently, when the storage operation is interrupted, the video data stored in memory array l can be read out. As a result, video data is serially inputted and simultaneously video data is serially outputted at different frequencies.

Next, FIGS. 5 to 9, which show configurations for achieving the operations shown in the timing chart shown in the second figure, will be explained using timing charts.

FIG. 5 shows a specific example of the circuit configuration of the memory write control block 5.

Write-address-counter lO is memory array 1
This is a counter that counts the array address when writing the memory.
Since the number of arrays in array 1 is 8, a 3-bit counter is used. The write φ array address signal, which is the count output of the write address counter 10, is sent to the memory timing control block 2 as shown in FIG. 7, and is used as a write address for write data.

The write address counter IO is a synchronous-up fist counter in this embodiment, and the write address counter IO is a synchronous-up fist counter, and CL R
” The write array contention address status is cleared to the value O by the signal 'i', and when the enable terminal E is 1, the write number clock WCK is input and the count is increased.

The write bit contention counter is WDEt
- By counting WCK Shinkin t Shinkin 3 during the output period, write address - Counter IO enable signal -
A counter for generating the E and write bit count signals. In this embodiment, since the data length of shift register 3.7 is 128 bits, a 7-bit synchronous up counter is used. Count (1 write contention bit count signal is CLRl
.

When the WRQ family (j is reset to i10 and all bits become (+61), the ripple-carry output R
C becomes 1. This carry output RC of 1 is the enable signal E of the write conflict array counter IO and the flip-
It is used as the flop 14 manpower. Also, as shown in FIG. 8, the write bit φ count signal is
Via Jista 4.

It is stored in memory array l along with the video data. As a result, the length of the video fist data stored in each memory array is stored in association with the video fist data as a lead meeting bit φ count signal.

D-type flip-flop 12 and AND gate 13
is a circuit for detecting the rear end of the WDE main signal,
A WEND signal V) as shown in the timing chart of FIG. 3 is generated. The WEND signal - is logically summed by the OR gate 16 and used as a signal for inputting video data for one life, and is input to the enable signal E of the write array counter 10 and the flip-flop 14. In addition, the WDE is activated for l clocks by the WCK signal.
The MWDE signal delayed from the t signal is stored in the memory array l via the buffer register 4 as shown in FIG. The MWDE low signal is a line continuation signal and is used for video signal line reproduction during read operation, that is, RDE
It is used for 11) live end r determination of the l line when reproducing the t signal.

The output WRQ4X of the D-type flip-70 tube 14 is the data write signal No. 1 to the buffer contention register 4 as shown in FIG. 8, and the write request signal to the memory timing control block 2 as shown in FIG. used as.

FIG. 6 shows a specific example of the circuit configuration of the memory read control block 8.

Read e-address counter 20 is memory array 1
This is a synchronous counter that counts the array e address at the time of reading. Similar to the write address number counter 10, it is a synchronous counter that outputs a 3-bit linear φ array conflict address signal to the memory φ timing control 2 as shown in FIG. −
It is a 7pφ counter. The read/7F reply counter 20 is cleared to the value O by the CLR1 signal -5-, and is counted up by inputting the read clock RCK when the enable terminal fE is 1.

The read bit number counter 21 is a 7-bit synchronous town counter for counting the enable signal E of the read and address counter 20 and the bit length for generating the RDE customer response. The read bit counter 21 receives video data from the memory array 1.
Leading with data. RCK clock for loading the read bit count signal (= write bit count signal - indicating the bit length of the read video data) by the RLD signal and serially outputting the video data from the shift register 7. A countdown is performed for each input, and when the count value reaches 0, the ripple carry signal RRC becomes 1. Therefore, when the RRC signal becomes 1, serial output of video and data from the shift register 7 ends.

D-type working flip-flop22. AND gate 23
, JK type clip flop 24 is an MRD read with video data from memory array l.
E Ienobu''f (=signal M W D E) and RLD
This is a circuit for generating an RDE zero signal using signal 1). That is, the flip-flop 24 is set by the RL, D signal 5'f due to the input of the RDSt signal t;-, thereby causing the RDEX signal to go low. After that, MRDE! in the data read from memory array l! After the serial output from the shift register 7 of the video fist data whose signal - is l is completed, the RRC signal causes a flip.
Flop 24 is reset. In this way, the serial output from the shift register 7 of the video data with the MRDEt signal of 1 is completed from the input of the video data output light (for example, the RDSt signal from the laser beam 1, printer). Up to r, RDE low trust can be formed. Therefore.

RDE's original report on manually generated l-line data L() fζ
) can be formed according to the clock frequency for data read.

D type fritz 7'-flop 29, NOR gate 3
0 is RD as shown in the timing chart in Figure 4.
Signal for lead start, RT O
This is a circuit for generating P (4-;).

SR flip-flop25. D type frillus flop 26. The AND gate 27 sets the first data from the memory array l in the buffer register 4 by the first WRQ input after the input of the CLRt signal.
This is a circuit for generating 4j 8'j. This FR
The RQ signal becomes the RRQ signal via the OR gate 28.

After this circuit operates, a request to read the data set of the buffer register 4 is made by RT OP c-: sy and an RRC signal. That is, OR gate 28
The output RHQ signal t) makes a data set request to the memory timing control block 2, which in turn sends a data set request to the memory timing control block 2 via the RDLD signal 5.
) is output. In addition, the FRRQ signal is.

When the RDSt signal is input for the first time, in order to make the serial output of video data 4.1 ft, it is necessary to store the video data to be output first in the buffer register 6. used.

FIG. 7 is a diagram illustrating the exchange of signal lines in the memory timing control block 2.

Memory timing system
The array at 1/s signal, WR signal, and RD signal are output to control the data rate and write operation n.

W RQ <If the signal is accepted, the write-7 ray from the write cloud address ψ counter lO shown in FIG.
When a write operation is performed using the address signal (-) and the RRQ signal is accepted, the read operation is performed using the read array address signal from the read contest address e counter 20 shown in FIG. Also, when reading data, it outputs a data latch (No. 11) RD LD signal to the buffer register 6.

Note that when WRQ signal and RRQ signal occur simultaneously, priority 1111 fQ is attached to the signal so that either read or write operation can be received by +1.

FIG. 8 shows shift register 3. buffer register 4
FIG. 3 is a diagram showing peripheral signal-line exchanges.

The video input data signal DIN is the clock WCK signal -
19 is written into the shift register 3 serially. WDE! The signal is used as a false Irf signal for the shift operation.

Buffer register 4 is a D-type flip-flop, and latches parallel data from shift register 3 in response to the WRQ signal, which becomes write data to memory array 1.

FIG. 9 is a diagram showing the exchange of signal lines around the buffer register 6 and shift register 7.

Contrary to FIG. 8, parallel read data from the memory array I is latched into the buffer register 6, which is a D-type flip-flop, by the RDLD signal. The latched data is sent to the memory read control 1 block 8 and shift 1/distaff, respectively.

The RLD signal is used as a data load signal t;- to the shift register 7.

Below 1. As shown in FIG. Outputs as serial video data for 1 life, saving memory space.
Storing and embedding video data into array I is performed quickly.

In addition, storage and reading to and from memory 7 rays is carried out by equity 11.
, 1, so that reads can be performed between stores to the memory array, thereby making the serial output of the video-data or IF simultaneously with the serial video data input.

In addition, the storage operation and readout operation of the video number data of memory number 7 Ray 1 are created by WCK and RCK, respectively, and they are independently controlled, so the storage operation and readout operation are This can be done during the J1 period.

In this embodiment, the memory configuration is such that the input f-tater and the output data are each 1 bit, but the shift register 3,
Buffer register 4, memory array 1, buffer φ
By increasing the register 6 and the shift register 7 by a certain number of pins, it becomes possible to convert into other bits.

Furthermore, the data to be processed is not limited to video data, but may also be serial data output from a word processor, computer, etc., for example.

It can be used as a human output buffer for various data.

Also, as you can see from the timing chart in Figure 2, the read-write interval to memory array L becomes longer, so slow memory 7-ray is used for serial input/output of high-speed video data. It is ready for use.

In addition, even when dynamic memory is used as memory array 1, there is a margin in timing, so it has a built-in self-refresh mechanism and pseudo-metallic RA.
M operation is easily realized of(E).

Furthermore, -) the line length of the inserted data can be reproduced simply by inputting the timing signal of the read register 1, eliminating the need for a line length counter at the time of readout, which was required in the past. It becomes possible to simplify the circuit configuration of applied equipment.

Furthermore, for the same reason, it becomes possible to deal with signals having different data lengths on the line If.

〔effect〕

As explained above, according to the present invention, serially sent input data is divided into multiple internal processing data bit lengths and read and write control is performed, so one line of data can be used for data input and output. It does not require memory that can process all the data, and it can process even if the data length of one line is uneven, and the memory storage area is divided and only the amount used according to the data length is used. This improves memory usage efficiency.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a block configuration of a memory according to the present invention, and FIGS. 2 to 4 are timing number charts for explaining circuit operation. 5 is an explanatory diagram showing an example of the configuration of the memory write control block 5 in FIG. 1, FIG. 6 is an explanatory diagram showing an example of the configuration of the memory read control block 8 in FIG. 1, and FIG. Memory timing control block 2 in Figure 1
8 is a diagram showing an example of the structure around the shift register and buffer register 4 in FIG. 1, and FIG. 9 is a diagram showing an example of the structure around the shift register and buffer register 4 in FIG. FIG. 3 is a diagram showing an example of a peripheral configuration. In the figure, 1 is a memory read control block, 2 is a memory timing control block, 3 and 7 are shift registers, 4 and 6 are buffer write registers, 5 is a memory write control block, and 8 is a memory read control block.

Claims (1)

[Claims] Input data sent serially for each line is divided into multiple internal processing data bit lengths and stored in parallel.
A data input/output memory characterized in that data stored in multiple pieces is read out in parallel and one line of input serial data is reproduced.