JPH03141099A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the increase of input/output pins by setting successively an initial value of an address to an address generating means at every bit group through a bidirectional bus means, and executing successively an access to an access address from this initial address. CONSTITUTION:A superordinate address is set to a data bus 3, and also, a load pulse 4 is generated. Accordingly, this superordinate address is stored in an address register 30 through a bidirectional driver 20. Subsequently, a subordinate address is set to the bus 3, and also, a load pulse 5 is generated and stored in an address register 40 through the driver 20. Thereafter, write data is set to the bus 3 and a write strobe 2 is generated, and the write data is written in an address shown by the registers 30, 40 of a RAM 10 through the driver 20. Subsequently, when an increment pulse 6 is inputted, the contents of the register 40 are brought to increment, and the write data corresponding to the next address increased by 1 from an initial address is written. When a carry 7 is generated from the register, a write access can be executed succes sively and continuously.

Description

TECHNICAL FIELD The present invention relates to memory integrated circuits, and more particularly to sequentially accessible memory integrated circuits.

Prior Art Writable/readable random access memory (RAM)
), the data bus and address bus are
Although data buses are independent on a one-to-one basis, address buses are not independent on a one-to-one basis, and address data is divided into multiple times and sent to the address bus. There are some structures.

Such conventional RAM has the disadvantage that as the storage capacity increases, the number of I10 bins for address signals increases, and the number of input/output pins of the memory integrated circuit increases.

OBJECT OF THE INVENTION Therefore, the present invention has been made to eliminate the drawbacks of the conventional ones, and its purpose is to provide a memory integrated circuit in which the number of input/output bins does not increase even when the storage capacity increases. Our goal is to provide the following.

Structure of the Invention According to the present invention, there is provided a random access memory means for storing information, a bidirectional bus means connected to the memory means for exchanging data with the outside, and an address divided into a plurality of bit groups. address generating means which is set for each group and whose contents can be sequentially incremented; and in response to a continuous access instruction to the memory means, an initial value of the address at the time of continuous access is generated by the bidirectional bus means. There is obtained a memory integrated circuit characterized in that each bit group is sequentially set in the address generating means via the bit group, and access is performed while sequentially incrementing the access address from this initial address.

Example The present invention will be described in detail below with reference to the drawings.

The figure is a block diagram of an embodiment of the invention. The memory integrated circuit 100 is a RAM l0 in which data can be written/read.
A bidirectional driver 20 is connected to this RAM and exchanges data with the outside via the data bus 3. Each group of upper and lower bits of the address input via the bidirectional driver 20 is processed by a load pulse 4. and address registers 30 and 40, which can be freely set in response to the address registers 30 and 5.

The address register 40 corresponding to the lower bit group is configured to sequentially increment the set initial address every time the increment pulse 6 is generated, and the address register 3o corresponding to the upper bit group is incremented by the generation of a carrier. ing.

The RAM 10 becomes readable with read strobe 1 and writable with write strobe 2.

The operation of the memory integrated circuit 100 having such a configuration is as follows. An upper address is set on the data bus 3, and a load pulse 4 is generated. Therefore, this upper address is stored as an initial value in the address register 3o via the bidirectional driver 20.

Next, a lower address is set on the data bus 3, and a load pulse 5 is generated. Therefore, this lower address is stored in the address register 40 as an initial value via the bidirectional driver 20.

After that, write data is set on data bus 3 and write strobe 2 is generated. As a result, write data is written via the bidirectional driver 20 to the address indicated by the address registers 30 and 40 in the RAM 10. Subsequently, when an increment pulse 6 is input manually, the content of the address register 40 of the lower address bit is incremented, and write data corresponding to the next address increased by 1 from the initial address is written.

When the signal 7 is generated from the address register 40, the address register 30 of the upper address bit/soto is incremented, so that sequential write access becomes possible.

In the case of continuous read access, if the read strobe 1 is generated and the increment pulse 6 is generated sequentially, the contents of the RAM 10 are read out continuously, and the data bus 3 is accessed via the bidirectional driver 20. This makes it possible to output to.

Although the above embodiment shows the case where the access address is divided into two bit groups, upper and lower, the access address is not limited to this, and it is divided into multiple groups according to the bit width of the data bus, and the corresponding It is sufficient to provide an address register.

Effects of the Invention As described above, according to the present invention, the memory integrated circuit is
Sequential writing to M disks, electronic disks, etc./
When used as a read function, it has the advantage that the integrated circuit's output bins do not increase even if the storage capacity increases.

[Brief explanation of the drawing]

The figure is a circuit diagram of an embodiment of the present invention. Explanation of symbols of main parts 10...RAM 30° 2 0...Bidirectional driver 0...Address register

Claims (1)

[Claims] (1) Random access memory means for storing information, bidirectional bus means connected to this memory means for exchanging data with the outside, and addresses divided into a plurality of bit groups are set for each bit group. Both of them include address generating means whose contents can be sequentially incremented, and in response to a continuous access instruction to the memory means, the initial value of the address at the time of continuous access is generated for each of the bit groups via the bidirectional bus means. The memory integrated circuit is characterized in that the addresses are sequentially set in the address generating means, and the access address is sequentially incremented from the initial address and accessed.