JPS6228995A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To attain the control of a memory IC of large capacity without increasing the number of the signal lines of the IC by connecting an output control signal to an address signal line not in use within the memory IC in the inputting of a column address. CONSTITUTION:Row address signals R0-R7 are inputted from address signal lines A0-A7 at the trailing edge of a clock phi1, and column address signals C0-C5 are inputted from the lines A0-A5 at the trailing edge of phi2. On the other hand, a line A7 is ignored as the address signal after the inputting of the signal R7. At such a time, an output control signal line phi4 is connected to the line A7 within a memory IC11 and after the inputting of the signal R7, it is used as the output control signal. Normally, read out information appear at data signal lines DATA0-3 after a prescribed time elapse of the inputting of the phi2. At such a case, eight bits signal switching circuit switches R0-R7 to C0-C5, sending them on the lines A0-A7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory integrated circuit (IC) among semiconductor memories having bidirectional data signal lines.

[Conventional technology]

Currently, semiconductor memory ICs, especially dynamic MOS memory IJs, are used as memory elements in information processing devices.
ICs are common, but as memory ICs have become more highly integrated and their applications have diversified, memory ICs with multiple data bit configurations have come to be used in addition to the conventional one data bit configuration. Ta. Memo IJ with this multiple data bit configuration
In Ic, in order to prevent an increase in the number of input/output signal lines, the data signal is normally a bidirectional signal for both input and output.

As this memory IC, an example of a memory having a structure of 16 words x 4 bits is spread out as shown in the waveform diagram of FIG. In the figure,
φ1. φ2 are two clock signals generally called RAS (row address) signal and CAS (column address) signal, respectively, and the contents of the address signal line Ao%A are taken in at the falling edge of the first clock signal φl. ,
This is the address signal R11-R called the row address.
, and when the second clock signal φ2 falls, an address signal Co-C, also called a column address, is generated.
These 14-bit address signals address 16 words.

On the other hand, there are two methods for writing data into this type of memory: an early write method and a delayed write method.

This will be explained using 82 types of timing diagrams.

Generally, early write means that the second clock signal φ2
Write clock φ3 and data signal 1jlD at the falling edge of
S-included information wD on ATAo-DATA3.

~3 is confirmed. In this case, the clock signal φ1 before starting the 1 operation. In the case where φ2 is not input, the data signal lines 11A'rAO to DATA
Since the circuit inside the memory IC is configured so that 3 is in the input state, the data signal 19 I) A
, TAO-DATA3 may require a signal to determine the input or output.

On the other hand, when the delayed drive is applied, the clock signal φ1゜φ2
Since the write clock signal is input after a certain period of time has elapsed after the clock signal φS is input, it cannot be distinguished from the read cycle until the clock signal φS changes to the input ζ. Therefore, in distinction from the read cycle, the data signal lines DATAO~3 are brought into the input state, and the write information W is inputted prior to the input of the write clock signal φ1.
A data output control signal φ1 is required to input DO to WD3. Particularly, in a delayed read, when information at a certain address is read and then rewritten within the same memory cycle, it cannot be executed without the data output control signal -4. This is shown in waveform group B in the figure. RDO-RD3 is read data,
During this read, the data signal lines DATAO~3 are in the output state,
WDO to WD3 are write data, and the signal line DATA
It is in the input state of 0 to 3 digits.

[Problem that the invention seeks to solve]

In the above-described conventional memory IC, the output control signal φ4 is required only for the delayed drive cycle. That is, there is a drawback that a dedicated signal line (φ4) is required even though that state (φ4) is unnecessary in other cases.

An object of the present invention is to eliminate these drawbacks and provide a memory IC that does not require a signal line dedicated to output control signals and can control a large capacity memory without increasing the number of signal lines.

[Means for solving problems]

The configuration of the present invention is that address signals are inputted in a time-division manner into row and column addresses using two clock signals, and write information and read information are bidirectionally input and output through the same data signal line. In a memory integrated circuit, a data output control signal determines input/output of the data signal line.

It is specially ordered that the address signal be inputted from the unused address signal line at the second input of the time-division input of the address signal.

C Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart during delayed riding of this embodiment. In the figure, 11 digits are memo QIC of the embodiment.

This is a 12-digit 8-bit signal switching circuit. First, when the first clock signal φl falls, the address signal line A O-A
A row address signal 'Fto-JL' is input from t,
Next, at the fall of the second clock signal φ2, a column address signal Co%C5 is inputted from the address signal lines A, .about.A5.

On the other hand, the address signal hAr is ignored as an address signal after the row address signal R7 is input. However, the output control signal line φ4 is connected to the memory IC11.
Signal inside &! Since it is tangential to A7, after the address signal R7 is input, it can be used as an output control signal. Usually, the setup information RDO-RD3ti
Since the clock signal φ2 does not appear on the data signal lines DATAO~3 until a certain period of time has passed after being input, the clock signal φ2
No matter what state the output control signal is in before 2 is input, it does not affect the performance of the memory ICII. Furthermore, since the output control signal is ignored during early writing, the state of the signal i k A r is irrelevant to the operation.

The memory ICI 1 of this embodiment is not provided with a signal line dedicated to output control signals, and an 8-bit signal switching circuit 12 switches between row addresses R, ~R7 and column addresses Co%C. In time division, Izuwa connects one side to the signal line A of the memory IC11.

~A, output above. Here, the clock signal φ which has conventionally been used to control the output of the memory IC is input to the address signal line A instead of being directly input to the memory ICI 1.
It is connected to the conventionally unused input of the signal switching circuit 12 on the column address side corresponding to No. 7. Therefore, there is no need to add any special external circuit.

〔Effect of the invention〕

As discussed above, the present invention eliminates the need for a dedicated signal line for the output control signal by connecting the output control signal to the address signal line that is not used when inputting a column address inside the memory IC, and also eliminates the need for a signal line dedicated to the output control signal, and By adding special circuits, it is possible to realize a memory IC with the same functions and performance as conventional ones.In particular, by using the input line, which was conventionally used as an output control signal line, as an address signal line, the IC can be improved. It is possible to control a larger capacity memory IJIC without increasing the number of signal lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention when using a memory, FIG. 2 is a timing diagram explaining this embodiment, and FIG. 3 is a timing diagram explaining the operation of a conventional memo IJTc when using it. be. 11...Memo IJIc, 12...Signal switching circuit, Ao%A,...Address signal line b
co-c, ・・・・・・Column address signal, Ro~R
7...Row address signal, φl, φ2...
...Clock signal, φ3...Write clock signal, φ4...Data output control signal. Agent Patent Attorney Susumu Uchihara □t go R7 (a~G 3rd class)

Claims (1)

[Claims] In a memory integrated circuit, an address signal is time-divisionally inputted into row and column addresses using two clock signals, and write information and read information are bidirectionally input and output through the same data signal line. A memory integration characterized in that a data output control signal that determines the input/output of the data signal line is input from any address signal line that is not used during the second input of the time-division input of the address signal. circuit.