JPH01125647A - Priority processing circuit - Google Patents

Abstract

PURPOSE:To prevent the influence of an external interface fault to an internal bus by giving priority right to the internal bus when the external interface is hanged while the priority right is held by the external interface. CONSTITUTION:A priority processing circuit 4' transmits a write selecting signal WSL and a write responding signal WACK based on the write signal WT received from an external interface 1. At the same time, the circuit 4' outputs a read selection signal RSL, a read selection signal RSL and a read answer signal RACK based on the read signal RD received from an internal bus 2. When the interface 1 is hanged with the signal WT kept turned on, the signal WSL is turned off with the signal RSL received from the bus 2 and turned on. Thus the priority is given to the reading actions carried out at the side of the bus 2. Thus it is possible to prevent the influence the fault of the interface 1 to the bus 2 and to improve the reliability of a processor.

Description

[Detailed Description of the Invention] [Summary] Regarding a priority processing circuit that controls writing and reading of data to and from an input buffer interposed between an external interface and an internal bus, the external interface The purpose of this is to provide a priority processing circuit that transfers priority to the internal bus in the event of a hang, and enables read operations from the internal bus. A priority processing circuit that controls reading and writing of data to the buffer 1, and outputs a write selection signal and a write response signal based on a write signal from the external interface side, and also outputs a write selection signal and a write response signal based on the write signal from the external interface side, and also outputs a write selection signal and a write response signal based on the write signal from the external interface side. A read selection signal and a read response signal are output based on the signal, and when the external interface hangs and the write signal remains on, the write selection signal is turned off and the read response signal on the internal bus side is output. The configuration is such that the selection signal is turned on to give priority to the read operation on the internal bus side.

[Field of Industrial Application] The present invention relates to a priority processing circuit that controls writing and reading of data to and from an input buffer interposed between an external interface and an internal bus.

The channel circuit interposed between the external interface and the internal bus has an input buffer, and when data is written to the input buffer, it generates an interrupt and writes the data in the input buffer. I am trying to read it to the internal bus. However, input buffer? If the write timing and the read timing overlap, data cannot be guaranteed, so a priority processing circuit is required to prioritize one of the two.

[Prior Art] As a conventional priority processing circuit of this type, there is one shown in FIG. 4, for example.

In FIG. 4, 1 is an external interface, 2 is an internal bus, 3 is a channel circuit interposed between the external interface 1 and the internal bus 2, and the channel circuit 3 is an input buffer 5 and a priority processing It has a circuit 4.

When the write (WT> signal is output from the external interface 1 to the priority processing circuit 4, the priority processing circuit 4 outputs the write (WT> signal) to the input buffer 5,
Data is written into the input buffer 75 from the external interface 1. Next, when the read RD> signal is output from the internal bus 2 to the priority processing circuit 4, the priority processing circuit 4 outputs the read RD) signal to the input buffer 5. The data written in the internal bus 2 is read out into the internal bus 2. Note that when the WT double signal and the RD double signal are generated simultaneously, the W double signal has priority.

[Problems to be Solved by the Invention] However, in such a conventional priority processing circuit, the WT times the signal is output from the external interface, and the W
If the external interface hangs while acquiring the T signal priority, the WT signal remains on and 1.
Even if the RD-multiplied signal is output from the internal bus side, priority cannot be taken, and there is a problem in that a failure in the external interface spreads to the internal bus side.

The present invention has been made in view of such conventional problems.If the external interface hangs while the external interface is acquiring priority, the priority is passed to the internal bus and the internal bus is transferred to the internal bus. The object of the present invention is to provide a priority processing circuit that enables read operations from.

[Means for solving problems] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 is an external interface, 2 is an internal bus, and 5 is a buffer interposed between the external interface 1 and the internal bus 2.

4' is the write from the external interface 1 (WT
> outputs a write selection (WSL) signal and a write response (WACK) signal based on a read selection (R8L) signal and a read response (RACK) signal based on a read (RD) signal from the internal bus 2. When the external interface 1 hangs and the write (WT) signal remains on, the write selection (WSL> signal is turned off and the read selection <R3L> from the internal bus 2 is output. ) signal is turned on to give priority to the read operation on the internal bus side.

[Operation] In the present invention, while the external interface 1 is acquiring priority, the external interface 1 hangs and writes (
When the WT> signal remains on, priority is given to the RD> signal read from the internal bus 2 to enable read operation from the internal bus side.

Therefore, a failure in the external interface 1 can be prevented from spreading to the internal bus 2, and the reliability of the device can be improved.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a circuit block diagram of a priority processing circuit showing one embodiment of the present invention.

First, to explain the configuration, in FIG. 2, 11 is a register (first buffer) that outputs the RD and O signals after one clock when the read (RD) signal is input, and 12 is the register (first buffer) for reading the R
DO signal and write selection (WSL> signal, which will be described later)
a first AND circuit, 14, which receives input via the knot circuit 13;
is a register (second buffer) that outputs an RDI signal one clock period when the output of the first AND circuit 12 is input;
15 is before.

When the RD1 signal is input, a read response (
RAC> register that outputs the signal (third buffer),
16, by inputting the RAC signal and the RD multiplied signal,
This is a second AND circuit that outputs a read response (RACK) signal.

On the other hand, 17 is a register (fourth buffer) that outputs the WTO signal after one clock when the write (WT> signal is input).
, 18 is a third AND circuit which outputs a read selection (R3L> signal) by inputting the RDO signal and the RD1 signal; 19 is a third AND circuit to which the output of the first AND circuit 12 is input via the second NOT circuit 2OA; This is a fourth AND circuit to which the R8L signal is input via the third NOT circuit 20B, and the WTO signal is further input.

21 is a register (fifth buffer) that outputs the WT1 signal one clock after the output of the fourth AND circuit 19 is input.
, 22 is a WTI signal and a flip-flop (JK
By inputting the inverted output of flip 70 (23), the R
A fifth AND circuit outputs the 3L signal, 24 is a register (sixth buffer 7) that outputs the WT2T2 signal one clock period when the R3L signal is input, and 25 generates a write pulse by inputting the inverted output of the WT2T2 signal K flip-flop 23. (The sixth AND circuit 23 outputs the WTP> signal, to which the WTP signal is input and the fourth AND circuit 23 outputs the WTP> signal.
A write response (WAC>
A JK flip-flop 27 which outputs a signal and its inverted signal is a seventh AND circuit which outputs a write response (WACK> signal) by inputting the WAC signal and the WT multiplied signal.

Next, the operation will be explained based on the time chart shown in FIG.

First, as shown by ■ in FIG. 3, the operation mode of the buffer 5 will be described when the RD multiplied signal is output from the internal bus side, but the WT multiplied signal is not outputted from the external interface side.

RD double signal from internal bus 2 followed by first buffer 11
The RDO signal is output from the second buffer 14, followed by the RD1 signal from the second buffer 14, and roughly at the same time as the RD1 signal is output, the R3L signal is output from the third AND circuit 18. Furthermore, the RAC signal is output from the third buffer 15 following the RD1 signal, and the RACK signal is output from the second AND circuit 16 almost simultaneously with the RAC signal.

When the RDO signal goes to the "0" level, the R3L signal also goes to the rOJ level. Therefore, the buffer 5 is in the read mode during the output period of the R3L signal.

Next, as shown by ■ to ■ in FIG. The operation mode of the buffer 5 when outputting is explained.

In (3), the WT multiplied signal from the external interface 1 is followed by the WTO signal from the fourth buffer 17,
Following this, the fifth buffer 21 outputs the WT1 signal, and the sixth buffer 24 outputs the WT2T2 signal. Furthermore, the WSL signal is output from the fifth AND circuit 22 almost simultaneously with the WTI signal. This puts the buffer 5 in write mode. Here, when the WAC signal is output from the JK flip-flop 23 in response to the WT2T2 signal, the inverted output of the JK flip-flop 23 is input to the fifth AND circuit 22 and the sixth AND circuit 25, respectively, so the WSL signal becomes "1". ” and the WTP signal changes from the “1” level to the “O” level, and the WTP signal also changes from the “1” level to the rOJ level. This ends the write mode of the buffer 5. - On the other hand, in ■, the WSL signal is input to the first AND circuit 12 via the first NOT circuit 13, so R
The DI signal goes from the rOJ level to the “1” level, and the third
The AND circuit 18 outputs the R3L signal at the "1" level. Buffer 5 therefore changes to read mode. That is, priority is given to the internal bus side.

When the output of the RD1 signal changes from the "1" level to the "0" level, the R8L signal output from the third AND circuit 18 changes from the "1" level to the "0" level, and the read mode of the buffer 5 ends. Then, at ■, the WT low signal is followed by the WTO signal, the WTO signal is followed by the WTI signal, and the WSL signal is output almost simultaneously with the WT1 signal, the buffer 5 enters the write mode, and on the other hand, Due to the output of the WAC signal, the WSL signal becomes “
When the level changes from "1" level to "0" level, the write mode of the buffer 5 ends.

Next, as shown in ■ and ■ in Figure 3, the RD low signal W
The operation mode of the buffer 5 when the T low signal is output at the same time will be explained.

In (2), when the RD low signal is followed by the RDO signal and the R5L signal is output at the same time as the RD1 signal, the buffer 5 enters the read mode, while the RDO signal becomes "O" level and the R3L signal becomes "0". ” level, the read mode of the buffer 5 ends. On the other hand, in (2), while the R3L signal is at the "1" level, the output of the fourth AND circuit 19 is at the "0" level, and the WT1 signal output from the fifth buffer 21 is at the "0" level. When the R3L signal goes to “0” level, the WT1 signal goes to “0” level.
1 level, and the WSL signal also became "1" level,
Buffer 5 is placed in write mode. “1” of WAC signal
The WSL signal changes from "1" level to "0" level by outputting the level.
” level, the write mode of the buffer 5 ends.

As mentioned above, external interface 1 hangs and W
If the T low signal remains on, the RD low signal from internal bus 2 can be given priority and the buffer 5 can be changed from write mode to read mode. As a result, a failure in the external interface 1 can be prevented from spreading to the internal bus 2, and the reliability of the device can be improved.

[Effects of the Invention] As explained above, according to the present invention, even if the external interface hangs and the interrupt signal/signal remains on, priority is given to the read signal from the internal bus side. The buffer can be placed in read mode, so
It is possible to prevent an external interface failure from spreading to the internal bus, and improve the reliability of the device.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is a circuit block diagram showing an embodiment of the present invention, Fig. 3 is a time chart for explaining the operation, and Fig. 4 is a circuit block diagram showing a conventional example. It is a diagram. In the figure, 1...external interface, 2...internal bus, 4'...priority processing circuit, 5...buffer.

Claims (1)

[Claims] A priority processing circuit (4) that controls reading and writing of data to a buffer (5) interposed between an external interface (1) and an internal bus (2), which A write selection signal and a write response signal are output based on the write signal, and a read selection signal and a read response signal are output based on the read signal from the internal bus side. When the write signal remains on, the write selection signal is turned off and the read selection signal on the internal bus side is turned on to give priority to the read operation on the internal bus side. processing circuit.