JPS5975494A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the manufacturing cost and to improve the memory function, by providing a mode execution circuit and setting selectively the mode to form the memory having plural read/write modes with the same mask pattern. CONSTITUTION:A cell array 1 where plural memory cells are arranged in matrix is provided, a desired data is read out sequentially from the array 1 based on an address signal applied externally so as to write data in the array 1. In this case, mode executing circuits 8-11 execute plural different read/write systems. A mode selecting set circuit 8 transmits a signal selecting and executing one of the read/write systems.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and the present invention provides a plurality of different modes of convolution method. In preparation, among the various modes, the operating mode τ is quickly selected, and as shown in the setting δn, it is related to the semiconductor storage device Ji.

In recent years, address multiplexing methods have been adopted in large capacity memories such as 64-pin dynamic RAM (random access memory) in order to reduce the number of required bins. Of course, if this address multiplex method is adopted, the address signal is supplied twice, and the access time becomes correspondingly longer. Therefore, here
'1M erase and high speed read 1. f! Various types of writing modes, such as page mode, nibble mode, and byte mode, have been proposed as methods to enable # writing.
What these modes have in common is that when the first row address signal and clear address signal are taken in, the -1 column address signal alone is supplied or the column address strobe signal is toggled, resulting in continuous operation. Read the data of the fushu focus,
The point is that VC is being used with a lot of intimidation. Kon
As a result, at least the time required to supply the row address signal becomes less secure, and the overall access time is shortened.

In recent years, it has become common to apply all of these various read/write modes to large-capacity memories such as 256 bits or 1 mechanical hint.

However, in the conventionally proposed methods, each mode was commercialized separately.

Therefore, firstly, the present invention makes it possible to configure a 4-cow storage device with various bladder write modes such as normal random access mode, page mode, nibble mode, and byte mode using the same mask pattern. The purpose of the pond of the present invention is to
2. Based on the mode selection controller number, one of the above various modes is selected and the read and write operations are performed according to the selected mode. It is about providing.

A further object of the present invention is to provide a semiconductor memory device which is capable of taking in mode selection braking signals from address bins in a time-division manner and selecting any mode.

The purpose of the further oil of the present invention will become clearer in the following description of real 1M chestnut.

This invention will be explained below using the drawings.

FIG. 1 shows a schematic configuration of a dynamic RAM in which δn is used to select a mode by incorporating a control signal for mode selection from an address bin as 181. show. In the same figure,
Each block surrounded by a one-dot chain line 1 is formed on one semiconductor substrate, for example, a silicon substrate, using well-known semiconductor integrated circuit technology.

In FIG. 1, it is a memory cell array in which memory cells with a focus of 1i64 are arranged in an L matrix of 256×256 bits.脣に匍】limit δn
However, in the non-implemented case, the sense amplifier is in this memory cell array.

2a, 2bH Address buffer circuits 2a, 2bicH1 Addresses of X thread 1d AX0 to AX7 supplied in two parts from a micro processor sensor (hereinafter referred to as CPU), etc. not shown.
and Y thread address 1 west issue A y o ~ A y? are inputted n times.

3 a, a bU upper Md address buffer circuit 2a
.

2b output signal ax1+ azl (L”0~?) and a
yt' (1=0 to 7), the address signal Axt''Ayt(i=Q
These are an X decoder and an X decoder for selecting - memory cells corresponding to 7).

Note that aX□, a x 1, ay□, and fan pulse 7nzon are mutually complementary signals.

4 is a timing generation circuit, and this timing generation circuit 4
Ha, C! Based on the address strobe signal (hereinafter referred to as RAS signal) and column address strobe signal (hereinafter referred to as OA 81M) supplied from the PU, etc.
The control signal φ which combines the operation of the above-mentioned Abi 22 fufufu circuits 2a, 2b and X, X decoders 3a, 3bi 8. φ81. φ7
＋ 'φa3. φdi ' 1st signal φd2 which disables the operation of the mode selection circuit described below, and 1g signal φ which controls the read/write control circuit. 1st and 2nd class will occur.

5, the main amplifier transmits and latches the data output from the memory cell array.

Further, although not particularly limited, the main amplifier 5 includes a switch circuit 1 that is controlled by the output signal of the X decoder 3b and the output signal of a shift register, which will be described later. Y-tecoder and shift register [therefore selection δn
The switch circuit is configured so that the data that was launched into Pyru's main amplifier is sent to the input/output buffer, or the data from the input/output buffer is transferred to the desired memory cell. I'm here.

The above-mentioned memory cell array 1 and main amplifier 5 will be explained in detail later in FIGS. 5(A) and 5(B). ill@1
Control key signal φ from circuit 7. , based on)
Ia 77 Fu 5 Is the data included? The output order I) is output to the output terminal I/'1, which is transmitted from the input terminal Dln to the selected memory cell V in the memory cell array at each main amplifier tbIL. Do not move.

The successive convolution control circuit 7 receives the inner S control No. 16 φ supplied from the nnrsr2 timing Geno circuit 4. 1 and CP
Based on the write enable signal WE supplied from U etc., an excessive control signal φ is sent to the input/output cover sofa 6. , there is a sea urchin that outputs sound.

In this embodiment, in addition to the above configuration, various circuits as described below are newly provided.

8. It is a mode selection circuit, and although there are no limitations to this,
It is constituted by a decoder constructed by combining two appropriate logic gates.

9, the Y-DEC (X decoder) #51I circuit receives the output signals φA, φ, and from the mode selection circuit 8, and controls the X decoder to determine its state. φa. Output τ.

10, an output signal φ8. from the mode selection circuit 8. φ
This is an S, R (shift register) control circuit which receives a signal p'l and outputs a control signal for controlling the state of the shift register 11.

The shift register 11, which will be explained in detail later using FIGS. 3 and 5 (Aj), is, for example, a shift register composed of a plurality of flimps δn, yc.

Year 517.1 CA) ij, the above memory cell array 1. X decoder 3b, X decoder 3a, main amplifier 5
．． 3 is a detailed front diagram of the shift register 11 and the input/output buffer 6. FIG.

In this fact 1#11+II, although it is not limited to the old man, the memory cells are arranged in the so-called two-point system. 0
As shown in the figure, a word 41JWLt) (n "" 0 to 255) coupled to the output node of the X decoder is connected to the output node of the .

As a memory cell, there is no limit to the number of cells (in Figure 5).
As shown in vC, one information storage capacitor CM and one address supply MO8FET (insulated gate type field effect transistor) QM are formed t'L7?
1) A transistor type memory cell is used.

1i data line Dn, ICU between Dn, sense amplifier SAn and main amplifier MA, l or xlk Taly QCm
A is placed on the table. Further, a decode output signal 7n from the Y decoder 3b is applied to the pair of data lines Dn and Do, respectively.
In addition, the switch circuit SWn is switched to the switch 1ti11@Iδn by the output signal from the flip-flop FF in the shift register 11 corresponding to this output signal yn.
It is coupled to a pair of common data lines CD and CD.

As will be explained in detail with reference to FIG. 3, the shift register 11 is modified by modifying the decoded output signals corresponding to each of the flip-flops U and Y decoder 3b formed in the shift register 11. The settings are detailed.

A pair of common data Yutaka OD, CDi'ff, son
The input and output are connected to the cover sofa 6.

In addition, in FIG. 5(4), dummy cells are omitted in order to make the r part of the drawing flat.

Next, this practical operation will be explained.

1. Normal random access mode [j, -i'j
Readout of 1 focus rate, convolution operation? This will be explained using FIG. 1, FIG. 5, and the second figure sound.

When the RAS signal supplied from the outside falls from a high level to a low level as shown in FIG. 2, the open side No. 100 φ□ at a high level is output from the timing generation circuit 4 to the address buffer circuit 2aK. Sanru. Then, the address buffer circuit 2a takes in the address number 100 Axo-Ax,r that is being supplied to the address bin at that time and launches it internally. Subsequently, the timing generator circuit 4 outputs a high-level signal 1g to the X decoder 3a, and then output signals a and a from the address buffer circuit 1E62a to the X decoder 3a.
Based on Xi Then, the selection δf′
L, the data of all the memory cells connected to the word net, that is, the data for one row, is sent to the internal sense amplifier S.
Added 1@ to An, including main amplifier MAnK.
Then, amplify and launch the timing generator circuit 4.
The OA8 signal supplied from the outside is connected to the RA in Figure 2.
No. 8 signal then changes from high level to low level Kf-a
When n, a high level control signal φy is output to the address buffer circuit 2b. Then, the address buffer circuit 2b takes in the address signals A y o to A y y that are being supplied to the address bin at that time and launches. As a result, the control signal 16 φy2 at a high level is output from the timing generation circuit 4, and the Y decoder 3b is activated. Address buffer circuit 2b to Y decoder 3b
Based on the outputs ayt and ayt, one decode output signal 7nk corresponding to address signals Ayo to Ayy is set to high level, and the remaining nine Qi code output signals t are set to low level. Due to this, the coupling δ to the path SWn
A pair of data lines DΩ, Dnn5, “f:t”L
It is electrically coupled to the SOF'L common data OD and CD. In other words, among the data launched in the main amplifier MA of the 2561, the data of the memory cells on the -M selected data lines are stolen into the cover sofa 6. The input/output cover sofa 6 receives a control signal φ from the 6-source output saving A system-circuit 7. 2 is sent from the main amplifier 5 and output to the output terminal Dout.

In heat-intensive operations, the human output is 6 or the control is 100 φ. , based on the input terminal Din, common data 4ycD.

The potential of the CD is set to 1ζ in accordance with this captured data.Similar to the continuous read operation, the selection is also made in accordance with the address signal.The common data line CD or CD is connected to the memory cell. A voltage corresponding to the voltage of .delta.n1 is applied, and the captured data is transferred to the selected memory cell.

Next, regarding the operation in page mode, Section 1.1.
Figures 2 and 5 (explained using N purple).

When the main amplifier 5 (VC) goes down, the amplified data is output from the input/output buffer 6, as shown in Figure 2. When the OA El signal rises, the timing generation circuit 4 outputs an error level. 1111 both signals φdl
is output. Then, the address signal input circuit 2b inserts the signal tone δn into the address bin and launches it. Next, a high level control signal φ1. is output. In addition, the outputs 4g (a) and (a-) of the area address buffer circuit 2b are taken to the mode selection circuit 8 and decoded to form the old mode i4 selection signal.

Ato synchronized with the first rise of the old CAS issue.

For Respin, you should choose between each mode, and
If you face it in advance, as shown in Table 1, the mode selection 7ttl + 1st gear consisting of 8 pins with the 8 pins installed will be placed in the bag. Therefore, if the mode selection system # signal supplied to the address bin in synchronization with the rise of the CAS signal rises to 1XL'' level, this occurs in the mode selection circuit 8. After decoding δ, the beige mode exit signal φF is output (see FIG. 2).

The following is a white table: 1 Then, the Y-tecoder control circuit 9 receives this mode selection signal φ.
Due to my busy schedule, I planted Ybukoyuda 3b Oaccess River HQ. Therefore, the next time the Tanhi CAB signal falls, the address buffer l! 2I approximately 2bK taken in 'Efi address signal Aa. ~A, the data corresponding to green is withdrawal a
tt, 6. As a result of this step 11, the data on the selected data δf' out of the data 1ζ held in the latch 6 in the main amplifier 5 is provided to the input/output buffer 6 and becomes the output name n. In this way, every time the SA AB I M falls, in synchronization with this, only the row A 1116 A y t is faintly mixed, and the corresponding data is read out. Page mode is executed.

Next, without changing the address signal, multiple data r
Operation when inputting/outputting the series
2 Figures 1, 2, 3, and 5 (A for 4h will be explained. As one of them, the operation sound in nibble mode will be explained. At the rising edge of 9, the address expander circuit 2b [fetch 1 mode selection signal is set to address A, , A, as shown in (2) of Table 1.
, is at the "H" level [i, the mode selection circuit 8 is powered down, and the mode selection signal φ, which executes the nibble mode r, is output. In response to the mode selection signal φNk, the shift register control circuit 10 operates as a shift register of the aJ variable shift register 1tv4i.
Make sure there is no bt access name.

The phase-change shift register 11 is configured as shown in FIG.
It is arranged so that it can operate as a shift register with any number of stages depending on the control signal from 0. In the illustration <1i
A mode selection signal φ is outputted from the mode selection circuit 8 to the variable shift register 11 consisting of flip-flops F, F, 0 to F, F, n.
Then, the shift register control circuit 10 controls the gate G.
When 4 is opened, the pond gate Gs...Gn is all closed.71. Then, shifts are repeated between the flip-flops F, F, Q to F, 7, and 3 on the open game G4L side, operating as a four-stage shift register. This four-stage shift register 11 is not particularly limited, or a clock pulse φ is generated from the shift register control cycle 1slO in accordance with a change in the CjAB signal. , the high level is shifted one by one for 1+1j. That is, the output signal of the fourth class shift register 110 is the clock pulse φ. Every time p is applied atL, the level increases by δtL. If you look at the field, if the output signals of I', F, and 2 are at high level, and the output signals of the other three flip-flops are at low level, the OAS signal will be Change ζ clock pulse φ. , is applied to the shift register 11, the output signals of the flip-flops F, 'F, and 'L become high level, and the output signals of the other three 7-lip flops become low level. In this way, each time the CA31 number changes in the shift register 11, the high level is shifted one after another.

The address signal A y t taken in by the address buffer 2bK when the CAS signal first falls is applied to the flip-flop whose output signal is set to high level at the beginning. In other words, each decoded output signal of the Y decoder 3b is set at δn so that it is supplied to the corresponding flip-flop, and its state is set according to the decoded signal supplied to the flip-flop. The back of the sea urchin has 0 awns. Therefore, in response to the address signal A y t taken in, the decode signal '(reception'/f
The output signal of the 7th flip-flop immediately goes to level... In contrast to this 'nVc, the output signals of the remaining flip-flops are 1 when the corresponding decode signal is low level.
For example, address signals hy, VC+: and the output signals of flip-flops F, F, 2 are set to low level. The 2tC compatible switch circuit sW2 is turned on. As a result, the data of the memory cell that had just been launched into the main amplifier number MA is provided to the human output vanofer 6 after two switch times, and is sent to the output terminal Dout of the output system n. As mentioned above, each time CA31g changes, the output signal at Ilh of sw, swo, SW, becomes -E level, so the output terminal I)put or Rani,
Main amplifier MAL data, MAQ data, MA3
The output system will be sent to ++* of the data. Ding, that is,
The data of 4 pins is read out serially.

The above explanation is about the nibble mode. ), address A. .

AI, if only AI is set to H# level,
Part-time job mode? A mode till signal φ, which can be executed, is generated as hX in the mode selection circuit 8. Then, in response to the control signal outputted from the shift register control circuit 1'0, only the gate G8 of the variable shift register 11 is closed, and the gates of the gate are closed.

As a result, variable shift register 1li-f'84f
It operates as a shift register. As a result, c
The data of 8 pins is serially read out from the main amplifier 5 by the toggle VC of As1g.

In this way, each stage of flip-flops F, F, 0, F, F forms a variable shift register.

1,...F, F, n, etc., if the final stage pulse is provided at the gate of the feedback 3 logic, the number of stages of the shift register is n (up to 256 stages in the actual IM column). Within the range of 1. An arbitrary number of hints of data r can be read from the serial VC.

Moreover, in the circuit of the implementation column, the selected mode r is determined by the 8-pin mode allowance @ signal, so in this case, a maximum of 256 modes can be selected. As a result, the RAM is preset with a ripple mode as shown in Table 1(n), in which one line of data digits is serially read out, and this f'Lk transparent You can choose and execute it.

When using the shift register ll'f as in the nine-nibble mode and ripple mode described above, a control signal φ is supplied from the mode selection circuit 8 to the Y-decoder control circuit 9, and the Y-decoder control circuit 1 is supplied with the control signal φ. TM9 is designed to prevent Ytekota 3br from operating.

When a special I/ciltII layer is set, f is placed in a floating state at each output node of the Y decoder 3b.
l, 6° Therefore, the operation of the shift register 171'-1
Therefore, the Y decoded signal does not give any negative effects.

The shift register control circuit 10 selects the shift register 11 from the mode selection circuit 8, and the shift register control circuit 10 selects the shift register 11. It's awned so it doesn't work.

When using in page mode, address No. 18 Ay
When the decoded signal of Y decoder 3b determined by I is set to high level, the output signals of flip-flops F, F, 2 are set to high level, and the next address No. 18 A y IVc
Therefore, flip-flop IP? , 255 may be at a high level. In this case, when the output signal of the flip-flop F, F, 255 is at a high level, the Flinoff 77'F, F, 3 if,
One low level note code output signal of the Y lever 3b causes its output signal to become low level. The same applies to C in normal mode. Therefore, when in page mode or i/-mal mode, shift register 11 does not give any malfunction to the operation.

Furthermore, in the above circuit, the write enable signal WF
When writing data when i goes low level 6, the bladder convolution control circuit 7
Garano control wholesaler 1g φ. t, therefore, the supply δ71. from the input terminal D1n. The data is transferred to the memory cell selected by the X decoder 3a through the switch circuit turned on by the Y decoder 3b or the shift register 11. Therefore, even in page mode, nibble mode, byte mode, etc.
It is possible to input 4 data.

In addition, the variable shift register lli configuration (G)
４、G、・・・・・・Gn, the arrangement is M O
S') transfer gate r can be used.

In addition, in the above embodiment, the open side I/H rotation from the timing IE circuit 4 is modified to operate the decoder as the mode selection circuit 8. ) Signal (Ao ~ A,) To create the RAE3 signal and the CAB signal button direct fold human signal for the song, one thing is to assemble a gate circuit to form a mode selection circuit of 8 mode selection circuits. is also possible.

In addition, in the above implementation, the switch circuit and the shift register were supplied with decoded signals from the same Y-tecoder 3b, but decoded signals from different decoders were supplied to the switch circuit and the shift register. Even if it is supplied, it will be difficult.

In addition, the decode signal from the shift register 11 [id, Y decoder 3b] should not be supplied, and when the shift register 11 is in a mode such as nibble mode or byte mode, the constant flip-flop Alternatively, in FIG. 3, the output signals of the flip-flops F, ?, 0 may initially be at a high level.

In the first embodiment and in FIG. 5, the main amplifier may be removed, the sense amplifier may be provided with a launch function 7, and the main amplifier km may be matched to the common data line. In this case, since the number of main amplifiers is reduced, the chip surface can be reduced and the cost can be reduced.

l! Then, in the upper bC real column, the data latched by the variable shift register 11 to the main amplifier 5 is read in the order of r and δn, but the data from the sense amplifier is latched and shifted to hp=m. Set up a register,
this? The shift register control circuit 10 may shift 'g+t' according to the selection mode.

In the above-mentioned implementation, the third rising edge of CABABO was taken into account, and at that time, the control signal for mode selection was taken into the address bin. Here, the interrupt information for selecting the mode is set after the address bin t1 so that it is entered in the time + + ' mode.

Conventionally, an address signal is supplied to the address bin when the RASi ;; and CAB information are in line, but CAS
It was an irregular period of time, as the address bin was begging for the level of work when the Hakugo signal went up. Seven yc, implementation 1+
Like lJ, address bin ytO1l! Therefore, even if a mode selection signal is supplied, the access time will not be lengthened by this tL.

Due to my colleague's reasons, during the period of the address bin or the song being played, the clear signal is to select the mode from the address bin at the start of CABABO for the third time or later. It is also possible to import the information. ``!'' It is also possible to determine the selected mode by the signal supplied to the address bin when the CAB terminal rises when the rcXmd is turned on.

Historically, a control signal for mode selection? Instead of using the address bin R as the supply bin, the data input bin Din, etc. may be used instead of the address bin R.

64 bit dynamic RAM Ti, internal refresh circuit installed, cAse before the RAS signal goes down.
When the falling edge of the g signal is detected, the internal refresh is performed visually. In a 16-bin package (34kRAM), the 1st pin, which was conventionally used for inputting the refresh signal, will be used for internal refresh. It can be used as a dedicated input pin for the mode S selection side signal.

For the reason of four balls, even with a 1 mega pin Dyna Mink RAM with an 18 pin pan cage, there is one extra yashibin, so
This can be used as an input pin for mode selection control signals. If arranged in this way, there is no need to supply signals using a complicated time-division system, so there is an advantage that the RAM becomes easier to use.

So far, an implementation has been described in which the external terminal (bin) r is used to supply a mode selection signal. In this method, the user can use the provided RAM1 as needed.
It has a Melint ligature that can also be used as a mode.

On the other hand, the only mode L+U has a slight disadvantage of 2M in that even if the RAM 1 is used only as the nibble mode, the mode selection control f81 signal 7 must be supplied.

Next, external terminal? We will explain how to select a mode that is not used. In this method, the manufacturer selects and sets modes according to the user's anxiety and introduces them to the user.

In the circuit of the embodiment row (FIG. 1), the band 7 is provided at the input terminal of the mode selection circuit (tecoder) 8,
By all wire bonding, 'power supply voltage (Vo
. )-! It is selective for the band that continues to play on the ground (OV). In addition, the power supply voltage (Vo.)
A fuse element is provided between the ground and all input terminals of the mode selection circuit 8, and one of the fuses is cut off. 1CJ1: The mode selection control (E) signal (Table 1) corresponding to the shield mode is always input to the mode selection circuit 8x51:, the level of each input terminal can be set. . The mode selection circuit 8 outputs a mode 28 option number for executing the desired mode.

When the mode is set according to the high level or low level of the mode selector, as in the case where a dedicated external terminal R is used to input the mode exit monthly discount [phase] signal, If the band is connected to a dedicated external terminal, the external terminal may be replaced by wire bonding to a pad connected to the voltage (Vo.) or ground, or the level may be set using a fuse element. By fixing P
You can set the awn to the desired mode.

ii [,mode selection circuit 8? Instead, circuits for executing each read write-up mode are separately formed around the memory cell array 1, and the circuits for executing each mode are provided with circuits connectable to external terminals. As a result, the user (2) -5 & desired VC ratio selects the 2S1) circuit from among these circuits and connects the band of that (B) route to the external terminal using all wire bonding, and connects the H
[Notes on how to execute the desired mode:) You may also create a device "c".

In addition, in this invention, as shown in FIGS. 4(A) and 4(B), the memory cell array is 41 or
Configure a suitable enemy such as 1M+ with the divider nk memory cloak, read one pin from each cloak at the same time using the X-tecoder and Y-tecoder, latch it to the sense amplifier, and shift it to R. It can also be used in memory devices such as 4-pin or 8-pin data τ that can be outputted to number llln by a register and read serially.

Also, this invention is not limited to RAM (RAM), ROM (read/read memory).
It can also be easily applied to (only memory).

As explained above, this invention has the following advantages: 1. Since the mode can be selectively set, it is possible to form the same mask pattern on the memo 92 having multiple reading convolution modes such as page mode, nibble mode, and byte mode. Therefore, Memo IJ with each mode
'Is this an advantage compared to designing and manufacturing them individually, and does this result in lower manufacturing costs? can be significantly lowered.

Also, each mode 2 is provided externally? ! If selection is made possible by a control signal generated by 8δ, each mode can be executed depending on the necessity, which has the effect that the memory capacity can be reduced by 8&delta.

Furthermore, if the control signals for mode selection are interspersed in a time-division manner, the functions of the memories can be made to be the same without increasing the number of bins δ.

Furthermore, if control signals for mode selection are taken in in a time-division manner using address bins, it becomes possible to store a large number of modes in one memory.

In addition, by applying this invention to the 1112 of each tTi read convolution mode, the data output I)ou in FIG.
T? A circuit that needs to be changed as shown by the broken line is installed inside the chip, and this circuit is controlled by an external control signal. It may also be possible to select the operating mode. This allows the functionality of the memory to be improved.

[Brief explanation of drawings]

FIG. 1 shows an actual flow of the conductor storage device according to the present invention.
Figure 2 is a timing chart of the signals of each part of the circuit, Figure 3 is an elliptical diagram of the memory cell array showing one row of the configuration of the fil variable shift register, and Figure 5 (A) i-t. , memory cell array, Y decoder. FIG. 5B is a block diagram of an X decoder, a main amplifier, and a shift register, and a circuit diagram of a memory cell. 1...Memory cell array, 8...Mode) i! ! I
Selection circuit, 11...shift register. Agent Patent Attorney Bo 1) Li Xin ゛1. Noi,,,,,+:,,:,,1st r,! l"'y1 4> Figure 3 No. 7J l-4

Claims (1)

[Scope of Claims] 1. A memory cell array consisting of several memory cells arranged in a matrix; δn so that all data can be stored in the 1111st read awn n5It memory cell array.
A mode execution circuit for executing a plurality of different write-out writing methods in a semiconductor memory device, and a mode selection circuit for selecting and executing one of these write-out convolution methods. Set W + stage? A semiconductor memory device that is similar to that of the original. 2. Is it the above mode selection setting method or the Fushushin's resistance convolution method? IJ2 provided in the above mode execution circuit to execute
Each level of several terminals? The level to be set consists of meditation + step, and the level setting means is set to a predetermined level of 1 and 72. 2. The semiconductor self-storage device according to claim 1, wherein n or - modes corresponding to the terminals are executed. 3. Multiple read/write methods are used to execute the above mode execution circuit or each mode is formed separately.12. Claim 1, characterized in that one of these circuits is selectively connected to an external terminal of the Jar, so that a desired mode is executed. The semiconductor storage device described above. 4. The mode selection setting means is a mode selection circuit that receives a mode selection control signal supplied from a dedicated external terminal, selects a corresponding mode, and operates the mode execution circuit. The semiconductor memory device according to claim 1. 5. The upper mode selection setting means is provided in a time-sharing manner from an external terminal.Mode: I8 selection control number r, selects the corresponding mode tS, and selects the upper d own mode execution circuit. The mode selection circuit that allows you to move
+ Kozue Mosquito's range 1st hU2 semi-offensive sd memory w,. 6. Claim 5, characterized in that the mode selection setting means comprises a decoder which decodes the mode selection control signal supplied from the address bin to select and execute the corresponding mode. The semiconductor storage device described above. 7. The mode selection setting means receives the mode selection control signal in synchronization with the rise of the column address strobe (g) and selects the corresponding mode. 8. The semiconductor memory device according to claim 5 or claim 6. 8. The mode execution circuit includes a shift register r, and the shift register is shifted down by a predetermined number of stages to achieve the desired focus. Claims Ifll is characterized in that the data of
! The semiconductor memory device according to item 2, item 4, item 5, yari, 6, Hana, or Katsutsugu, 7.