JPH05204847A - Data transfer controller - Google Patents

Abstract

PURPOSE:To transfer data not through a data buffer in a main storage device. CONSTITUTION:A transfer control part 10 sends a request to read data and a request to write data to a transfer source and a transfer destination according to a data transfer request signal 100 from a processor 2. The output of a 1st address register 12 which holds the read start address of the data outputted from the processor 2 and outputs it as an address signal and the output of a 2nd address register 13 which holds the write start address of the data outputted from the processor 2 and outputs it as an address signal are connected selectively to the data readout destination and data read-in destination by the transfer control part 10 to specify the read and write addresses of the data. The transfer control part 10 transfers the data to an extended storage device 4 through the data buffer 11, but transfers the data to the main storage device 3 not through the data buffer 11 according to the data transfer request signal 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device, and more particularly to data transfer for transferring data between a main storage device in a computer and an external expansion storage device or between different storage locations of the external expansion storage device. Regarding the control device.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional data transfer operation when data stored in a storage location of an external expansion storage device connected to a computer is transferred to another storage location of the same expansion storage device. FIG.

When the amount of data to be processed becomes enormous, it becomes impossible to store the above-mentioned data only in the main storage device 3 incorporated in the computer that processes such data. Therefore, in the above-mentioned computer, the extended storage device 4 is connected to the outside, and data which cannot be stored in the main storage device 3 is stored in the extended storage device 4 and stored in the extended storage device 4 as necessary. It is normal to read the data in the computer and use it.

As described above, in the computer system having the extended storage device 4 externally, the data stored in the specific storage location of the extended storage device 4 is transferred to another storage location of the extended storage device 4. Will be required.

In such a case, in the conventional computer system, as shown in FIG.
When the data stored at the addresses a1 to a2 of the above is transferred from the addresses b1 to b2 of the extended storage device 4, the data stored at the addresses a1 to a2 are added to the buffer area in the main storage device 3. The data is read out by an amount corresponding to the storage capacity of 20 and stored in the buffer area 20.

Next, the data stored in the buffer area 20 is written in the direction from the address b1 to the address b2 of the extended storage device 4, and subsequently from the address next to the already read address in the extended storage device 4. Buffer area 20
The storage capacity is stored in the read buffer area 20 once, and the stored data is sequentially written from the address next to the address where writing has been completed toward b2. Hereinafter, the same operation was repeated until the transfer of the required data was completed.

[0007]

In the computer system using the above-mentioned conventional extended storage device, when the desired data stored in the extended storage device is transferred to another storage location of the extended storage device. , Once the desired data is read into the buffer area in the computer, this data is transferred to the desired address in the extended storage device for writing, so a large amount of data can be read into the buffer area of the main storage device at one time. Therefore, in order to write the read data to a desired address of the extended storage device at one time, it is necessary to provide a large-capacity buffer area in the computer. The data to be transferred to the buffer area in the main memory having a small storage capacity is sequentially read and read from the expansion memory in a large number of times. Transfer time since going to transfer data between different storage areas of extended storage by repeating a write only successively extended storage unit has a drawback that a long.

Further, when the access to the main memory for transferring such data competes with the access for other information processing to the main memory from the processor, the access efficiency of the processor decreases. However, there is a drawback in that the throughput of the entire conventional computer system having such a main storage device and an extended storage device externally decreases.

It is an object of the present invention to exclusively control the transfer of data between different addresses of the extended storage device and the transfer of data between the extended storage device and the main storage device, and to control the transfer of these data in the main storage device. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transfer control device capable of performing the above-mentioned data transfer without using the above data buffer and without competing with the access from the processor to the main storage device.

[0010]

A data transfer control device of the present invention is controlled by a data transfer request signal from a processor, and is provided between a main storage device and an extended storage device and between different storage locations in the extended storage device. In a data transfer control device that transfers and controls data, a first address register that holds and outputs an address of a transfer source of the data output from the processor, and a transfer destination of the data output from the processor A second address register for holding and outputting the address, and a data buffer for temporarily storing the data read from the transfer source controlled by the write request signal and reading the stored data controlled by the read request signal. , The output from the first address register in response to a first selection signal A first selector that outputs a read address signal of the data to any one of the storage devices, and an output from the second address register according to a second selection signal to the main storage device or the extension storage device. A second selector for outputting as a built-in address signal and the first and second selection signals according to a data transfer request signal from the processor, and at the same time, sending a data read request signal to the transfer source to control data read. When the transfer destination is the extended storage device, the write request signal and the read signal subsequent to the write request signal are sent to the data buffer to control the data buffer, and the data buffer is controlled via the data buffer. The data is output and a data write request signal is sent to the extended storage device to control the extended storage device to send the data to the extended storage device. When the data output from the buffer is written, and when the transfer destination is the main storage device, a data write request signal is sent to the main storage device to transfer the data read from the transfer source to the main storage device. And a transfer control unit for controlling the writing.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data transfer control device of the present invention, and FIG. 2 is an explanatory diagram showing the relationship between the data transfer control device of FIG. 1 and a processor and other devices.

The data transfer control device 1 includes a transfer control unit 10
And the data buffer 11 are the main components.

A data transfer request signal 100 including information of a data transfer source and a data transfer destination is applied from the processor 2 to the transfer control unit 10, and the first address of the data to be read by the processor 2 is read. The address signal 102 that specifies the first address register 12
And an address signal 103 designating the first address to write the data of the transfer destination of the data is added from the processor 2 to the second address register, and
A value indicating how many times the storage capacity of the data buffer 11 has the data to be transferred, that is, a data block number request signal 101 indicating the number of blocks is given from the processor 2 to the block counter 15.

First, the operation of the data transfer control device 1 of the present invention will be described in the case of transferring data stored at an address in the extended storage device 4 to another address in the extended storage device 4.

The transfer control unit 10 receives the data transfer request signal 10
If the data transfer source is the extension storage device 4 according to the content of 0, the read request signal 302 is output and added to the extension storage device 4, and at the same time, the address output from the first address register 12 for designating the read address. The first select signal 205 for selecting and outputting the signal 203 as the address signal 304 input to the extended storage device 4 is selected by the first select 14
Output to.

Further, a data write request signal 303 is output to the extended storage device 4. Further, the second selection signal 206 for selectively connecting the address signal 204, which is output from the second address register 13 and specifies the write start address of the write destination, as the write start address signal 315 for the extended storage device 4. Is output and the write start address signal 315 is applied to the extended storage device 4.

From the extended storage device 4, the data 9 designated by the read request signal 302 and the address designation 203 is sent.
01 is read.

The transfer control unit 10 applies a third selection signal 207 for selecting and reading the data 901 to the data selector 18. The data selector 18 selects the data 901 by the third selection signal 207 and outputs it to the data buffer 11.

A write request signal 307 is output from the transfer control unit 10 to the data buffer 11 to control the data buffer 11 to temporarily write the data output from the data selector.

When the data corresponding to the storage capacity of the data buffer 11 is written in the data buffer 11, the transfer controller 10 outputs a read request signal 306 to the data buffer 11 and the second selector 17 outputs the write request signal 306. Expansion storage device 4 specified by the start address specifying signal 315
The data output from the data buffer 11 is sequentially written in a predetermined direction from this address as the write start address.

When the reading and writing operations are completed, the block number updating signal 200 for decrementing the number of blocks in the block counter 15 by 1 is output from the transfer control unit 10 to the block counter 15. The block counter 15 holds it. The content held is updated to a value obtained by subtracting 1 from the value indicating the number of blocks in which the block is present. The block counter 15 outputs the number of the result obtained by subtracting 1 to the zero detection circuit 16 as a signal 201.

If the value represented by the signal 201 is zero,
The zero detection circuit 16 outputs the zero detection signal 202 to the transfer control unit 10.

If the zero detection signal 202 is the transfer control unit 10,
If it is output to, the transfer control unit 10 ends the data transfer. When the zero detection signal 202 is not output,
An address update signal 20 for increasing the address values of the first address register 12 and the second address register 13 by the number of addresses corresponding to the storage capacity of the data buffer 11.
8 is applied as a control signal from the transfer control unit 10 to the first address register 12 and the second address register 13. When the address update signal 208 is applied, the first
And the second address registers 12 and 13 update the address values obtained by adding the address values corresponding to the storage capacity of the data buffer 11 to the already stored address values as the address signals 203 and 204, respectively, and update the updated values. Is output.

Based on the updated address signals 203 and 204, the transfer control unit 10 sequentially starts from the data stored at the address next to the already read data in the expansion storage device 4 in the same order as described above. The data is read in a predetermined direction, the data is once written in the data buffer 11, and the data written in the data buffer 11 is sequentially determined from the next address in the expansion storage device 4 where the writing has already been performed. Write in the direction.

The transfer control unit 10 repeats the above control until the above-mentioned zero detection signal 202 is output.

Data transfer request signal 1 from processor 2
If 00 is a request to transfer the data stored in the main storage device 3 to the extended storage device 4, the transfer control unit 10
Outputs the first selection signal 205 to the first selector 14 and selectively connects the address designation signal 203 as the read address signal 314 to the main memory 3. At the same time, the transfer control unit 10 outputs the second selection signal 206 to the second selector 17 as a control signal, and the second selector 1
7, the write address signal 204 is selectively output as the write designation address signal 315 and added to the extended storage device 4.

Further, the transfer control unit 10 uses the read request signal 30.
0 is output to the main storage device 3, and the write request signal 303 is output to the extension storage device 4. Data 9 stored at the address starting from the specified address from the main memory 3
00 is read.

The transfer control unit 10 selects the data 900 from the main memory input to the data selector and outputs it to the data buffer 11 as the third selection signal 2 which is a control signal.
07 is output and added to the data selector 18 as a control signal.

The data selector 18 uses the third selection signal 20.
The data 900 output from the main storage device 3 is selected and input by 7 and output to the data buffer 11.

The data buffer 11 writes the data output from the data selector 18 when the write request signal 307 output from the transfer control unit 10 is applied.

Then, the read request signal 3 from the transfer control unit 10
When 06 is output to the data buffer 11, the data once written is read out from the data buffer 11 and the data buffer 11 is read from the address of the extended storage device 4 designated by the write address designating signal 315 in the designated direction. The data read from 11 is sequentially written.

In this case, the operation of the block counter 15 and the zero detection circuit 16 and the operation of the transfer control section 10 when the zero detection signal 202 is output from the zero detection circuit 16 are at an address of the expansion storage device 4 already described. This is the same as the case of transferring the data in 1 to another address of the extended storage device 4, and therefore the description thereof is omitted.

Data transfer request signal 1 from processor 2
If 00 is a request to transfer the data stored in the extended storage device 4 to the main storage device 3, the transfer control unit 10
Outputs the first selection signal 205 to the first selector 14 and selectively connects the address designation signal 203 as the read address designation signal 304 to the extension storage device 4.
At the same time, the transfer control unit 10 outputs the second selection signal 206 to the second selector 17 as a control signal, and the second selector 17 selects and outputs the write designation address signal 204 as the write address signal 305 for main storage. Add to device 3.

Further, the transfer control unit 10 uses the read request signal 30.
2 is output to the extended storage device 4, and the write request signal 301 is output to the main storage device 3. Data 901 starting from the specified address is read from expansion storage device 4, and this data 901 is sequentially written in main memory device 3 from the address specified by write address signal 305 in a preset direction.

When the above-mentioned data writing is completed, the transfer controller 10 outputs a block number update signal 200, and the block number stored in the block counter 15 is reduced by one.

In this case, the write request signal 307 and the read request signal 306 are not output from the transfer control unit 10 to the data buffer 11.

Further, when the zero detection signal 202 is output from the zero detection circuit 16 which receives the output 201 from the block counter 15 which has been subtracted as described above, all the outputs from the transfer control unit 10 are stopped. Then, the above-mentioned data transfer is stopped.

If the zero detection signal 202 is not output after the above-mentioned data transfer, the same address control signal 208 as described above is output from the transfer control unit 10 and the first address register 12 and the second address register 12 are output. The address values of the address register 13 are added by the values already described, and the results are output as the address signal 203 and the address signal 204, respectively, and until the zero detection signal 202 is output, data is transferred from the transfer source to the main storage device 3. The transfer will be repeated.

In the embodiment shown in FIG. 1, the block counter 15 and the zero detection circuit 16 divide the data buffer 11 into data amounts that can be stored in the data buffer 11 to transfer data larger than the storage capacity of the data buffer 11. However, if the storage capacity of the data buffer 11 is sufficient, the block counter 15 and the zero detection circuit 16 of FIG. 1 are unnecessary, and the first address register 12 and the second address register 13 are transfer-controlled. It is not necessary to update the address value by the address update signal from the unit 10, and the first address register 12 only needs to hold and output the read start address of the transfer source that is first output from the processor 2, and similarly. The second address register 13 first holds and outputs the write start address of the transfer destination output from the processor 2. Re if it is it is Akira et al.

[0041]

As described above, the data transfer control device of the present invention does not increase the storage capacity of the main memory device and is independent of this access when the processor accesses the main memory device. It is possible to perform data transfer between different storage areas of the expansion device and between the main storage device and the expansion storage device, and a system for performing the above-mentioned data transfer in a computer system using the main storage device and the expansion storage device. This has the effect of not lowering the throughput of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer control device of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between the data transfer control device of FIG. 1 and another device.

FIG. 3 is an explanatory diagram showing a conventional data transfer operation.

[Explanation of symbols]

 1 Data Transfer Control Device 2 Processor 3 Main Storage Device 4 Extended Storage Device 10 Transfer Control Unit 11 Data Buffer 12 First Address Register 13 Second Address Register 14 First Selector 15 Block Counter 16 Zero Detection Circuit 17 Second selector

Claims (2)

[Claims] 1. A data transfer control device which controls data transfer request signals from a processor and transfers and controls data between a main storage device and an extended storage device and between different storage locations in the extended storage device. , A first address register for holding a read start address of a transfer source of the data output from the processor and outputting as a read address signal, and a write start address of a transfer destination of the data output from the processor A second address register for outputting as a write address signal, and a data buffer for temporarily storing the data read from the transfer source controlled by the write request signal and for reading the stored data controlled by the read request signal And the first
A first selector for selectively connecting and outputting the read address signal to either the extended storage device or the main storage device in accordance with the selection signal, and the write address signal in response to a second selection signal. A second selector for selectively connecting and outputting to the main memory device or the extended memory device; and the first selector in response to a data transfer request signal from the processor.
And a second selection signal, a data read request signal is sent to the transfer source to read the data, and when the transfer destination is the extended storage device, the write request signal and the subsequent read operation in the data buffer. Sending a signal to control the data buffer to output the data via the data buffer to send a data write request signal to the extended storage device to control the extended storage device to send the data to the extended storage device. The data output from the buffer is written, and when the transfer destination is the main storage device, a data write request signal is sent to the main storage device to transfer the data read from the transfer source to the main storage device. A data transfer control device, comprising: 2. A data transfer control device, which is controlled by a data transfer request signal from a processor, transfers data between a main memory device and an extended memory device and between different memory locations in the extended memory device and controls the data. , A read start address of a transfer source of the data output from the processor is held, and when an address update signal is added, a predetermined value is added to or subtracted from the held address value to hold the held address value. And a write start address of a transfer destination of the data output from the processor, and a hold address when the address update signal is applied. The first address register according to the predetermined value for the transfer destination address value. A second address register that updates the address value by the same value as the write address signal and outputs the updated value as a write address signal, and stores the data block number request signal output from the processor. A block counter that updates the value of the held block by 1 when it is added and outputs it, and a zero detection circuit that monitors the output of the block counter and outputs a zero detection signal when the output of the block counter becomes zero. A data buffer which is controlled by a write request signal and temporarily stores the data read from the transfer source, and which is controlled by a read request signal and reads the stored data; and a read address signal according to a first selection signal. A first selector for selectively outputting the signal to either the extended storage device or the main storage device, and a first selector in response to a second selection signal. A second selector for selectively connecting and outputting a write address signal to the main storage device or the extension storage device, and outputting the first and second selection signals in response to a data transfer request signal from the processor. At the same time, a data read request signal is sent to the transfer source to control the data read, and when the transfer destination is the extended storage device, the write request signal and the read signal following it are sent to the data buffer to send the data buffer. To output the data via the data buffer and send a data write request signal to the extended storage device to control the extended storage device to output the data output from the data buffer to the extended storage device. Each time the writing of the data is completed, the address update signal and the block number update signal are output to monitor the zero detection signal. Data is read from the transfer source until the zero detection signal is detected, and control of writing the data to the transfer destination is repeated. When the transfer destination is the main storage device, a data write request signal is sent to the main storage device. Every time the data read from the transfer source is written to the main storage device, the address update signal and the block number update signal are output to monitor the zero detection signal and the zero detection signal is A data transfer control device comprising: a transfer control unit that repeatedly performs control of reading data from the transfer source and writing the read data to the transfer destination until detected.