JP2010049718A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mechanism for interrupting access to an unauthorized address from a bus master device connected to a system bus of a processor with less circuit quantity. <P>SOLUTION: According to the form of the system bus, an address line and a control line between the bus master device and the bus, or an unauthorized address access interruption mechanism is inserted to a control circuit part of the bus. The unauthorized address access interruption mechanism includes a register for setting an address range permitting the access. Whether an address output to the address line is within this range is determined by a comparator. When the address is out of the range, the output of the control line is suppressed, whereby the unauthorized address access is interrupted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to a processor used in a central processing unit of a computer.

  In today's processors, especially microcomputers for embedded devices, a technique is used in which a CPU core that performs general-purpose processing and a plurality of peripheral IPs for specific processing are configured on a single chip, and the system is configured as a single-chip processor. Yes. In such a system, a configuration in which devices such as a plurality of CPUs and peripheral IPs are connected to a bus in a processor is common, and in particular, a bus master that is a side that issues an access request to the bus. A system with multiple devices.

  From the bus master device including the CPU in the processor, (1) a software bug, (2) a hardware bug, and (3) a temporary hardware failure (soft error due to α rays, etc.) on the bus. May occur. Such access is referred to as illegal address access. Especially for embedded devices, product defects due to software bugs are often a problem.

  In the following, a system that performs image input and processing will be shown as an example in the case where an illegal address access occurs in a system in which there are a plurality of bus masters considered by the inventor of the present invention. FIG. 10 shows the system configuration. Reference numeral 810 denotes an image input unit, and reference numeral 830 denotes a memory. 810 and 830 are both connected to the system bus 800. The 810 takes in an image from, for example, a camera, and stores the data in the 830 by performing a bus master operation. Reference numeral 850 denotes a data flow in this operation.

  An image processing unit 820 performs processing such as color tone correction and noise removal. 820 reads image data from the memory 830 and writes back the processing result. Reference numerals 851 and 852 denote data flows.

  Here, since the memory writing 850 from the image input unit 810 and the memory writing 852 from the image processing unit 820 need to be performed in parallel, it is necessary to switch so that there is no collision in the memory area accessed by both.

  FIG. 11 is a memory map in the system shown in FIG. A portion indicated by 910 is an area of the memory 830. In order for the image input unit 810 and the image processing unit 830 to operate in parallel, the image input unit 810 writes in the area 921 in the area 910 and the image processing unit 830 writes in the area 920 for a certain period T. This avoids memory area collisions. Similarly, in the period T + 1, 922 and 921, respectively, in the period T + 2, 920 and 922, and so on.

  The avoidance of memory area collision by area switching as described above is particularly important in a system having a plurality of bus masters. For example, when an illegal access occurs due to a bug in the control software and a memory area collision occurs, there arises a problem that the image data is not processed correctly.

  Some CPU cores, which are representative of bus master devices, have a mechanism called an MMU (memory management unit), and have the ability to detect and block illegal address access. However, generally, the peripheral IP does not have an MMU. Here, when a general MMU is applied to the peripheral IP, the MMU also performs conversion from a virtual address in the CPU core to a physical address. For the purpose of blocking unauthorized address access, the overhead of circuit amount, The software overhead for handling it is large. Therefore, it has been found that it is difficult to apply the MMU for the purpose of detecting and blocking unauthorized address access from the peripheral IP.

  One object of the present invention is to provide an illegal address access detection / blocking circuit with a small amount of circuit overhead.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, an information processing apparatus comprising a first bus master device, a first slave device, and a bus connected to the first bus master device and the first slave device, wherein the first bus master device When accessing one slave device, a first illegal address access blocking circuit is provided for detecting and blocking unauthorized access to the first bus master device.

  More preferably, the first illegal address access blocking circuit has a range setting register for setting an access prohibition range.

  More preferably, the range setting register includes a first register that holds an upper limit address of an address assigned to the first slave device, and a second register that holds a lower limit address. The address access blocking circuit further includes a comparison circuit for comparing whether the address output from the first bus master device is included in the address range indicated by the first register and the second register.

  According to the present invention, a highly reliable information processing apparatus with a small circuit amount can be realized.

1 is a system configuration according to a first embodiment. 2 shows a bus configuration and device connection in the first embodiment. The illegal address access blocking mechanism in the first embodiment. Operation of illegal address access blocking mechanism. The system configuration in Example 2. 7 shows a bus configuration and device connection in the second embodiment. The illegal address access blocking mechanism in the second embodiment. An embodiment of a processor to which an illegal address blocking circuit is applied. 2 shows a second embodiment of a processor to which an illegal address blocking circuit is applied. A system with multiple bus masters. The memory map in the system shown in FIG.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of an information processing device according to the invention will be described with reference to the accompanying drawings. Although not particularly limited, circuit elements constituting each block of the embodiment are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit technology such as a CMOS (complementary MOS transistor) or a bipolar transistor. It is formed.

Example 1
1 to 3 show one embodiment of the present invention. In the present embodiment, the system bus structure uses a bus format in which a control line, a data line, and an address line are shared by a plurality of devices.

  FIG. 1 simply shows a configuration of the entire system in the present embodiment, and each component is formed on one semiconductor substrate, although not particularly limited. A system bus 100 in the processor has a configuration in which a control line, a data line, and an address line are shared by a plurality of devices. 110 and 120 are bus master devices that access other devices via the system bus 100, and 130 accepts requests from the master devices 110 and 120 via the system bus 100 and responds to the system bus 100. Returns a slave device.

  As an example of such a system configuration, for example, a system having two bus master devices, that is, an audio processing IP and an image processing IP, and writing each processing result to a serial interface as a slave device is conceivable. .

  In this embodiment, a system of two bus master devices and one slave device is assumed. However, the method of the present invention does not limit the types and number of these devices.

  111 and 121 are main circuits of the bus master device, respectively. 113 and 123 are illegal address access blocking circuits of the present invention, which are connected to the main circuit 111 and 113 of the bus master device through the connection lines 112 and 122 and to the system bus 100 through the connection lines 114 and 124. Yes. The slave device 130 is connected to the system bus 100 through a connection line 131.

  As will be described in detail later, the unauthorized address access blocking circuits 113 and 123 have a function of detecting and blocking unauthorized access to the bus master device when the bus master device accesses the slave device.

  FIG. 2 shows the connection relationship between the system bus 100 itself and the system bus 100 and the connection lines 114, 124, and 131.

  The connection line 114 that connects the bus master device 110 and the system bus 100 includes a 210 request control line, a 211 read / write designation control line, a 212 address line, a 213 write data line, and a 214 read data line. .

  The request control line 210 is not particularly limited, but “H” indicates that a request is requested and “L” indicates that there is no request. Further, when the request control line 210 is “H”, the read / write designation control line 211 indicates “H” indicates a read request, “L” indicates a write request, and the address line 212 indicates the target address. In the case of a write request, data to be written is output from the write data line 213. In the case of a read request, data is input from the read data line 214. A connection line 124 that connects the bus master device 120 and the system bus 100 has the same configuration as the connection line 114. 210 to 214 correspond to 220 to 224, respectively.

  The connection line 131 that connects the slave device 130 and the system bus 100 includes 230 request control lines, 231 read / write designation control lines, 232 address lines, 233 write data lines, and 234 read data lines. For example, the output from the request control line 210 is transmitted to the request control line 230. The slave device inputs data from the write data line 233 or outputs data to the read data line 234 through the connection line 131.

  FIG. 3 shows the internal configuration of the illegal address access blocking circuit 113 included in the bus master device 110 of the present invention. The same applies to the illegal address address blocking circuit 123 included in the bus master device 120.

  The signal lines 310 to 314 constitute the connection line 112 and correspond to the signal lines 210 to 214 constituting the connection line 114 with the bus, respectively.

  Reference numeral 320 denotes an unauthorized address access detection unit. The registers 321 and 322 have a range setting register for setting an address range in which the bus master device 110 accesses the slave device 120. The register 321 stores the upper limit of the address range permitted to access the bus master device 110, and the register 322 stores the lower limit address value. Although not explicitly shown in the figure, these registers can be set through the signal line 112. The register may be set by software processing at the time of power-on, or may be configured to be automatically set upon detection of power-on.

  Reference numerals 323 and 324 denote comparators. The comparator 323 compares the value of the address line 312 and the value of the register 321, and outputs “H” to the signal line 325 when the value of the address line 312 is larger. To do. Similarly, the comparator 324 compares the value of the address line 312 and the value of the register 322, and outputs “H” to the signal line 326 when the value of the address line 312 is smaller. Therefore, the signal line 327 which is the logical product of the signal line 325 and the signal line 326 becomes “H” output when the value of the address line 312 is within the range specified by the register 321 and the register 322.

  Reference numeral 330 denotes an illegal address access blocking unit. When the output of the signal line 327 is “H”, that is, the value of the address line 312 is within the range specified by the registers 321 and 322, the output of the request control line 310 is directly sent to the request control line 210. Is output. Conversely, when the output of the signal line 327 is “L”, that is, outside the access permission range, even if the output of the request control line 310 is “H”, the output of the request control line 210 is “ L "and unauthorized address access is blocked. Further, the signal line 327 is output as it is as the signal line 315 and notifies the bus master device main circuit 111 that it has been cut off. In this way, unauthorized access can be blocked. In this embodiment, only one set of the registers 321 and 322 and the comparators 323 and 326 is provided. However, when there are a large number of slave devices, the present invention can be realized by providing according to the number of slave devices. Needless to say. The addresses stored in the registers 321 and 322 may be configured to store all the bits indicating the address, or may be configured to store only a part thereof. That is, it is only necessary to specify a range where access control is desired. For example, when it is desired to perform the above-described illegal address detection in the range of H'080000 to H'0BFFFFFF in the address space of the corresponding slave device, the upper 8 bits may be set. In this case, the registers 321 and 322 and the comparators 323 and 326 can be made small and can be realized with a small area. Alternatively, the registers 321 and 322 may be set to 32 bits. In this case, it is possible to set a range for detecting an illegal address more finely, and it becomes easy to apply to a plurality of slave devices having different address ranges.

  FIG. 4 shows an operation in the case where an access to a normal address and an access to an illegal address occur in a processor counting the illegal address access blocking function. Reference numerals 700 and 710 indicate one clock period, and transitions of the request control signals 310 and 210, the address line 312, and the internal signals 325, 326, and 327 of the illegal address access blocking mechanism 320 in this period.

  In the period 700, the value 701 of the address line 312 is within the range set in the registers 321 and 322. At this time, the outputs of the signals 325 and 326 are “H”, and the output of the signal 327 is also “H”. Therefore, “H” equal to the request control signal 310 is also output to the request control signal 210.

  In the period 701, the value 702 is larger than the lower limit set in the register 322. At this time, since the output of the signal 326 becomes “L”, the output of the signal 327 also becomes “L”. Therefore, while the request control signal 310 is “H”, the request control signal 210 is “L”, and unauthorized address access is blocked. In the case of an illegal address access, there is no particular limitation. For example, an exception can be made by drawing a signal line for notifying an interrupt into the master device 110 and performing exception processing on the master device side or detecting the interrupt with software. Processing is performed.

  With this configuration, for a bus master device such as one peripheral IP, in the minimum configuration, two registers, two comparators, and two AND gates, and an illegal address with a small circuit amount An access blocking mechanism can be realized, and product failure due to software bugs can be expected and early detection can be expected.

(Example 2)
5 to 7 show another embodiment of the present invention. In the present embodiment, the system bus structure is a switch type (interconnection network type bus). The switch type (interconnect network bus) bus structure is a structure in which, for example, a connection relationship between a bus master device and a slave device is controlled by a selector. By adopting this configuration, the system bus can be operated at a higher speed. Hereinafter, points different from the first embodiment will be mainly described, but it is needless to say that the matters described in the first embodiment can be appropriately applied to the second embodiment.

  FIG. 5 shows a simple configuration of the entire system when the present invention is applied. Reference numeral 400 denotes a switch type system bus (interconnection network type bus) in the processor. Reference numerals 410 and 420 are bus master devices, and reference numeral 430 is a slave device. The bus master devices 410 and 420 and the slave device 430 are connected to the system bus 400 via connection lines 411, 421, and 431, respectively. As in the first embodiment, this method does not limit the type and number of devices to be connected.

  FIG. 6 shows the connection relationship between the system bus 400 itself and the system bus 400 and the connection lines 411, 421, and 431. The connection line 411 that connects the bus master device 410 and the system bus 400 includes 510 request control lines, 511 read / write designation control lines, 512 address lines, 513 write data lines, 514 read data lines, and 515 requests. It is comprised by the acceptance notification line, and the meaning of each signal line 510-514 respond | corresponds to 210-214 of Example 1. FIG. A signal line 515 indicates whether or not the request from the request control line 510 has been accepted. The connection line 421 that connects the bus master device 420 and the system bus 400 has the same configuration as the connection line 411.

  The connection line 431 that connects the slave device 430 and the system bus 400 includes 530 request control lines, 531 read / write designation control lines, 532 address lines, 533 write data lines, and 534 read data lines. The meaning of each signal line corresponds to 230 to 234 in the first embodiment.

  Reference numeral 540 denotes a request signal selector (switch) control circuit. Request control lines 510 and 520 and address lines 512 and 522 are inputted, and selector control signals 541, 542 and 543 and a request control line 530 are outputted. When the selector control signal 543 output from the control circuit 540 is “L”, the read / write designation control line 511 is output to the read / write designation control line 531. On the other hand, when the selector control signal 543 is “H”, the control line 521 is output to the control line 531.

  Similarly, 512 or 522 is output to the address line 532 according to the selector control signal 542, and 513 and 523 are output to the data line 533 according to the selector control signal 541, respectively. In this way, the connection between the bus master devices 410 and 420 and the slave device 430 is switched. With this configuration, the system bus 400 can be operated at high speed.

  FIG. 7 is a diagram showing an internal configuration of the control circuit 540. Reference numeral 600 denotes a decoder, which outputs “H” to the signal line 601 when the value of the address line 522 indicates the slave device 430. Therefore, when a request from the bus master device 420 is issued to the slave device 430, the selector outputs a control signal on the 420 side to the control signals 541, 542, and 543.

  The decoder 600 outputs “H” to the signal line 602 and “L” to the signal line 525 when the value of the address destination 522 does not indicate the slave device 430, and to the signal line 602 in the opposite case. “L” and “H” are output to the signal line 525.

  Reference numeral 610 denotes an unauthorized address access detection unit. Reference numerals 611 and 612 denote registers, and reference numerals 613 and 614 denote comparators. The circuit of the illegal address access detection unit is equivalent to 320 in the first embodiment, and the signal line 617 is “H” when the value of the address line 512 is within the range specified by the register 611 and the register 612. " The registers 611 and 612 can be read and written through the signal line 411.

  Reference numeral 620 denotes an unauthorized address access blocking unit, which is equivalent to 330 in the first embodiment, and masks the request control line 510 when the output of the signal line 617 is “L”. Thereby, unauthorized address access from the bus master device 410 can be blocked. Further, the signal line 602 is masked by the output of the signal line 617 to notify the bus master device 410 that the illegal address access is blocked. In response to the notification, the bus master device 410 performs exception processing and the like.

  As described above, since the bus master devices 410 and 420 are always accessed by the slave device via the selector of the system bus 400, the illegal address blocking circuit of the present invention only needs to be provided in the selector control circuit, and the area is reduced. be able to.

  FIG. 8 shows an example of a specific processor PC to which the present invention is applied. The processor PC includes a central processing unit CPU that controls the entire processor PC. The MMU included in the central processing unit CPU has a function of converting a virtual address in the CPU core to a physical address and blocking illegal address access. In the processor PC in this embodiment, the central processing unit CPU, the direct memory access controller DMAC, the image processing dedicated IP (device) MPEG4, and the audio dedicated processing IP (device) MP3 constitute a bus master device. External access by the processor PC is performed by an external bus interface circuit EXIF connected to the bus state controller 5 through an internal bus IBUS. The external bus interface circuit EXIF is connected to the external memory MEM. The bus state controller BSC outputs strobe signals RAS, CAS, a write enable signal WE, and the like for the memory MEM provided outside.

  The processor PC includes a clock pulse generator CPG, an interrupt control circuit INTC, a serial communication interface controller SCI, a real-time clock circuit RTC, and a timer TMU as built-in peripheral circuits connected to the internal bus IBUS. These peripheral circuits are accessed by the central processing unit CPU or the direct memory access controller DMAC, the image dedicated processing device MPEG4, and the audio dedicated processing device MP3 via the internal bus IBUS. The clock pulse generator CPG outputs a clock signal synchronized with the system clock. The processor PC performs operations such as fetching data from the outside in synchronization with the system clock signal.

  The bus state controller BSC determines an access data size, an access time, and a wait state in accordance with an access target circuit (address area to be accessed) by the central processing unit CPU and the direct memory access controller DMAC, and external memory MEM. Control bus access to. Further, the bus state controller BSC arbitrates contention between the direct memory access controller DMAC and external bus use requests.

  Here, the internal bus IBUS has a bus format. Accordingly, the central processing unit CPU and the dedicated image processing device MPEG4, the dedicated audio processing device MP3, and the direct memory access controller DMAC which are bus master devices are provided with the unauthorized access blocking circuit IABU according to the present invention. As a result, it is possible to block unauthorized address access with a small amount of circuit, and it is expected to prevent product defects due to software bugs and to detect them early. When the internal bus IBUS is switched, unauthorized access can be prevented by providing an unauthorized access blocking circuit on the internal bus IBUS, and it is not necessary to provide an unauthorized access blocking circuit in the direct access memory controller DMAC or the like. Can be reduced.

  In recent circuit design, each device (CPU, DMAC, etc.) is designed in advance and registered in the design tool as an IP, and among the devices registered at the time of circuit design, a device necessary as a product is displayed on the design tool. A single LSI circuit is designed by combining them. In this case, the illegal address blocking circuit of the present invention can be easily realized by registering it in a design tool or the like as one IP and connecting the registered illegal address blocking circuit between each device and the system bus. it can.

  FIG. 9 shows a second embodiment of a processor to which the present invention is applied. 8 is different from FIG. 8 in that a peripheral bus PBUS to which peripheral circuits are connected is provided separately from the internal bus IBUS. The internal bus IBUS and the peripheral BUS are connected via a bus state controller BSC. With this configuration, the peripheral circuit as a slave device is connected to the bus master device via the bus state controller BSC including the direct memory access controller DMAC. Since the processor PC in FIG. 8 is configured to directly access the peripheral circuit via the internal bus IBUS, an unauthorized access blocking circuit needs to be provided for each slave device in each bus master device. In the embodiment, since the peripheral circuit is connected to the bus master device via the bus state controller, the unauthorized access blocking circuit can be integrated in the bus state controller, and the area of the processor PC is reduced compared to FIG. It becomes possible.

  As described above, the present invention has been described based on the embodiments, but various modifications can be made without departing from the scope of the purpose of the present application. For example, a hard-wired configuration may be used without providing a register that specifies an address range.

DESCRIPTION OF SYMBOLS 100 ... System bus 110, 120 ... Bus master device 130 ... Slave device 113, 123 ... Unauthorized address access blocking mechanism 320 ... Unauthorized address access detection unit 330 ... Unauthorized address access blocking unit 321, 322 ... Access permission range setting register 323, 324 ... Comparator 400 ... System bus 410, 420 ... Bus master device 430 ... Slave device 540 ... Request signal selector control circuit 600 ... Address decoder 610 ... Illegal address access detection unit 620 ... Illegal address access blocking unit 611,612 ... Access permission range setting register 613, 614 ... Comparator CPU ... Central processing unit MPEG1,2 ... Image dedicated processing unit BSC ... Bus state controller DMAC ... Direct memory access controller Roller WDT ... watch dog timer INTC ... interrupt control circuit,
SCI, SCIF ... Serial interface communication controller TMU ... Timer RTC ... Real time clock CPG ... Clock pulse generator EXIF ... External memory interface MEM ... External memory MMU ... Memory management unit IABU ... Illegal address access blocking circuit IBUS ... Internal bus PBUS ... Peripheral bus

Claims (13)

A first bus master device;
A second bus master device;
A first slave device;
A connection control circuit connected to the first bus master device, the second bus master device, and the first slave device;
The first bus master device is capable of write access for writing data to the first slave device and read access for reading data,
The connection control circuit includes a selector for selecting a connection state between the first bus master and the first slave device, and a selector control circuit for controlling the selector.
The selector control circuit includes a decoder and an illegal address access blocking circuit,
The decoder and the illegal address access blocking circuit operate in parallel,
The decoder decodes a predetermined signal and outputs a signal for controlling the selector;
The illegal address access blocking circuit detects whether the access of the first bus master device is normal or illegal when the first bus master device accesses the first slave device. A semiconductor device that enables access from the first bus master device to the first slave device, and blocks access from the first bus master device to the first slave device when the access is illegal. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the illegal address access blocking circuit includes a range setting register for setting an access prohibition range, and determines that the address is illegal when the address to be accessed is within the access prohibition range. The semiconductor device according to claim 2,
The range setting register includes a first register that holds an upper limit address of an address assigned to the first slave device, and a second register that holds a lower limit address.
The first illegal address access blocking circuit further includes a comparison circuit for comparing whether an address output from the first bus master device is included in an address range indicated by the first register and the second register. Semiconductor device. The semiconductor device according to claim 3,
The illegal address access blocking circuit blocks access when the first address sent from the first bus master device is in a range where access is prohibited,
The decoder outputs a selector control signal to the selector according to a second address sent from the second bus master device, and the selector selects the first slave device and the first bus master device or the second bus master device. A semiconductor device characterized by switching the connection. A first bus master device;
A first slave device;
A bus connected to the first bus master device and the first slave device,
The first bus master device can be accessed including a write access for writing data to the first slave device or a read access for reading data,
The first bus master device has a first illegal address access blocking circuit;
The first illegal address access blocking circuit detects whether the access of the first bus master device is normal or illegal when accessing the first slave device, and when normal, the first bus master device A semiconductor device characterized in that access from a device to the first slave device is permitted, and access from the first bus master device to the first slave device is blocked when the device is illegal. The semiconductor device according to claim 5,
The first illegal address access blocking circuit includes a range setting register for setting an access prohibition range, and determines that the access address is illegal when the address to be accessed is within the access prohibition range. . The semiconductor device according to claim 6,
The range setting register includes a first register that holds an upper limit address of an address assigned to the first slave device, and a second register that holds a lower limit address.
The first illegal address access blocking circuit further includes a comparison circuit for comparing whether an address output from the first bus master device is included in an address range indicated by the first register and the second register. Semiconductor device. The semiconductor device according to claim 7,
The semiconductor device according to claim 1, wherein the first and second registers hold a number of bits equal to a number of bits of an address output from the first bus master device. The semiconductor device according to claim 8,
The semiconductor device according to claim 1, wherein the first and second registers hold a bit number smaller than a bit number of an address output from the first bus master device. The semiconductor device according to claim 9,
The semiconductor device further includes a second slave device connected to the bus, and is capable of permitting or denying access from the first bus master device to the second slave device,
When the first bus master device accesses the second slave device, the first bus master device detects whether the access of the first bus master device is normal or illegal, and when the access is normal, the first bus master device reads the first bus master device from the first bus master device. A semiconductor device, wherein access to a second slave device is permitted, and access to the second slave device from the first bus master device is blocked when the access is illegal. The semiconductor device according to claim 10,
The semiconductor device further includes a second bus master device connected to the bus,
The second bus master device can be accessed including a write access for writing data to the first slave device or a read access for reading data,
The second bus master device has a second illegal address access blocking circuit;
The second illegal address access blocking circuit detects whether the access of the second bus master device is normal or illegal when accessing the first slave device, and when normal, the second bus master device A semiconductor device characterized in that access from the device to the first slave device is permitted, and access from the second bus master device to the first slave device is blocked when the device is illegal. The semiconductor device according to claim 5,
The semiconductor device according to claim 1, wherein the first bus master device is a CPU, an image processing IP, or an audio processing IP. The semiconductor device according to claim 11,
The semiconductor device according to claim 1, wherein the first bus master device and the second bus master device are a CPU, an image processing IP, or an audio processing IP.

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